Device and Bias selection

The block diagram and power budget of this PA are shown in Fig. 2.4. The input/output matching network are realized by transformers. In the initial power budget, the estimated insertion loss of matching network is assumed to be 1.5 dB. Therefore, the saturated output power of each power cell should be higher than 16.5 dBm. In the power amplifier design, selection of device size is directly related to the target output power.

From the load-line theory [10], the output saturated power of the PA can be expressed as the following: recommended AC voltage swing (Vpp) is twice of dc supply voltage. Furthermore, the Vk

is the threshold voltage which is about 0.3 V in the 65-nm CMOS technology, as shown

in Fig. 2.5. Because the proposed PA is designed for Class-F^-1 operation, the gate bias voltage (Vgs) should be selected at Class-C operation. However, the bias selection is also related to the AM/PM distortion of the power amplifier design. Moreover, the detailed analysis will be discussed in this part. As a result, the operating condition of the proposed PA is decided at deep Class-AB. For a target Psat of 16.5 dBm (44.67 mW), a total dc current of 85.1 mA can be calculated in the Class-AB operation (Vg 0.6 V). Fig.

2.6 demonstrates the curve of transistors with different gate width per 32 fingers.

According to this figure, the current density of the device is roughly 0.28 mA/m in the same biasing region. As a result, the total gate width of is 358 m determined for the power stage design.

Fig. 2.5 The DC-IV curve versus different gate bias with the device of 64-m total gate width.

Fig. 2.6 The Id versus Vgs with different gate width

For the total gate width of 358 m, choosing multi-finger and multi-way combing transistors is commonly used to decrease the intrinsic gate resistance with the same total device size. Table 2.2 compares the load-pull simulations of a differential power cell which consist of different finger, gate width per finger, and numerous of transistors with the same total size. The results show that combining more transistors and using more fingers of the device can reach better performance of intrinsic peak PAE with roughly the same Psat. Nonetheless, the input impedance of amplifier would become smaller due to shunting all of the input conjugate impedance by combing numerous devices. As a result, it places large burden on the design of input matching network. To sum up, each differential power cell is built by combing four transistors as a unit and each size of transistors is 1.4 m × 32 fingers.

Table 2.2 Load-pull simulation of different conditions of the same total device size.

For continuous Class-F^-1 PA design, the bias condition should be chosen at closed to Class-B operation. However, bias voltage is one of critical parameters for the power amplifier design. Simulated PAE with different Vg at different output power levels is shown in Fig. 2.7. For the transistors biasing at deep Class-AB mode, higher back-off efficiency is demonstrated compared with the device biasing at Class-A due to smaller dc drain current at the low power region. Therefore, the bias condition of this PA is chosen at 0.4 V to exhibit higher PBO efficiency. However, the AM-AM and AM-PM distortions are also related to bias condition of the power amplifier. The AM/AM distortions versus Vgs with different output power level at 38 GHz is shown in Fig. 2.8.

Thanks to the positive gm3 of the device, the transistor biasing at triode region exhibits superior AM/AM distortion compared with the transistor biasing at saturated region.

Although PA biased at 0.4 V demonstrates better PBO efficiency, a worse AM-AM distortion is also observed. Prior works [11],[12] show that the AM/PM distortion is related to the nonlinearity of input capacitance variation at different input power level.

The equivalent circuit of small signal transistor model is shown in Fig. 2.9. For the common source transistors, the parasitic elements at the gate can be considered as a first-order low-pass RC circuit. Since the parasitic capacitor Cgs depends on the Vgs of the device, the output current at the drain of transistors Iout can be expressed as follows

[27]:

where ₂ represents second-order voltage dependence of Cin. As a result, the phase of output current contains an input-dependent term which is related to the capacitance Cin. When the input power level becomes higher, the large variation of Cin will increase₂ in the equation (2.4) which causes sever AM-PM distortion. Both parasitic capacitance Cgs and Cgd are main factor of input capacitance Cin. Gate to source parasitic capacitance Cgs versus different bias condition is shown in Fig. 2.10. The value of Cgs has higher variation around 0.3 V which will degrade AM-PM distortion of PA. Besides, there is an equivalent capacitance of (1-Av)×Cgd at the gate of the device owing to the Miller effect, where Av is voltage gain of the transistor. In the high input power region, output voltage will contain several harmonic distortion signals which leads to a severe nonlinearity of ttttt

Fig. 2.7 Simulated PAE with different Vg at different output power levels.

Fig. 2.8 AM/AM distortions versus Vgs with different output power level.

Fig. 2.9 The equivalent circuit of small signal transistor model.

Fig. 2.10 Simulated Cgs at different bias condition.

Fig. 2.11 Cin versus output power with different bias condition.

Fig. 2.12 AM/PM distortions versus Vgs with different output power level.

(1-Av)×Cgd. Therefore, considering the above problems, input parasitic capacitance Cin

versus input power with different bias condition is shown in Fig. 2.11. Besides, Fig.

2.12 shows AM/PM distortion at different output power level under different bias condition. Device biasing at the Vgs of 0.5 V has smaller variation of input parasitic capacitance which causes lowest AM/PM distortion. There is an AM-PM distortion up to 8^oof transistors biased at 0.4 V. In conclusion, this proposed PA is biased at 0.4 V to increase PBO efficiency, while also to degrade the AM-AM and AM-PM distortion of the PA.