Chapter 1 Introduction
1.2 The Motivation of this Work
Recently, random telegraph noise has been regarded as a serious concern for CMOS device scaling. It is caused by the capture and emission of charge carriers in the gate oxide traps and results in severe Id fluctuation as shown in Fig. 1.1 (a), and threshold voltage shift as shown in Fig. 1.1 (b). Due to its strong dependence on device dimension, it is predicted that RTN amplitude will grow with device scaling more rapidly than that the Vth variation caused by random dopant fluctuation. Therefore, new methods for measuring and modeling RTN are necessary to gain more understanding of the statistics of RTN as a function of bias and device size. Moreover, the impact of RTN on the reliability of circuit operation such as SRAM read/write stability is not negligible even for the 40 nm generation. Because the multi-level RTN will increase the switching amplitude, it is more likely to cause system failure [1.9] as shown in Fig. 1.2. However, due to the complex switching mechanisms of multi-level RTN, it is difficult to analyze this phenomenon. For the purpose of analyzing this phenomenon, we develop a simple and useful method which enables the multi-level RTN reduces to two-level RTN, as shown in Fig. 1.3. Additionally, stress-induced RTN [1.10] is another big issue in this study. In this work, we compare the traps distribution between planar devices and trigate devices as shown in Fig. 1.4 (a) and Fig. 1.4 (b). Besides, we compare the fresh devices and stressed devices. Finally, we are
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interested in the impact of RTN on trigate SRAM. In order to enhance the SRAM operation speed, the larger supply voltage is used often. However, the larger supply voltage might cause the device stressed and induce the RTN signals. It will reduce the RSNM and even induce failure of the transition in butterfly curves.
1.3 Organization of the Thesis
In this thesis, we will focus on the device variation which is caused by RTN-traps, because RTN-traps induce threshold voltage shifted severely. To discuss the correlation between trap position and ID variation, we develop a new method to profile traps distribution. Then we measured the SRAM circuits to analyze the impact of RTN traps on the circuits. Moreover, we use different stress methods to control the generated traps.
Through the different stress method, the trap positions can be controlled successfully.
In Chapter 2, we introduce the profiling methods and the extracting method of the RTN-trap positions. Besides, we describe the basic properties of RTN, the process flow, and the operation principle. Afterwards, we introduce the CMOS devices used in our study.
In Chapter 3, we compare the bulk planar devices with the bulk trigate devices in both fresh condition and stressed condition to identify the effect of process-induced RTN traps and stress-induced RTN traps. In Chapter 4, we demonstrate the applications of the result
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we reported in chapter 3. The applications include the influence of multi-level RTN on SRAM cell with the trigate devices and the planar devices by the manipulation of RTN-trap positions. Finally, the summary and conclusions are given in Chapter 5.
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τ c
∆I D
τ e I D
Time
(a)
(b)
Fig. 1.1 (a) Carrier trapping and detrapping by the slow trap near the drain side.
(b) Illustration of the three parameter of the RTN noise: capture time τc, emission time τe, and current amplitude ΔID.
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2.1 2.2 2.3 2.4
210 220 230 240
level4 level3 level2
I d (n A )
Time(second)
level1
Fig. 1.2 The schematic diagram of Multi-level RTN.
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2.80 2.85 2.90 2.95
96 98 100 102
I d (n A )
Time(second)
9mission time, τe
Capture time, τc
Ca pt ur e
9m iss io n
Fig. 1.3 A Two-level RTN schematic diagram.
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(a)
(b)
Fig. 1.4 (a) Convention planar MOSFET. (b) Trigate structure MOSFET.
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Chapter 2 Profiling Method- Theory and Experiment Setup
2.1 Introduction
Recently, random telegraph noise has been regarded as a serious concern for scaling of CMOS devices. Due to its strong dependence on device dimensions, it is predicted that RTN amplitude will grow with device scaling more rapidly than the Vth variation caused by random dopant fluctuation. RTN is believed to be originated from the traps at the Si/SiO2 interface through the process of capture and emission of charge carriers in the channel, leading to switch current between two or multiple levels [2.1]. Based on the temperature and voltage dependence of single charge effect, an analytical model for tunneling mechanism is developed and traps parameters are extracted [2.2], including the trap depth and the trap energy.
Recently, the charge pumping measurements has been utilized to characterize trap properties. However, the charge-pumping current may be too small to be reliably measured in small-size devices at a lower frequency required. Besides, the charge-pumping current may contain gate leakage as devices are stressed or heavily destroyed even when wear out or soft breakdown happens. In this chapter, we demonstrate a new method of extracting the
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trap positions with 2-D distribution in the oxide layer. This method includes the lateral profiling and the longitudinal profiling. To extract the trap depth, the mechanism of RTN should be understood. Because the trap depth is relate to time constant, capture time (τc) and the emission time (τe). Through the slope of ln(τc/τe) versus VG, the trap depth could be extracted. Besides, we utilize the barrier peak in the channel direction to probe the trap position. RTN signals are the most sensitive at the barrier peak. By increasing source-to-drain voltage, VSD, the barrier peak will be shifted from the middle of channel to the drain side, and the correct position can be extracted. Therefore, the position of RTN signals can be extracted in channel direction.
2.2 Profiling Method in Two Dimension
2.2.1 General Equation of the Trap Depth
Figure 2.1 (a) shows the schematic diagram of RTN (random telegraph noise) noise with drain current fluctuation. The probability of a transition from the high current state to the low current state is given by 1/τe. Similarly, the probability of a transition from the low current state to the high current state is 1/τc. ET in thesis is the energy of the trap, and the EF is Fermi energy for electrons. Based on the principle of detailed balance, the average emission time is given by [2.3]:
. (2.1)
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Here, k is the Boltzmann constant, T is the temperature, τc and τe are average capture time and emission time, respectively, and g is the degeneracy factor. Therefore, let g = 1;
. (2.2)
where ECox is the conduction band edge of the oxide, EC is the conduction band edge of
silicon, φo is the difference between the electron affinities of Si and SiO2, VFB is the flat-band voltage, φs is the amount of band-bending, ZT is the position of the trap in the
oxide measured with respect to Si-SiO2 interface, Tox is the oxide thickness, VGS is the gate-source voltage, and q is electronic charge. The right-hand side of Eq. (2.2) represents the difference between trap energy level and electron’s Fermi level. We can easily recognize the energy difference from Fig. 2.2.
By differentiating (2.2) with respect to VGS, the position of the trap in the oxide ZT
can be obtained by the following equation:
. (2.3)
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2.2.2 Lateral Profiling Method
Because the RTN signals are more sensitive to the peak of the channel potential barrier, and the barrier peak is dependent on the source-to-drain voltage; the trap position in the channel direction can be defined. Fig. 2.3 shows the barrier peaks fluctuated by oxide traps. The emission/capture charge on the local trap causes barrier peaks raised/suppressed directly, and the drain current would suffer from the barrier scattering seriously. By increasing source-to-drain voltage, the barrier peak will be shifted from the middle of the channel to the drain side. The relation between source-to-drain voltage and the position of barrier peak cane be derived as below:
(2.4)
. (2.5) where Ypeak is the position of barrier peak at given VDS, Y0 is the barrier peak at VDS = 0.05V, Leff is the effective channel length, ΔL is depletion region length at given VDS; which used to adjust the channel length, S.S.0 is the subthreshold Id swing at VDS = 0.05V, S.S. is the subthreshold Id swing at given VDS, Vbi is junction barrier between source and channel, Vc,max is barrier heigh of long channel, as shown in Fig. 2.4.
To extract the trap position, we extract Vbi , Vc,max , and ΔL experimentally.
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2.3 Device Preparation and Experimental Setup
2.3.1 Device preparation
The 28nm technology node of the bulk trigate CMOS devices with poly-Si gate made on a pilot foundry platform, with EOT(SiO2)= 20Å were prepared as shown in Figs.
2.5. Also bulk-planar devices on the same technology node were made for comparisons as shown in Figs. 2.6.
2.3.2 Experimental Setup
The experimental setup for the current-voltage measurement of devices is illustrated in Fig. 2.7 and Fig. 2.9, respectively. Each of the analyzers is connected by the co-axial or tri-axial cable including the semiconductor parameter analyzer (HP 4156C) as shown in Fig. 2.7. In order to suppress the noise of transport, we connect the parameter analyzers directly without switch mainframe, while the RTN signal is measured, as shown in Fig. 2.8.
The Cascade guarded thermal probe station, and a thermal controller. This facility provides an adequate capability for measuring the low leakage devices MOSFET characteristic.
Therefore, our group developed a control system in HT-Basic language. Through
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IEEE-488 (GPIB) cable, we can directly give the order to each analyzer. From the above system, the I-V and C-V characteristics of the MOSFET devices can be precisely performed.
While measuring the RTN signal, we set the interval time and the total measure points in the beginning. Then, to calculate both the high level state time and the low level state time of Id, we can get the average τc and τe . In this experiment the gate voltage is biased at Vth versus different VDS. Through the ID-VG curve the Vth can be extracted.
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τ c
∆I D
τ e I D
Time
(a)
(b)
Fig. 2.1 (a) Illustration of the three parameter of the RTN noise: capture time τc, emission time τe, and current amplitude ΔID. (b) Carrier trapping and detrapping by the slow trap near the drain side.
Trap
Capture Emission
Source Drain
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E c
E v E F φ o
E C,ox - E T
Z T
q Ψ s
q Ψ p
SiO 2
Si Poly Si
Fig. 2.2 The energy band diagram of the Si-SiO2 interface in the channel at the trap location.
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Fig. 2.3 Oxide trap RTN induce barrier peak fluctuate: Vth variation is dominated by the trapping or de-trapping in the oxide layer trap.
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Fig. 2.4 A new model is to approximate the carrier peak in the channel as a second degree curve, in which the peak position can be determined by the DIBL.
Gate
S D
y
ΔL + L”
eff= L
effV
bi0
V
c,maxV
c(V
sd)
DIBL
Y
0Y
peak20
Y Y +
Y + Poly Gate Y
STI STI
Oxide
Cha nne l
Fig. 2.5 (a) The 3D schematic of bulk trigate device used in this work. (b) The cross-section from Y to Y+ of trigate device.
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S D
Poly Gate
Bulk planar devices
Fig. 2.6 The bulk planar MOSFET devices made for comparisons.
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Fig. 2.7 The experimental system of current-voltage (I-V) for both n-type or p-type MOSFET.
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Parameter Analyzer HP 4156C
PC
Probe Station
Fig. 2.8 The measurement setup using Analyzer HP 4156C to do the sampling of RTN signals.
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Substrate
Source Drain
V
GSV
DSGate
Poly
Oxide
Fig. 2.9 The terminals setup for the sampling using HP4156C Analyzer.
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Chapter 3 Influence of Multi-level RTN in Trigate MOSFET
And the Distribution of Oxide Trap Through 2-D Profiling
3.1 Introduction
As Intel co-founder Gordon Moore’s bold prediction, popularly known as Moore's Law, states that the number of transistors on a chip will double approximately every two years. Electrical engineer which has maintained this pace for decades, this golden rule as both a guiding principle and a springboard for technological advancement, driving the expansion of functions on a chip at a lower cost per function and lower power per transistor by introducing and using new materials and transistor structures. As VLSI scales toward 22nm node, the leakage and variation are intolerant in the planar devices. Therefore, finFET structure had been proposed since 1999 and been mass produced recently.
However, there are several problems not solved in FINFET device, and RTN is one of the most important variation sources.
In this chapter we dedicated to profile the distribution of RTN traps to explain the influence of trap positions. In order to understand the difference between the planar
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devices and the trigate devices, we used two kinds of devices in this experiment separately.
On the other hand, we took the devices under stressed condition and fresh condition while measurement, to understand the difference between processing induced RTN and stress induced RTN. Since finFET devices just began to be used on mass product recently, the device quality was not very stable. Devices with defect might induce circuit failed and power consumption. Through this study, we can realize the drawbacks of produce process and improve the procedure.
3.2 Experimental
3.2.1 Process Induce RTN Trap
Figure 3.1 shows the result of a RTN trap in the planar pMOS device. According to our experiment, the trap distribution is a Gaussian-like shape. To understand the reason of Gaussian-like distribution, we examine Eq. 3.1 and Eq. 3.2 below.
The depth of RTN traps can be extracted from Eq. 3.2, and the trap depth is related to
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the trap energy, ET. However, the trap energy is a distribution rather than a constant. The trap distribution is dependent on the channel position.
The difference between oxide trap energy level and Fermi level is changed by gate voltage and determines the ratio of capture time and emission time. Through physical methodology, we can find the relationship between time constants and trap energy and Fermi level with trap depth.
Fig. 3.2 is the result of RTN traps in the planar nMOS devices. The figure demonstrates that there are two traps in the planar nMOS device. From the profiling result, the different depths of two traps can be observed easily in this profiling method. We also observed that the two traps interact in the middle of them. To discuss the profiling result, we can examine the ΔID /ID curve as shown in Fig. 3.3. Depending on the trap location, 3 cases of RTN signal can be observed in the ΔID /ID curve, from which the case 1 and the case 3 are two-level signals, but the case 2 is four-levels in the interaction region because the barrier peak is affected by the two overlapping traps.
Figure 3.4 shows the profile of single RTN trap in a trigate pMOS device, and Fig. 3.5 shows the profile of a bulk-trigate nMOS device. By comparing the trap profiling results of bulk-trigate devices with the planar devices, the broader distributions can be observed in both nMOS devices and pMOS trigate devices. From the result, we make an assumption that the deeper RTN trap might induce boarder distribution. Fig. 3.4 shows the single trap
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profile, and Fig. 3.5 shows the profile of two RTN traps without overlapping. Comparing Fig. 3.2 and Fig. 3.5, we realize that if the two traps separate far enough, the signals are always two-levels. Because both traps are not overlapped, no 4-level RTN is observed. On the other hand, if the two traps are so close that the trap energy overlapped thus it will induce four-level RTN signals in the overlapped region.
By differentiating equation 3.1 with VGS, the position of the trap in the oxide is conventionally obtained. Fig. 3.6 shows positive dependency of ln(τc/τe) on VGS for planar devices and negative dependency for trigate devices. The RTN-traps in the trigate devices tend to exchange with gate, but the RTN-traps in the planar devices tend to exchange with channel. Because the trap depths in the trigate devices are deeper than that in the planar devices as shown in Fig. 3.7. As a result, Fig.13 outlines the information of process induced RTN traps.
We also got the cross-sections of RTN traps by examining the profiling result. Fig. 3.9 compares the cross-sections of RTN traps with reported data [3.1], [3.2], and theory value, showing good consistency.
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3.2.2 Stress Induce RTN Trap
Since SRAM is highly vulnerable to mismatch, and the devices might be stressed while operating; to understand the stressed devices impact on circuits is important. To understand the behavior of post-stressed SRAM, we utilize different stress mechanisms, hot carrier (HC) stress and NBTI stress for the nMOS devices and the pMOS devices respectively. HC means carriers gain enough energy to enter the conduction band. We used drain avalanche to get the hot carrier. This occurs when a high drain voltage is applied under non-saturated conditions, and results in the very high electric fields near the drain, which accelerates channel carriers into the drain's depletion region. Studies have shown that the worst effects occur when VD = 2VG. Instead of HC stress, we utilize NBTI stress for pMOS devices. In the sub-micrometer devices nitrogen is incorporated into the silicon gate oxide to reduce the gate leakage current density and prevent the boron penetration. However, incorporating nitrogen enhances NBTI. It is possible that the interfacial layer composed of nitride silicon dioxide is responsible for those instabilities. This interfacial layer results from the spontaneous oxidation of the silicon substrate. To limit this oxidation, the silicon interface is saturated with nitrogen resulting in a very thin and nitride oxide layer. In the case of NBTI, it is believed that the electric field is able to break Si-H bonds located at the Silicon-oxide interface. H is released in the substrate where it migrates. The remaining
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dangling-bond contributes to the threshold voltage degradation.
Figure 3.10 shows the result of HC-induced two traps in the planar nMOS devices. As people know, the carrier energy is usually raised on the high field region. The depletion region is the region of the highest electric field. Therefore, HC-induced traps tend to cluster in near drain region closely. From our research before, we got a conclusion that different RTN traps might interact with each other, if the energy band overlaps. Therefore, the profile of RTN traps after HC stressed is three regions separately, including the left-trap region, the right-trap region, and the overlapped region. Because these two RTN signals are quite different, it is beneficial to analyze. Otherwise, the RTN signal would become mess and hard to be analyzed. Fig. 3.11 shows the ID RTN signals of these separate regions. In the overlap region, the ID RTN signal is raised to a 4-level RTN obviously.
Figure 3.12 shows the result of NBTI-induced RTN traps in the planar pMOS devices.
The RTN traps tend to be generated in the middle of channel, because NBTI-stress bias on VG=-2V only, and without VD bias.
After the experiment upon, the stress condition the trigate devices we used on is similar to that we used on the planar devices. Fig. 3.13 shows HC stress in trigate nMOS devices.
The similar trap distribution can be observed on Fig. 3.11 and Fig. 3.13. Although the bulk-trigate structure and the bulk-planar structure are different, HC-induced RTN traps are usually generated in the vicinity of drain region. It is because the contribution of the
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highest field is there. Likewise, we use NBTI stress in the trigate pMOS devices. Fig. 3.14 shows the profiling result of NBTI-induced RTN traps, and the two fully-overlapped traps are observed. It is because these two traps located in the same position in channel direction, but the vertical positions are different. Besides, we find that these two traps exclude each other to induce three-level RTN. Fig. 3.15 (a) shows the schematic, these two traps are barely aligned together. When one trap is occupied, it will repulse the other to capture the carrier as shown in Fig. 3.15 (a) & (b).
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Oxide layer bulk planar pMOS device
L eff /W=28/120(nm)
Fig. 3.1 The profiling result of the process-induced single RTN in the bulk planar pMOS devices, showing a Gaussian-like profile. The insert is the ΔId/Id data of this RTN, confirming that there is only single RTN trap.