Stress Induce RTN Trap

Chapter 2 Theory of Profiling Method and Experiment Setup

3.2 Experimental

3.2.2 Stress Induce RTN Trap

Since SRAM is highly vulnerable to mismatch, and the devices might be stressed while operating; to understand the stressed devices impact on circuits is important. To understand the behavior of post-stressed SRAM, we utilize different stress mechanisms, hot carrier (HC) stress and NBTI stress for the nMOS devices and the pMOS devices respectively. HC means carriers gain enough energy to enter the conduction band. We used drain avalanche to get the hot carrier. This occurs when a high drain voltage is applied under non-saturated conditions, and results in the very high electric fields near the drain, which accelerates channel carriers into the drain's depletion region. Studies have shown that the worst effects occur when V_D = 2V_G. Instead of HC stress, we utilize NBTI stress for pMOS devices. In the sub-micrometer devices nitrogen is incorporated into the silicon gate oxide to reduce the gate leakage current density and prevent the boron penetration. However, incorporating nitrogen enhances NBTI. It is possible that the interfacial layer composed of nitride silicon dioxide is responsible for those instabilities. This interfacial layer results from the spontaneous oxidation of the silicon substrate. To limit this oxidation, the silicon interface is saturated with nitrogen resulting in a very thin and nitride oxide layer. In the case of NBTI, it is believed that the electric field is able to break Si-H bonds located at the Silicon-oxide interface. H is released in the substrate where it migrates. The remaining

dangling-bond contributes to the threshold voltage degradation.

Figure 3.10 shows the result of HC-induced two traps in the planar nMOS devices. As people know, the carrier energy is usually raised on the high field region. The depletion region is the region of the highest electric field. Therefore, HC-induced traps tend to cluster in near drain region closely. From our research before, we got a conclusion that different RTN traps might interact with each other, if the energy band overlaps. Therefore, the profile of RTN traps after HC stressed is three regions separately, including the left-trap region, the right-trap region, and the overlapped region. Because these two RTN signals are quite different, it is beneficial to analyze. Otherwise, the RTN signal would become mess and hard to be analyzed. Fig. 3.11 shows the I_D RTN signals of these separate regions. In the overlap region, the I_D RTN signal is raised to a 4-level RTN obviously.

Figure 3.12 shows the result of NBTI-induced RTN traps in the planar pMOS devices.

The RTN traps tend to be generated in the middle of channel, because NBTI-stress bias on V_G=-2V only, and without V_D bias.

After the experiment upon, the stress condition the trigate devices we used on is similar to that we used on the planar devices. Fig. 3.13 shows HC stress in trigate nMOS devices.

The similar trap distribution can be observed on Fig. 3.11 and Fig. 3.13. Although the bulk-trigate structure and the bulk-planar structure are different, HC-induced RTN traps are usually generated in the vicinity of drain region. It is because the contribution of the

highest field is there. Likewise, we use NBTI stress in the trigate pMOS devices. Fig. 3.14 shows the profiling result of NBTI-induced RTN traps, and the two fully-overlapped traps are observed. It is because these two traps located in the same position in channel direction, but the vertical positions are different. Besides, we find that these two traps exclude each other to induce three-level RTN. Fig. 3.15 (a) shows the schematic, these two traps are barely aligned together. When one trap is occupied, it will repulse the other to capture the carrier as shown in Fig. 3.15 (a) & (b).

Oxide layer bulk planar pMOS device

L _eff /W=28/120(nm)

Fig. 3.1 The profiling result of the process-induced single RTN in the bulk planar pMOS devices, showing a Gaussian-like profile. The insert is the ΔId/I_d data of this RTN, confirming that there is only single RTN trap.

Case2( trap a+ trap b) Case3( only trap b)

2.3nm 3.1nm

Fig. 3.2 The profiling result of process-induced multi-RTN in the bulk planar nMOS devices, showing 2 Gaussian-like packets, traps b & c. Note that we categorize this result into the Case 1, 2, and 3. For the Case 2, two packets are overlapped in tails.

6

Case3- trap c induced 2 level RTN

Case2- trap b & c induced 4 level RTN Case1- trap b induced b level RTN

Lv.3Lv.4Lv.2

DI d / I d (%)

^Lv.1

Time(sec)

Fig. 3.3 The result of the profiling of the process-induced two-RTN traps in the bulk trigate nMOS devices, showing 2 Gaussian-like waveforms, but both waveforms are not overlapped because of a large distance between them.

O xi de D ept h i n E .O .T .( A

) bulk trigate pMOS device L _eff /W=28/100(nm)

Fig. 3.4 The result of the profiling of the process-induced single-RTN in the bulk trigate pMOS devices, showing a Gaussian-like distribution.

Fig. 3.5 The result of the profiling of the process-induced two-RTN traps in the bulk trigate nMOS devices, showing 2 Gaussian-like waveforms, but both waveforms are not overlapped because of a large distance between them.

37 the positive dependency, but (right) the bulk trigate devices shows the negative dependency.

Fig. 3.7 From judging the RTN proofing data and ln(τc/τe) dependency, we conclude that (up) RTN of planar devices are near the interface between the oxide and Si; (down) RTN of trigate devices are near the interface between the oxide and poly-Si.

SiO ₂

Carrier Trap

PolySi Si sub.

SiO ₂

Carrier

Trap

PolySi

Si sub.

Fig. 3.8 Summarizes the information of process induced RTN in this work.

0 1 2 3 4

R adi us of c ros s- sec tion of R T N t rap( nm )

trap a b c d e f

ref.8 ref.9

Calculated screening length

this work

Fig. 3.9 The comparisons of the cross-section of the process-induced RTNs in this work. The reported data and the theoretical value show good consistency.

41 Case2( trap g+ trap h)

Case3

(only trap h)

2.8nm 3nm

Fig. 3.10 The result of the HC stresss-induced multi-RTN in bulk planar nMOS devices, showing 2 Gaussian-like packets, traps g & h with strong interference. We categorize this result into the Case 1, 2, and 3. For the Case 2, two packets are overlapped in tails.

0 100 200 300 400 500 600

-3.0 -1.5 0.0

150 180 210 240 270 300 -4

-2 0 2

160 170 180 190 200

-1.5 0.0 1.5 3.0

Case3- trap h induced 2 level RTN Case2- trap g & h induced 4 level RTN Case1- trap g induced 2 level RTN

Lv.4 trap-g induced RTN, and the Case 3 is the same for trap-h. But the Case 2 shows 4-level behavior composed by the trap-g & trap-h. Lvs.1 &2 are contributed from the trap-h, the others are from the trap-g.

Fig. 3.12 The result of the NBTI stress-induced single-RTN in the bulk planar pMOS devices, showing a Gaussian-like shape. Note that this shape distributes near the middle of the channel region.

Fig. 3.13 The result of the HC stress-induced single-RTN trap in bulk trigate nMOS devices, showing a bell shape. Note that this shape distributes near the region of drain side.

Fig. 3.14 The result of the NBTI stress-induced 2-RTN traps in bulk trigate nMOS devices. These two traps are totally overlapped in the shape and aligned on the same channel position with very close trap depths.

Trap k cannot trap another carrier.

Due to Coulomb repulsive force of the trapped trap, there is no Lv.4.

Carrier

Trap k trapped carrier.

Trap l cannot trap.

another carrier either

Fig. 3.15 (a) The 3 level RTN was observed in the Case 1 addressed in Fig. 3.14. There is no Lv.4, which two traps are overlapped. This is due to the fact that Coulomb repulsive force of a trapped trap rejects the trapping process of empty trap, (b) & (c).

Chapter 4 The Applications of Multi-RTN: The Impact on SRAM

Operation & The Manipulation of RTN-trap Positions

4.1 Introduction

In this chapter, we will be focused on the influence of device variation on circuits, especially for SRAM. As microprocessors and other electronic applications get faster and faster, the need for large quantities of data at very high speeds increases, while providing the data at such high speeds get more difficult to accomplish. Besides, the manipulation of RTN-trap positions has been demonstrated by utilizing different stress methods. It will reveal a new scenario of the discrete-bit storage on SONOS or nano-crystal memory cells in the future.

As microprocessor speed increases from 25 MHz to 1GHz and beyond, system designers have become more creative in their use of cache memory, interleaving, burst mode, and other high-speed methods for accessing memory. The old system sporting just an on-chip instruction cache, a moderate amount of DRAM and a hard drive have given way to sophisticated designs using multi-level memory architectures. One of the primary building blocks of the multi-level memory architecture is the data cache.

According to our previous research, RTN traps induced by excessive mechanical stress are correlated to leakage current in very high-density SRAM devices, especially multi-RTN, and it will degrade the RSNM severely.

Finally, we are interested in the manipulation of RTN-trap positions. In the previous study, we found that the RTN-trap position is dependent on the stress methods, and therefore, we may control the trap positions by the HC stress or the FN stress.

Hot-carrier emission is expected to be accelerated in the depletion region. Electrons gain energy through channel potential. While electrons get 3.2eV, it will be injected from the conducting band in the silicon substrate to the gate dielectric, and it is probable to break either a covalent or a Si-H bond randomly. Because the HC-stress will induce electron-hole pairs, by monitoring the substrate current, we can distinguish the extent of hot carriers. A high substrate current means a large number of created electron-hole pairs and therefore an efficient Si-H bond breakage mechanism. When interface states are created by HC stress, the threshold voltage is modified, and the subthreshold slope is degraded.

According to the principle of HC stress, it can be used to control the RTN traps generated at the drain edge. Moreover, the maximum electric field will be shifted toward the center of the channel by modifying the drain voltage, and the traps will be generated there. Through the profiling result, we found that the traps are generated at the region

between the channel middle and the drain edge actually. In the final part, we utilize the FN stress to generate RTN-traps in the center of channel. In the previous measurement result, we found that the RTN traps are located in the center of the channel through NBTI stress.

Hence, we consider that the electric field distribution of NBTI stress is similar to that of FN stress in nMOS devices. After the measurement, the manipulation of RTN-traps in the channel which is generated by different stress conditions has been observed.

4.2 The Basics of SRAM

4.2.1 SRAM Operations

The SRAM cell consists of a bi-stable flip-flop connected to the internal circuitry by two access transistors as shown in Fig. 4.1. When the cell is not addressed, the two access transistors are closed, and the data is kept to a stable state, latched within the flip-flop.The flip-flop needs the power supply to keep the information. The data in an SRAM cell is volatile. However, the data does not “leak away” like in a DRAM, so the SRAM does not require a refresh cycle.

Figure 4.2 shows the read/write operations of an SRAM. To select a cell, the two access transistors must be “on” so the elementary cell (the flip-flop) can be connected to

the internal SRAM circuitry. These two access transistors of a cell are connected to the word line (also called row or X address). The selected row will be set at V_CC. The two flip-flop sides are therefore connected to a pair of lines, B and . The bit lines are (also called columns or Y addresses). During a read operation, these two bit lines are connected to the sense amplifier that recognizes if a logic data “1” or “0” is stored in the selected elementary cell. This sense amplifier then transfers the logic state to the output buffer which is connected to the output pad. There are as many sense amplifiers as the output pads. During a write operation, data come from the input pad. It then moves to the write circuitry. Since the write circuitry drivers are stronger than the cell flip-flop transistors, the data will be forced onto the cell. When the read/write operation is completed, the word line (row) is set to 0V, the cell (flip-flop) either keeps its original data for a read cycle or stores the new data which was loaded during the write cycle.

4.2.2 Steady Noise Margin

The SRAM cell immunity to static noise is measured in terms of SNM that quantifies the maximum amount of voltage noise that can be tolerated at the cross-inverters output nodes without flipping the cell. The graphical method to determine the SNM uses the static voltage transfer characteristics of the SRAM cell inverters.

4.2.3 Impact of Multi-level RTN on SRAM

Figure 4.3 is a 6T SRAM and TEM picture. To study RTN impact on SRAM carefully, we defined two cases of multi-RTN traps generated in different transistors. The two cases including RTN traps are generated on the pull up transistor only, and RTN traps generated on both pull-up transistor and pull-down transistor, as shown in Fig. 4.4. Because the RTN signals induce the V_t disturbance, the V_t of device with RTN will become multi-level.

Figure 4.5 shows the butterfly curve of planar SRAM under the case 1, pull-up transistor with multi-RTN signals. It has been observed that the butterfly curves split into 4-levels (the insert). Fig. 4.6 shows the RTN signals measured in pull-up transistor, and 4-levels can be pointed out demonstratively. It is the reason for the butterfly curves split into 4-levels. The similar phenomena can be observed in the trigate SRAM. Fig. 4.7 shows the butterfly curves of the trigate SRAM also split into clear 4-level transition under the same case. Fig. 4.8 shows the I_D RTN signals measured in the pull-up transistor, and 4-levels can be demonstrated. Comparing the butterfly curves of the planar SRAM with the trigate SRAM, the butterfly curves of trigate SRAM separate widely. It is because the RTN amplitude of the trigate devices is larger than that of the planar devices. Fig. 4.9 shows the comparison of σRSNM between the planar devices and the trigate devices under the case 1.

From the figure, we realize that the σRSNM increases severely, due to the RTN generation

under the case 1. Besides, the σRSNM for trigate SRAM is much larger than the planar SRAM under this case. From the result of our research, we also found that σRSNM depends on the amplitude of RTN signals.

Figure 4.10 shows the butterfly curves of the planar SRAM under the case 2, M2 and M3 with multi-RTN. It has been observed that the butterfly curves translate fail because of RTN signals. Note that the insert shows a noticeable component of transition failure. Fig.

4.11 shows the results of multi-RTN induced trigate SRAM failure on transition, which is due to a wide V_t-shift of M3 raised by the trapping and de-trapping of multi-RTN traps.

When V_t is shifted by RTN process upon the trigger voltage of SRAM, the transition will be immediately failed, Fig. 4.12 The larger multi-RTN induced V_t shift is, the higher the probability of transition failure raises.

4.3 The Manipulation of RTN-trap Positions

Figure 4.13 shows the schematic of hot-carrier stress under V_G= V_D= 2V bias condition and indicates that the impact ionization region is close to the drain edge while the drain voltage is increased. Fig. 4.14 shows the measurement result of the hot carrier stress under this condition, and the traps profile is approached to the drain side actually.

Figure 4.15 shows the schematic of hot-carrier stress under V_G= 2V and V_D= 1.5V

condition and indicates that the impact ionization region is far from the drain edge while drain voltage decreased. Fig.4.16 shows the measurement result of hot carrier stress under this condition. It has been observed that the traps profile is located in the region between the channel middle and the drain edge. Fig. 4.17 shows the I_B-V_G curve. The hot carrier stress is caused by that electric field which accelerates electrons and induces electron-hole pairs, so monitoring the I_B curve is an indispensable way to identify the mechanism of stress induced RTN-trap. I_B/ I_D ratio shows the efficiency of hot carrier stress rate, and the largest the hot carrier stress rate has been observed at V_D= 2.5V.

According to the profiling result of NBTI stress, we utilize FN-stress to inject charge to the center of the channel. Fig. 4.18 shows the schematic of the FN stress. Fig. 4.19 shows the result of RTN-traps profiling under FN-stress. Because the electric field of

FN-stress is broader than that of the hot carrier stress, the wider distribution is observed.

Besides, two distinct traps are found. Fig. 4.20 shows the slopes of the ln(τc/τe) versus VG

curve. The totally distinct slopes have been observed that the positive dependency of ln(τc/τe) versus VG for trap A and negative dependency for trap B. Therefore, we consider

that there are two traps.

Fig. 4.1 The schematic of SRAM cell. The SRAM cell consists of a bistable flip-flop connected to the internal circuitry by two access transistors.

Fig. 4.2Read/write operations.

wl

bl

V _n

M2 M4

V _na

SRAM Cell

M3 M5

bla

M1 M6

V _dd

Fig. 4.3 (Top) The schematic of the SRAM circuit. (Bottom) The TEM view of SRAM.

V _n

M2 V _dd

V _na

V _dd

V _na V _n

M2 M3

Fig. 4.4 Two multi-RTN cases utilized to study the impact of multi RTN on SRAM.

Fig. 4.5 The butterfly curves of planar SRAM with multi-RTN in M2 device. Note that the branch (red) with RTN traps has more fluctuated than that without RTN trap (blue) one. The insert is the zooming up, in which clear 4 level characteristic is observed, corresponding to 4 level I_d RTNof M2 devices.

Fig. 4.6 As a result, RTN fluctuation degrades the RSNM of SRAM.

5.18 5.25 5.32

0.25 Lv.4 0.26

Lv.3 Lv.2

Time(sec)

I d R T N of M 2 dev ic e( uA ) Lv.1

Vna=0.75V, Vdd=1V

0.0 0.2 0.4 0.6 0.8 1.0

V na (v ol t)

Vn(volt)

Case 1 in Fig. 22 of trigate SRAM

Vdd=1V

RSba

Lv.1Lv.2 Lv.3Lv.4

Fig. 4.7 The butterfly curves of trigate SRAM with multi-RTN in M2 device. Note that the branch (red) with RTN traps has more fluctuation than that without RTN trap(blue) one.

Fig. 4.8 Clear 4 level characteristic is observed, corresponding to 4 level I_d RTNof M2 devices.

9 10 11

0.87 0.88 0.89 0.90 0.91

Lv.4 Lv.3

Lv.2

I d R T N of M 2 dev ic e( uA )

Time(sec)

Lv.1

Fig. 4.9 As a result of multi-RTN in the oxide of M2 devices, the variation of RSNM will increase astonishingly. Note that the variation of RSNM increases much larger in trigate devices than that of planar devices

.

0 10 20 30 40 50

planar SRAM with 4-level RTN in M2 device

planar SRAM without RTN in each discrete device trigate SRAM with 4-level RTN in M2 device

trigate SRAM without RTN in each discrete device

σRSNM(mV)

Fig. 4.10 The butterfly curves of planar SRAM with multi-RTN in M2 & M3 device.

Note that the red branch shows transition failure component (the insert) due to multi-RTN in M3&M2 device. This is a newly RTN induced SRAM failure mechanism.

Fig. 4.11 The butterfly curves of trigate SRAM with multi-RTN in M2 & M3 devices.

Note that the red branch shows transition failure component (the insert) due to multi-RTN in M3&M2 devices. This is a newly RTN induced SRAM failure mechanism.

V t RT N of M 2

V

_dd

-V

_dd

0 time

V t RT N of M 3

Failure of Transition

a ult i-le vel o f Tran sit ion

Fig. 4.12 The schematic to explain why multi-level transition and failure of transition in butterfly curves of SRAM. The RTN-induced Vt shift in M2 or M3 causes these abnormal transitions of curves.

Fig. 4.13 The schematic to indicate that vertical electric field is approach to horizontal electric field, therefore RTN-traps in this stress condition is near the drain side.

Fig. 4.14 The result of the HC stress-induced single-RTN trap in bulk planar nMOS devices, showing a bell shape. Note that this shape distributes near the drain side.

Fig. 4.15 The schematic to indicate that vertical electric field is approach to the horizontal electric field, therefore RTN-traps in this stress condition is near the drain side.

Fig. 4.16 The result of the HC stress-induced single-RTN trap in bulk planar nMOS

在文檔中運用隨機電報訊號方法分析三閘極電晶體的多層級氧化層陷阱 (頁 45-0)

Chapter 2 Theory of Profiling Method and Experiment Setup

3.2 Experimental

3.2.2 Stress Induce RTN Trap

Oxide layer bulk planar pMOS device

L eff /W=28/120(nm)

Case2( trap a+ trap b) Case3( only trap b)

2.3nm 3.1nm

6

DI d / I d (%)

Time(sec)

O xi de D ept h i n E .O .T .( A

) bulk trigate pMOS device L eff /W=28/100(nm)

SiO 2

Carrier Trap

PolySi Si sub.

SiO 2

Carrier

Trap

PolySi

Si sub.

0 1 2 3 4

R adi us of c ros s- sec tion of R T N t rap( nm )

trap a b c d e f

this work

2.8nm 3nm

0 100 200 300 400 500 600

-3.0 -1.5 0.0

150 180 210 240 270 300 -4

-2 0 2

160 170 180 190 200

-1.5 0.0 1.5 3.0

Due to Coulomb repulsive force of the trapped trap, there is no Lv.4.

Chapter 4 The Applications of Multi-RTN: The Impact on SRAM

Operation & The Manipulation of RTN-trap Positions

4.1 Introduction

4.2 The Basics of SRAM

4.2.1 SRAM Operations

4.2.2 Steady Noise Margin

4.2.3 Impact of Multi-level RTN on SRAM

4.3 The Manipulation of RTN-trap Positions

wl

bl

V n

M2 M4

V na

SRAM Cell

M3 M5

bla

M1 M6

V dd

V n

M2 V dd

V na

V dd

V na V n

M2 M3

5.18 5.25 5.32

0.25

Lv.4 0.26

Lv.3 Lv.2

Time(sec)

I d R T N of M 2 dev ic e( uA ) Lv.1

Vna=0.75V, Vdd=1V

0.0 0.2 0.4 0.6 0.8 1.0

0.0 0.2 0.4 0.6 0.8 1.0

V na (v ol t)

Vn(volt)

Case 1 in Fig. 22 of trigate SRAM

Vdd=1V

RSba

9 10 11

0.87 0.88 0.89 0.90 0.91

Lv.4 Lv.3

Lv.2

I d R T N of M 2 dev ic e( uA )

Time(sec)

Lv.1

.

0 10 20 30 40 50

L _eff /W=28/120(nm)

) bulk trigate pMOS device L _eff /W=28/100(nm)

SiO ₂

SiO ₂

V _n

V _na

V _dd

V _n

M2 V _dd

V _na

V _dd

V _na V _n