In chapter 1, a brief overview of LTPS TFTs technology was given to explain the crystallization process. The motivations of this thesis were subsequently explained to introduce this thesis.
In chapter 2, experimental processes of elevated channel thin films were introduced. The mechanism of lateral growth of elevated channel thin films was proposed by material analysis. The material properties were analyzed by scanning electron microscope (SEM) and transmission electron microscope (TEM). Then experimental procedures of polycrystalline silicon thin-film transistors with double gate structure were introduced. The electrical characteristics, including the field-effect mobility, the subthreshold swing, the threshold voltage, and the uniformity were investigated.
In chapter 3, the double gate devices were compared with the top gate and bottom gate ones. Then the DGTFTs fabricated by elevated channel process were modified with lightly doped drain (LDD) structure and shrunk gate engineering with a view to suppression of leakage current. The process flows and the leakage current lowering mechanism would be discussed in detail.
Finally, conclusions were given in chapter 4.
Chapter 2
Fabrication of Location-Controlled Single Grain Boundary (SGB) and
Double Gate (DG) Polycrystalline Silicon (Poly-Si) Thin-Film Transistors
(TFTs) by Elevated Channel Methods Using Excimer Laser Annealing (ELA)
2.1 Introduction
2.1.1 Introduction to Elevated Channel Methods
Currently, high current-driving capability, low leakage current, and good uniformity of TFT characteristics are essential for the application of AMLCD, AMOLED, and 3-dimensional ICs [2.1]-[2.6]. Low-temperature polycrystalline silicon (LTPS) technology is the most promising method to fabricate high performance thin-film transistors (TFTs) on glass or plastic substrate [2.7]. In comparison with amorphous silicon (a-Si) TFTs, LTPS TFTs exhibit higher field effect-mobility and better reliability, which lead to higher driving current and better
stress resistance. Therefore, LTPS TFTs acting as pixel switches are allowed in smaller size; that is, higher aperture ratio is obtained. Furthermore, LTPS TFTs are compatible with complementary metal-oxide-semiconductor (CMOS) circuits which results in the alleviation of power consumption [2.8]. Consequently, the scan drivers, the data drivers, and even the processors are allowed to be integrated in a single glass substrate for the next generation of system on panel (SOP) application. As compared to high temperature polycrystalline silicon (HTPS) TFTs, the thermal budget of LTPS TFTs is much lower for the process temperature is below 200℃, which means that LTPS TFTs may open a new field for flexible microelectronics [2.9]. Accordingly, the cost of LTPS TFTs is much lower than that of HTPS TFTs.
In order to prepare LTPS thin films, several ways have been reported to date, including solid phase crystallization (SPC), metal induced lateral crystallization (MILC), and laser annealing [2.10]-[2.13]. Among these methods, the excimer laser annealing (ELA) may be the most promising one. The excimer laser emits in UV light region with short pulse duration (10-30ns) by the laser source of ArF, KrF, or XeCl (output wavelengths 193, 248, and 308nm, respectively) gas source. The strong optical absorption of UV light and small diffusion length during the laser pulse in silicon imply that high temperature can be produced and cause melting of silicon without significant damage of glass substrate [2.14]. In addition, ELA poly-Si films possess good crystallinity and few intra-grain defects due to the melt-regrowth process. During ELA process, the mechanism of grain growth is quite sensitive to the laser energy density. Fig. 2-1 schematically illustrates the grain growth corresponding to the different laser energy densities. As shown in Fig. 2-1 (a), if the laser energy density is too small to melt the whole a-Si thin film, vertical solidification occurs and the un-melted solid layer remains to be a-Si, while the melted Si layer transform into poly-Si with small grain size [2.15]. Refer to Fig. 2-1 (b), if the laser energy density is
large enough to completely melt the a-Si thin film, homogeneous nucleation occurs for deep supercooling, resulting in small grain size [2.16]. Only when the laser energy density is controlled around a certain threshold value will we obtain large grains whose size are as large as 1μm in diameter, as shown in Fig. 2-1 (c). This is so called Super Lateral Growth (SLG) regime [2.17], which vividly illustrates the behavior of
melted a-Si to recrystallize from very few un-melted Si residues to each other. For the very few residues as seeds, the lateral growth phenomenon causes large grain size.
However, there are some limits for the ELA process even though we control the laser energy density in SLG regime. First, the seeds of SLG regime appear randomly;
that is, the location of grain and grain boundary cannot be controlled and thereafter the large variation of grain size. Fig. 2-2 reveals the non-uniformity of grain size.
Second, a lot of process fluctuation factors exist, i.e., the pulse-to-pulse variation of excimer laser energy, the variation of a-Si film thickness, and the narrow process window of ELA process. Therefore, a novel method called Elevated Channel Process is proposed to enhance the uniformity of grain crystallinity and the location of grain and grain boundary. Moreover, with elevated channel process, we obtained much larger process window rather than that of conventional ELA process.
In this chapter, the experimental procedures of elevated channel process would be introduced. We studied the mechanism of lateral growth of elevated channel process by material analysis equipments. The material properties of elevated channel thin films were investigated by scanning electron microscope (SEM) and transmission electron microscope (TEM).
2.1.2 Introduction to Single Grain Boundary and Double Gate Polycrystalline Silicon Thin-Film Transistors Fabricated by Elevated Channel Method
High current-driving capability and good uniformity of TFT characteristics over a large area of glass substrate were imperative for devices aiming at AMLCD and AMOLED drivers and matrix [2.18]-[2.22]. Furthermore, they should be produced with low cost and high throughput. It was desired that the growth of high-quality large grain could be controlled in the device channel region from the viewpoint of device performance and uniformity. A novel process for high quality LTPS thin films for producing high-mobility polycrystalline silicon TFTs was described in the section above. We call this novel method, elevated channel method. With this method, single grain boundary (SGB) low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) with double gate (DG) structure were formed. There was only one longitudinal grain boundary in the center of the channel. Besides, it has been reported for integrated circuit (IC) application, a double gate device is expected to obtain ultimate high-performance ideal metal oxide semiconductor field-effect transistors (MOSFETs) [2.23]. Therefore, we can produce silicon-on-insulator-liked (SOI-liked) LTPS TFTs by means of introducing the double gate structure. Furthermore, another advantage of double gate structure is the enhancement of gate controlling ability.
With enhanced gate controlling ability, the devices will exhibit high driving current, steeper subthreshold swing, and superior short-channel effect immunity [2.24]-[2.26].
In this section, the detail process flows of SGB-DG- TFTs were introduced. Then the electrical characteristics were measured by electrical parameter analyzer, Agilent 4156. Both the N-type and P-type SGB-DG-TFTs were fabricated in comparison to conventional ones. Moreover, the dependence of laser shots number and electrical
characteristics was investigated. Finally, statistics and uniformity of electrical characteristics exhibited the superiority of SGB-DG-TFTs rather than conventional top gate TFTs.
2.2 Material Analyses of Single Grain Boundary Polycrystalline Silicon Thin Films Fabricated by Elevated Channel Methods
2.2.1 Process Flow of Material Analyses of SGB Poly-Si Thin Films Fabricated by Elevated Channel Method
Detailed process flows of prepared samples were shown in Fig. 2-3. At first, in-situ doping phosphorus polycrystalline silicon thin films with thickness of 1000Å were deposited by pyrolysis of pure SiH4 and PH3 by low-pressure chemical vapor deposition (LPCVD) at 550℃ on oxidized silicon substrates with oxide thickness of 1 μm. Then, the doped polycrystalline silicon layer was defined to form polycrystalline silicon gate by transverse coupled plasma reactive ion etch (TCP-RIE).
Next, a 500Å TEOS oxide layer was deposited as gate insulator by LPCVD at 700°C.
After the deposition of bottom gate insulator, the 1000Å amorphous silicon layer was deposited as the active layer by LPCVD at 550℃ with SiH4 as gas source. The elevated channel was named after the channel region which is elevated for bottom gate structure. Laser crystallization was performed by KrF excimer laser (λ=248nm).
The excimer laser system was shown in Fig. 2-4. During the laser irradiation, the samples were located on a substrate in a vacuum chamber pumped down to 10-3Torr
area was 20 (i.e., 95% overlapping) and laser energy density was varied. The grain structure of the crystallized polycrystalline silicon thin film was analyzed using scanning electron microscope (SEM) and transmission electron microscope (TEM). In order to facilitate the SEM observation, all the samples were processed by secco-etch before SEM analysis.
2.2.2 Material Analysis of SGB Poly-Si Thin Film Fabricated by Elevated Channel Method
2.2.2.1 Scanning Electron Microscope (SEM) Analyses
Fig. 2-5 shows SEM graphs of excimer laser crystallized polycrystalline silicon with elevated channel method. The channel length was (a) 1 μm (b) 1.2 μm and (c) 1.5 μm, respectively. The laser energy was 510 mJ/cm2and the poly gate thickness was 1000 Å. The longitudinal grains with 0.6 μm in length were formed in the channel region. It has been reported that lateral thermal gradient could arise as a result of the heat generated at moving solid-melting interface [2.27]. When a proper laser energy density irradiated the silicon thin film containing different thicknesses, the thin region in the channel region was completely melted while the thick region in the corner due to the step structures of bottom gate was only partially melted, leaving behind islands of solid material. As a result, grains would grow laterally towards the complete melting region from the retained solid seeds. The lateral growth would start from the still solid amorphous silicon spacer seeds and stretch toward the completely melted region until the solid-melt interface from opposite direction collided. Due to the in-situ design of thin channel region, the grain boundaries perpendicular to the current flow in the channel region could be reduced. Thus the field-effect mobility of
polycrystalline silicon TFTs could be greatly improved with this crystallization technique. When a longer channel length was adopted for crystallization, the laser fluence would have to be increased high enough to make the longitudinal grains collide with those grown from the other side; otherwise, small grains caused by spontaneous homogeneous nucleation would form in the center of the channel region as Fig.2-5 (c).
With a view to investigating the process window of elevated channel method, we altered the laser energy density irradiated on a-Si thin film. Fig.2-6 shows SEM graphs of poly-Si thin films with different laser energy densities while the channel length was kept at 1.2 μm. As the laser energy density was increased from 470 mJ/cm2 to 510 mJ/cm2, we obtained analogous gate structure in channel region.
Therefore, we could conclude that the process window of elevated channel method is much larger than that of conventional excimer laser annealing on whole flat a-Si thin film.
It has been reported that thinner active layer can achieve the “fully depleted”
device operation [2.28]. The electrical characteristics of fully depleted devices are much greater than partially depleted ones, such as alleviated kink effect, low threshold voltage, and more ideal subthreshold swing. In our experiment, thinner a-Si thin film (500Å) was also adopted to the elevated channel method. As shown in Fig.2-7, the laser energy density was controlled at 310 mJ/cm2 to completely melt thinner region but partially melted thicker region. However, the a-Si thin film was too thin to keep thermal energy retained in the molten Si channel region and the severe supercooling phenomenon occurred which led to homogenous nucleation. In consequence, small grains were observed in the channel region instead of the lateral grain growth.
Therefore, we must use a-Si thin film thickness of 1000 Å to prevent the homogenous
2.2.2.2 Transmission Electron Microscope (TEM) Analysis
Fig. 2-8 shows the cross-section TEM graphs of polycrystalline silicon thin film fabricated by elevated channel method in the channel region. From the Fig. 2-8, it could be found that single grain boundary was controlled artificially at the center of the channel region, and two large grains with very few intra-grain defects were observed. For polycrystalline silicon thin film used as active layer in thin-film transistor, fewer defects were desired. Meanwhile, the cross-section TEM graph of polycrystalline silicon thin film in the corner region the bottom gate shows that the thickness of the corner region became thinner than that in the channel region. From the correlated electron diffraction pattern of polycrystalline silicon thin film, the crystallinity of the polycrystalline silicon was analyzed. It could be found that as the channel region was selected, the diffraction spots become more obvious, which means that the crystallinity was good. When the corner region was selected, the ring was observed, which revealed that the vertical growth in the corner region of the grains exhibit poor crystallinity. But the corner regions would be heavily doped and act as the source/drain region of TFTs. Therefore, the poor crystallinity may not degrade the performance of LTPS-TFTs.
It is notable to keep an eye on the fact that the good crystallinity appeared not only in the channel region but also the regions at both sides away from the corner of bottom gate as shown in Fig. 2-9. This was analogous to the channel region that the thinner a-Si thin films at these sides were completely melted during laser irradiation, resulting in lateral growth of poly-Si grains. That is, we could obtain similar poly-Si grains with fewer defects except the channel. Therefore, elevated channel method has the potential of produce periodic poly-Si grains if the mask is well designed.
2.3 Fabrication and Electrical Characteristics Analyses of Single Grain Boundary (SGB) and Double Gate (DG) Polycrystalline Silicon (Poly-Si) Thin-Film Transistors (TFT) Fabricated by Elevated Channel Method
2.3.1 Process Flow of SGB-DG-TFTs by Elevated Channel Method
Detailed process flows of device fabrication were shown in Fig. 2-10. At first, in-situ doping phosphorus polycrystalline silicon thin films with thickness of 1000Å were deposited by pyrolysis of pure SiH4 and PH3 by low-pressure chemical vapor deposition (LPCVD) at 550°C on oxidized silicon substrates with oxide thickness of 1μm. Then, the doped polycrystalline silicon layer was defined to form bottom gate by TCP-RIE. Next, a 1000 Å TEOS oxide layer was deposited as bottom gate insulator by LPCVD at 700°C. After the deposition of bottom gate insulator, the 1000Å amorphous silicon layer was deposition as the active layer by LPCVD at 550
℃ with SiH4 as gas source. Laser crystallization was performed by KrF excimer laser (λ=248nm). During the laser irradiation, the samples were located on a substrate in a vacuum chamber pumped down to 10-3Torr and the substrate was maintained at room temperature. The number of laser shots per area was 10 or 20 (i.e., 90 or 95%
overlapping) and laser energy density was varied. Next, the active region was defined by TCP-RIE. Then, a 1000 Å TEOS oxide layer was deposited as top gate insulator by LPCVD at 700°C followed by in-situ doping phosphorus polycrystalline silicon
layer as top gate electrode. After the deposition of top polycrystalline silicon gate, the contact hole was defined and etched by TCP-RIE and 1:10 dilute Buffer Oxide Etch (BOE) solvent to interconnect top gate and bottom gate electrode. Next, a phosphorus/BF2 ion implantation with a dosage of 5×1015 cm-2 and energy of 40keV/70keV was performed to form source and drain regions. A 5500Å TEOS oxide layer was then deposited as passivation layer by LPCVD at 700℃ and the implanted dopants were activated by thermal annealing in furnace at 600°C for 9 hours. Then, contact hole opening by TEL5000-RIE and and metallization with Aluminum were carried out. Finally, Aluminum sintering was carried out at 400 ℃ to reduce the series resistance. No hydrogenation plasma treatment was performed during the device fabrication process. For comparison, conventional top-gate ELC polycrystalline silicon TFTs were also fabricated.
2.3.2 Electrical Characteristics of SGB-DG-TFTs by Elevated Channel Method
2.3.2.1 Electrical Characteristics of SGB-DG-TFTs
It has been demonstrated that large and longitudinal grains could be formed in the channel region by elevated channel method in section 2.1. The grain structure would have a significant influence on the electrical characteristics of the fabricated TFTs. Fig. 2-11~Fig. 2-16 show the typical transfer characteristics of n-channel SGB-DG-TFTs with channel lengths of 0.8 μm ~5 μm, in which the thickness of gate oxide was 1000Å and the number of laser shots per area was 10(i.e., 90%
overlapping). Fig. 2-17 ~Fig. 2-22 show the typical transfer characteristics of n-channel SGB-DG-TFTs with channel lengths of 0.8 μm ~5 μm, in which the
thickness of gate oxide was 1000Å and the number of laser shots per area was 20(i.e., 95% overlapping). Fig. 2-23 ~Fig. 2-28 show the typical transfer characteristics of p-channel SGB-DG-TFTs with channel lengths of 0.8 μm ~5 μm, in which the thickness of gate oxide was 1000Å and the number of laser shots per area was 10.
The laser process conditions were optimized and the conventional top gate TFTs were included for comparison. The threshold voltage was defined as the gate voltage required to achieve a normalized drain current of Id = (W/L)×10-8 A at |Vds| =0.1V.
The equivalent field-effect mobility was extracted from the maximum transconductance in the linear region of Id-Vg characteristics at |Vd| = 0.1V (i.e., the formula of μ=gm/[(W/L)VdsCox] ). The on/off current ratio was defined as the ratio of maximum drain current over minimum drain current at |Vd| =3V. Several important electrical characteristics of the TFTs were summarized in Table 2-1, Table 2-2 and Table 2-3 for laser shots and channel type of 10/N-type, 20/N-type and 10/P-type, respectively.
It is notable that the definition of field-effect mobility of double gate TFTs was analogous to HARA et al. [2.29] in this thesis. The definition of field-effect mobility could be approached by two aspects. One was the physical meaning of carrier transport capability of poly-Si layer, which was defined by the following equation:
DS
while the channel width was 2W because of the number of field induced channel was two.
The other definition was corresponding to the carrier transport capability in the occupied area of active region, which was defined by the following equation:
DS
while the channel width was W because of the occupied width of active region was only W.
In this thesis, the latter definition was adopted; the name of “equivalent field-effective mobility” and the symbol of “μ*” was used to avoid the confusion with the first definition.
According to Fig. 2-11~Fig. 2-28, the SGB-DG-TFTs exhibit superior electrical characteristics to those of conventional top-gate ones, especially in short channel devices. This could be attributed to the longitudinal grain and single grain boundary in the device channel region. Take the dimension of W = L = 1 μm and laser shots of 10 for example, SGB-DG-TFTs with equivalent field-effect mobility of about 720 cm2/V-s could be achieved by using elevated channel method and double gate structure while the mobility of the conventional counterpart was about 79 cm2/V-s.
Aside from the enhancement of equivalent field-effect mobility, the gate controlling ability of double gate structure could be emphasized by the electrical characteristics of subthreshold swing and drain-induced-barrier-lowering (DIBL, which was defined as the difference of threshold voltage between |Vd| =0.1V and |Vd| =3V). In W = L = 1μm device, we obtained subthreshold swing of SGB-DG-LTPS-TFTs about 0.23V/decade, while that of conventional top gate TFTs was about 0.66V/decade.
Similarly, the DIBL of SGB-DG-TFTs was lowered about 200mV rather than that of conventional top gate TFTs. In addition, although the maximum achievable length of lateral grain growth was limited between 0.6 μm as described in the previous section, the electrical characteristics of the TFTs with device dimension up to W = L = 5 μm were still superior to those of conventional ones. This could also ascribed to the long longitudinal grain growth at the channel edge even though many small grains resulted
from spontaneous nucleation exist in the channel center, forming a high series resistance in the middle of channel region as well.
Fig. 2-29 ~Fig. 2-46 display the output characteristics of SGB-DG-TFTs with
Fig. 2-29 ~Fig. 2-46 display the output characteristics of SGB-DG-TFTs with