Thesis organization

In this thesis, three voltage-control oscillators for X-band, WLAN 802.11a, Multi-band operation and an Ultra-wideband Low noise amplifier are realized in TSMC RF 1P6M 0.18μm CMOS technology.

Chapter 2 will include two kinds of transformer feedback techniques in two voltage-controlled oscillators separately. One of this is to achieve higher oscillating frequency and the other is for ultra-low power operation.

Chapter 3 will introduce a multi-band voltage-controlled oscillator and its frequency divider. The characteristic of wide tuning range under low voltage operation covers some group of MB-OFDM UWB system. Both the simulation and the measurement results are further discussed.

Chapter 4 will give some discussions of these circuits to compare the simulation and measurement results. Besides, the future work will be mentioned to propose the possible improvement.

Finally, appendix will present the design and implementation of 3.1~10.6 GHz UWB LNA. In this chapter we study the input matching technique.

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Chapter 2

CMOS Voltage-Controlled Oscillator with transformer feedback

2.1 Introduction

Fig. 2-1 Differential VCOs with (a) transformer feedback to the source and (b) transformer feedback to the front gate

As shown in Fig. 2-1(a), the drain terminal is magnetically feedback to source terminal with an impedance transformation of n²/g_m, where n is the transformer turns-ratio and gm is the transconductance of the transistor [4][5]. Since the impedance seen at the source terminal is 1/g_m, a relatively high turns-ratio is required for the transformer to make an impedance transformation, thereby entailing complexity in transformer design, making it possible to lower the oscillation frequency.

If we feedback the drain voltage to the front-gate like Fig. 2-1(b). Since the impedance seen at the gate of the switching transistor is relatively high, the turns-ratio

- 5 -

of the transformer can be optimized with a smaller number of turns. However, the parasitic capacitances of the transformer directly couple to the tank, and lower the oscillation frequency significantly.

2.2 Circuit Design Consideration

2.2.1 X-band Low phase noise QVCO with back-gate transformer feedback

A. Transformer Feedback to the Back-gate

To obtain both higher frequency and simplify the transformer design (small number of turns ratio), the front-gate feedback path can be modified to have a feedback to the back-gate as shown in Fig. 2-2.

Fig. 2-2 Proposed architecture of TFQVCO

- 6 -

B. Harmonic Filtering Resistor

Because the current source is the main contributor to the phase noise, the current source is replaced by resistor providing bias condition and wide-band operation, it can suppress not only second harmonic but also all the other harmonics [6]. The thermal noise of the resistor will be up converted into 1/f² phase noise by the switching transistors. So there is a tradeoff between the harmonic filtering and its thermal noise contribution. As we increase the resistance, the 1/f² phase noise performance will reach its optimum value and begin to degrade in the same way. This is because the thermal noise contribution overwhelms the phase noise reduction by the harmonic filtering. In this design, R=170Ω is selected.

C. Quadrature Generation

Fig. 2-3 Two interleaved VCO configuration

There are several ways to obtain quadrature signals: RC poly-phase filters, divider-by-2 circuit, and two interleaved voltage-controlled oscillators. RC poly-phase filters attenuate the signal and increase the effective capacitance of the tank. A lot of chip area is needed for a good matching of the filters. The divider-by-2 circuit needs and oscillator operating at 2 times higher than the desired frequency and a high-speed frequency. Both circuits dissipate a lot of power. For the low power consumption and quadrature phase accuracy, two interleaved VCO configuration is adopted as shown in Fig. 2-3.

With parallel coupling transistor to generate the I-Q phase. From the Barkhausen

- 7 -

criterion, oscillation only occurs when the loop gain is [A(jω)]⁴=1, which means A(j ω)=1 ∠ 90^o [7]. Therefore, this configuration provides quadrature-phase signals from the four outputs of these two proposed VCOs.

The all-PMOS topology is preferred since PMOS has lower corner frequency of flicker noise, which means less low frequency noise [8].

D. Transformer Design

A 2-µm-thick top AlCu metal is used for the windings to increase the quality factor. The transformer is designed with 1-µm line spacing, 150-µm outer dimension.

Besides, the quality factor of transformer can be optimized by increasing the metal width progressively from the inner to the outer turn [5][9]. As such, the series loss in the outer turn is reduced while its substrate loss associated with the wider metal width does not degrade the performance due to the virtual ground at the inductor's center tap.

Fig. 2-4(a) shows the transformer is simulated by ADS Momentum with primary inductance (L_d) 0.46nH, and the secondary inductance (L_s) 0.13nH, with quality factors 6.8 and 4.4 respectively. The transformer coupling coefficient km is modeled as shown in Fig. 2-4(b), which is calculated by Eq. (2-1) as 0.4 [10].

0.0E+0 2.0E+9 4.0E+9 6.0E+9 8.0E+9 1.0E+10 1.2E+10 freq

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

inductance

primary

secondary

Fig. 2-4 (a) The primary and secondary self-inductances (b) Transformer lump model

- 8 -

2 / 2 / )

Im(

) Im(

) Im(

22 11

12

d s

M

im

L L

L Z

Z K Z

= ×

=

(2-1)

MOS varactors are used to provide the frequency tuning capability. AM noise originating from the upconversion of low frequency noise cannot be neglected due to AM-PM conversion through the varactors. So the frequency tuning capability will be controlled as varactor's selectivity and traded for lower phase noise [11]. The accumulation-mode MOS varactor is adopted in one group with 10 fingers.

The equivalent capacitance Ceq is about 42~122 fF and its equivalent lumped model is shown as in Fig. 2-5.

Fig. 2-5 The lumped model of the MOS varactor

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2.2.2 5.25 GHz Low power VCO with drain-source Transformer feedback

The continuous growth of personal wireless communication demands low-cost low-power solutions in the design of wireless system. Low-voltage operation may save the power consumption of the analog as long as the total bias current does not need to be increased to maintain the same performance. Low voltage, however, limits the signal amplitude, which in turn limits the signal-to-noise ratio and degrades system performance.

(a) (b) Fig. 2-6 The Proposed (b) TF-VCO and its (b) half circuit

To improve the VCO performance in terms of low supply voltage, low power, and low phase noise, a TF-VCO is proposed to provide extra voltage swings, improved loaded quality factor, minimum noise-to-phase-noise transfer [5] as shown in Fig. 2-6.

A. Enhanced voltage swings

The main limitation of the signal amplitude is overcome by the concept of dual signal swing, which enables the output signals to swing above the supply voltage and

- 10 -

below the ground potential with transformer feedback to increase the carrier power.

Besides, the drain and source signal oscillate in phase to enhanced the swing amplitude.

For an ideal coupling factor k=1, the source signal amplitude V_s,p is related to the drain signal amplitude Vd,p by Vs,p=Vd,p/KL for KL=Ld/Ls and the maximum peak-to-peak oscillation amplitude at the drain would be increased to 2.V_DD(1+1/K_L)

B. Improved loaded quality factor

The TF-VCO could also be analyzed by the half circuit VCO’s transfer function.

In Fig. 2-6(b), the tanks at the source and the drain are modeled by two RLC networks with a magnetic coupling coefficient k between Ld and Ls. For simplicity, the coupling coefficient k is assumed to be unity for now.

Defining KL=Ld/Ls, KC=Cd/Cs, Rd=Qd.ω.Ld and Rs=Qs.ω.(Ld/KL) with Qd and Qs which corresponds to a unity loop gain with a zero phase shift for the closed loop. By solving (2-2), the oscillation frequency of TF-VCO is

- 11 - tank at the source is much larger than that of the tank at the drain.

An important parameter is the loaded quality factor Q_loaded of the tank circuit, which is defined as the Q factor of the second-order transfer function Vout/Vin. From (2-2), the quality factor is given by

Because the resonant frequency of the secondary tank ω_resonance of the TF-VCO is far above the oscillation frequency ωo, the unloaded parallel quality factor Qparallel of the secondary inductor atω_o is

- 12 -

C. Minimum noise-to phase-noise transfer

Fig. 2-7 Half circuits (a) Colpitts (b) TF-VCO

Fig.2-7 shows a comparison between a common-gate Colpitts VCO and the half-circuit TF-VCO, where the transformer is represented by an equivalent model. For the Colpitts oscillator, the capacitors C₁ and C₂ form the feedback network of the total tank capacitance and thus limit the maximum achievable L/C ratio. This contradicts the requirements for high tank quality factor and high tank impedance, and thus the Colpitts VCO is not favorable for low-power VCO design. The TF-VCO, on the other hand, uses a single transformer for the feedback and does not impose extra capacitance to the tank circuit, which could be similar to the Hartley design.

Since the proposed VCO is operated under an ultra-low dc voltage, the cross-coupled transistors are potentially biased in the weak-inversion region. Therefore, the drain noise of the transistors is no longer dominated by the thermal noise as [12] , ^n,d 4kT g_d0

f

i = γ

∆ , where gd0 is the channel conductance with VGS=0, and γ is the thermal noise coefficient. Instead, the drain noise is expressed as [13]

- 13 -

diffusion components as the gate overdrive V_GS-Vt approaches V_T.

Due to the fact that 2qID is generally greater than 4kTγg_d0 for low-power operation, the cross-coupled transistors may contribute more noise to the LC tank as the supply voltage decreases. Therefore, it imposes a fundamental limitation on the phase noise of the VCO for ultra-low-power and ultra-low-voltage applications.

D. Forward Body Bias

For deep-submicrometer MOSFETs, the threshold voltage V_t is no longer constant, but influenced by circuit parameters such as gate length, channel width, and drain-to source voltage due to the short-channel and narrow-channel effects. Typically, transistors with a large channel width and a minimum gate length exhibit a reduced Vt , which is preferable for low-voltage operations. In this VCO topology, the fundamental limitation on the supply voltage is imposed by the threshold voltage of the cross-coupled transistors. To further reduce the supply voltage, the FBB technique is adopted [14] as shown in Fig. 2-8.

For a MOSFET device, the threshold voltage is governed by the body effect as

Vt =Vt₀ +

(

2qNAεs /Cox

)

•

(

2φF +VSB − 2φF

)

(2-8) Where Vt0 is the threshold voltage for VSB=0V, ψF is a physical parameter with a typical value of 0.3V, N_A is the substrate doping, and ε_s is the permittivity of silicon.

By applying a forward bias voltage to the body through a current-limiting resistor RB, the effective threshold voltage is thus reduced while maintaining a minimum forward junction current between the body and the source terminals. The simulated effective threshold voltage and the drain current of a MOSFET with W=60μm and L=0.18μm are demonstrated in Fig. 2-8, indicating a threshold voltage reduction more than 80mV due to the FBB technique.

- 14 -

Fig. 2-8 I-V characteristics of the MOSFET with and without FBB Besides, Fig. 2-9 shows the threshold voltage and its corresponding drain current under different forward body bias conditions.

0.2 0.3 0.4 0.5 0.6

Fig. 2-9 Simulated threshold voltage and drain current of the MOSFET with FBB

E. Transformer Design

The design takes advantage of the higher mobility of the NMOS devices compared to PMOS and the higher quality factor of differential inductors over simple single-ended inductors for differential circuits with a deep n-well as the source-bulk isolation to the substrate. For differential inductors, the quality factor is improved by a factor of two, without special processing steps because the magnetic coupling between

- 15 -

the two coils ideally doubles the inductance value while the series loss is unchanged.

Fig. 2-10 shows the transformer is simulated by ADS Momentum with primary inductance (L_d) 0.786nH, and the secondary inductance (L_s) 0.221nH, with quality factors 7 and 5 respectively. The transformer coupling is calculated by Eq. (2-1) as 0.5 [10].

Fig. 2-10 The primary and secondary self-inductances

Fig. 2-11 shows the drain voltage swing under different coupling coefficient, which implies the actual carrier power is reduced for lower coupling coefficient, and the source voltage swing is no longer sinusoidal to help enhance the voltage swing.

This will unavoidably degrade the phase noise.

0 0.05 0.1 0.15 0.2

- 16 -

Fig. 2-11 The drain and source voltage waveform for (a) k=1 (b) k=0.75 (c) k=0.5

2.3 Chip Layout and Simulation Results

2.3.1 X-band Low phase noise QVCO with back-gate transformer feedback

Fig. 2-12 shows the layout designed and processed using TSMC 0.18µm mixed-signal/RF CMOS 1P6M technology. The chip size is 0.88×0.49mm² including the pads. The simulation result shows the phase noise is about -114dBc/Hz at 1MHz offset in Fig. 2-13 and Fig. 2-14 shows the output frequency tuning range of the QVCO is around 800 MHz ranging from 8.9 to 9.7 GHz. The QVCO core circuit draws only 4.1mA from a 1.5-V supply.

The figure-of-merit (FOM) is expressed as [15].

] compare the performance of the proposed VCO, the power-frequency-normalized figure-of-merit (FOM) is used in (2-9) as -185.5@1MHz.

- 17 -

Fig. 2-12 The Chip layout

Fig. 2-13 The frequency tuning range

- 18 -

Fig. 2-14 The phase noise

Table 2-1 QVCO performance in different corner conditions

Corner TT FF SS

Tuning Range 8.9~9.7GHz 9.05~9.8 GHz 8.8~9.65 GHz Phase Noise@1MHz -114dBc/Hz -113dBc/Hz -115dBc/Hz

Total Power (with buffer)

6.2+16.2mW 22.4mW

7.75+32.2mW 39.95mW

5.1+5.9mW 11mW

Table 2-2 QVCO performance under different supply voltage

Supply Voltage 1.5V 1.65V 1.35V

Tuning Range 8.9~9.7 GHz 8.85~9.6 GHz 8.95~9.75 GHz Phase Noise@1MHz -114dBc/Hz -114dBc/Hz -113dBc/Hz

Total Power (with buffer)

6.2+16.2mW 22.4mW

8.1+30.5mW 38.6mW

4.6+5.6mW 10.2mW

- 19 -

2.3.2 5.25 GHz Low power VCO with drain-source Transformer feedback

Fig. 2-15 The chip layout

Fig. 2-15 shows the layout designed and processed using TSMC 0.18µm mixed-signal/RF CMOS 1P6M technology. The chip size is 0.66×0.58mm² including the pads. The simulation result shows the phase noise is about -113dBc/Hz at 1MHz offset in Fig. 2-16 and Fig. 2-17 shows the output frequency tuning range of the TF-VCO is around 310 MHz ranging from 5.05 to 5.36 GHz. The power dissipation of the TF-VCO core circuit draws only 0.57mW from a 0.5-V supply. The figure-of-merit (FOM) is about -192@1MHz.

- 20 -

Fig. 2-16 The phase noise

Fig. 2-17 The tuning noise

- 21 -

Table 2-3 VCO performance in different corner conditions

Corner TT FF SS

Tuning Range 5.05~5.36GHz 5.08~5.38GHz 5.03~5.34GHz

Phase Noise@1MHz -113 -115 -112

Core Power 0.6mW 1.1mW 0.4mW

Buffer Power 16.3mW 22mW 12mW

Table 2-4 VCO performance under different supply voltage

Supply Voltage 0.5V 0.55V 0.45V

Tuning Range 5.05~5.36GHz 5.03~5.35GHz 5.05~5.36GHz

Phase Noise@1MHz -113 -114 -112

Core Power 0.6mW 1.2mW 0.46mW

Buffer Power 16.3mW 16.3mW 16.3mW

2.4 Measurement Results and Discussions 2.4.1 Measurement Consideration

The two voltage controlled oscillator are designed for on-wafer testing. Therefore the arrangement of each pad must satisfy rules of CIC’s (Chip Implementation Center’s) probe station testing rules. The measurement equipments contain Agilent E5052A signal source analyzer, E4407B spectrum analyzer, and E3615A DC power supply in Fig. 2-18.

- 22 -

(a)

(b)

(c)

Fig. 2-18 (a) Agilent E5052A signal source analyzer (b) E4407B spectrum analyzer (c) E3615A DC power supply

- 23 -

A. X-band Low phase noise Quadrature CMOS VCO with back-gate transformer feedback

The chip photograph is shown in Fig. 2-19.

Fig. 2-19 Chip Photograph

According to Fig. 2-20 , the measured output frequency tuning range of the fabricated TF-QVCO is 470kHz ranging from 8.14 GHz to 8.61 GHz. Fig. 2-21 shows the phase noise of -113dBc/Hz at 1MHz offset when the frequency is 8.45GHz and the output spectrum is -6.5dBm as show in Fig. 2-22. The VCO core draws 4.2mA from 1.5V supply.

- 24 -

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Control Voltage (V) 8.1

8.15 8.2 8.25 8.3 8.35 8.4 8.45 8.5 8.55 8.6 8.65

Frequency (GHz)

Fig. 2-20 The measured tuning range

Fig. 2-21 The measure phase noise

- 25 -

Fig. 2-22 The measure spectrum

Table 2-5 Performance summary of the TF-QVCO

Performance Post-Simulation Measurement

Supply Voltage 1.5V

Tuning Range 8.9~9.7 GHz (9 %) 8.14~8.61 GHz

Phasenoise@1MHz -114dBc/Hz -113dBc/Hz

Power Consumption ^22.4mW

(VCO core 6.2mW)

21.1mW (VCO core 6.2mW)

Output Power -3.2 dBm -6.5 dBm

FOM 185.5 183.6

- 26 -

Table 2-6 Comparison of TF-QVCO

This work MWCL,2005 [4] MWCL,2003 [16]

Technology 0.18um CMOS 0.18um CMOS 0.18um CMOS

Voltage 1.5V 1.8V 3V

Oscillation

Frequency ^{8.4 GHz 11.22 GHz 8 GHz}

8.14~8.61 GHz 8.08~7.83GHz

Tuning Range

5.6%

300MHz vtune

from 1.6-2V 3 %

Phase noise (dBc/Hz) -113dBc/Hz -109.4 @ 1MHz -117 @ 1 MHz Power

Dissipation ^{6.2 mW}

6.84 mW (vco core)

24 mW (vco core)

FOM 183.6 -181.8 -181.7

B. A Low-Power CMOS VCO with drain-source transformer feedback

The chip photograph is shown in Fig. 2-23.

Fig. 2-23 Chip Photograph

- 27 -

According to Fig. 2-24 , the measured output frequency tuning range of the fabricated TFDSVCO is 290kHz ranging from 5.13 GHz to 5.42 GHz. Fig. 2-25 shows the phase noise of -114dBc/Hz at 1MHz offset when the frequency is 5.33GHz and the output spectrum is 1.62dBm as show in Fig. 2-26. The VCO core draws 1.2mA from 0.5V supply.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Control Voltage (V) 5.1

5.15 5.2 5.25 5.3 5.35 5.4 5.45

Frequency (GHz)

Fig. 2-24 The measured tuning range

- 28 -

Fig. 2-25 The measure phase noise

Fig. 2-26 The measure spectrum

- 29 -

Table 2-7 Performance summary of the TF-VCO Performance Post-Simulation Measurement

Voltage 0.5V 0.5

Tuning

Range 5.05~5.36GHz 5.13~5.42

Phase noise

Table 2-8 Comparison of TF-VCO This work

Technology 0.18um CMOS 0.18um CMOS 0.18um CMOS

Voltage 0.5V 0.5V 0.6V

- 30 -

Chapter 3 Low Voltage Multi-Band VCO and its Frequency Divider

3.1 Introduction

Unfortunately, the inherently low transconductance of the MOSFETs at higher frequencies have impeded the evolution of low-power designs to RF front-ends. In addition to the power considerations, a reduced supply voltage is also an inevitable trend for CMOS designs as well. With the continuous shrinking in the transistor feature size, a proportional down-scaling of the supply is required to ensure the gate-oxide reliability [17].

The forecast of the supply voltage for CMOS circuits within the next decade [18]

is shown in Fig. 3-1.

Fig. 3-1 Forecast of the CMOS supply voltage by ITRS [14]

- 31 -

3.2 Circuit Design Consideration

Fig. 3-2 Frequency allocation of MB-OFDM proposal.

In this work, Band 1, 2 and 6~9 are covered as shown in Fig. 3-2. Band Group 2 from 4752~5808 MHz causes interference with 802.11 a and Band Group 4,5 is reserved for future use. In order to meet such a specification, a VCO accompanied with a frequency divider is used to loosen the stringency, where the VCO provides carriers for Band 6~9 while the frequency divider is in charge of Band 1, 2. The multiplexer is also included to select where the output is from vco or divider. The architecture is shown in Fig. 3-3.

Fig. 3-3 Architecture of this circuit

- 32 -

3.2.1 Voltage-Controlled Oscillator

The schematic of the proposed VCO is shown Fig. 3-4. In order to reduce the required supply voltage and to eliminate additional noise contribution, the tail current transistor in a conventional cross-coupled VCO is replaced by on-chip inductors. For an enhanced voltage swing under a low supply voltage, the capacitive-feedback technique is employed [14]. Due to the use of the on-chip inductor and the feedback loop established by C1 and C2, the drain and source voltages can swing above the supply voltage and below the ground potential. Consequently, the output swing of the VCO is enhanced, leading to a superior close-in phase noise.

Fig. 3-4 Schematic of the proposed VCO with switched capacitor array

A. Startup Conditions

- 33 -

Fig. 3-5 Simplified half-circuit model of the proposed VCO

In order to derive the startup conditions and the oscillation frequency,the equivalent half-circuit of the VCO core is shown in Fig. 3-5, where R₁ and R₂ represent the losses of the on-chip inductors L1 and L2, respectively. In the equivalent circuit, the shunt resistance R₁ and R₂ can be estimated by

From the small-signal analysis, the transfer function between V_o and V_i is given by

( )

- 34 -

with proper arrangement, (3-3) yields

[ ( ) ] ( )

( ) ₀² 1 0 From (3-6), the oscillation frequency can be approximated by

( ) ( )

Based on (3-5) and (3-7), the required transconductance g_m to sustain the oscillation is given by transconductance, which could be simplified by selecting the ratio appropriately.

B. Output Voltage Swing

In the proposed VCO circuit, a capacitive feedback is formed by capacitors C₁ and C2. Due to the in-phase relationship provided by the capacitive feedback and the use of on-chip inductors, the drain and source voltage can swing above the supply voltage and below the ground potential, as illustrated in Fig. 3-6(a). To evaluate the performance enhancement of this technique, the output voltage swing of the VCO is derived from the time-domain waveform of the drain current I1(t), as shown in Fig. 3-6(b).

- 35 -

Fig. 3-6 (a) The drain and source voltage waveform due to capacitive feedback (b) Acutal and modeld drain current waveform [14]

For simplicity, the periodic drain current is modeled by a square wave with a period of T0=2π/ω⁰ and an amplitude of I0. Note that, at the quiescent point, the transistors are biased at V_D1=V_D2=V_DD and V_S1=V_S2=0. The maximum drain current occurs when the gate voltage VG1 reaches its peak value. Assuming that the amplitude of output oscillating signal is A, the gate voltages V_G1 and V_G2 are (V_DD+A) and (VDD-A), respectively, while the source voltages VS1 and VS2 can be obtained by the voltage divider of C₁ and C₂. Thus, I₀ is approximated by the maximum drain current

For simplicity, the periodic drain current is modeled by a square wave with a period of T0=2π/ω⁰ and an amplitude of I0. Note that, at the quiescent point, the transistors are biased at V_D1=V_D2=V_DD and V_S1=V_S2=0. The maximum drain current occurs when the gate voltage VG1 reaches its peak value. Assuming that the amplitude of output oscillating signal is A, the gate voltages V_G1 and V_G2 are (V_DD+A) and (VDD-A), respectively, while the source voltages VS1 and VS2 can be obtained by the voltage divider of C₁ and C₂. Thus, I₀ is approximated by the maximum drain current

在文檔中 低功率變壓器回授與低電壓多頻之壓控震盪器和超寬頻系統之低雜訊放大器設計與研究 (頁 14-0)