Chapter 3 Low Voltage Multi-Band VCO and its Frequency Divider
3.2 Circuit Design and Consideration
3.2.2 Divider
Frequency dividers operating at high frequency are one of the key blocks in the RF circuits because dividers must function properly over the required bandwidth and provide enough output swing for the next stage. Three kinds of dividers are often used:
digital CMOS logic, current-mode logic (CML), and injection-locked frequency dividers (ILFD) [21]. Digital CMOS logic is seldom used since full-scale swing is needed and the operating frequency is relatively low. Compared with CML, ILFD has
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lower power consumption with larger area and narrower locking range. Due to very wide bandwidth of VCO, the CML is chosen in this work.
Fig. 3-7 Block diagram of the CML frequency dividers
Fig. 3-8 Schematic of the CML frequency dividers
The block diagram of CML frequency dividers is shown is Fig.3-7. The master and slave D-FFs are clocked by complementary clocked signals and the differential outputs of LC-VCO in the previous section provide this kind of input signals. Consequently, the inverter in Fig.3-7 is implemented without adding any circuit. The frequency of both Vm and Vo is half the frequency of Vi. Meanwhile the phase difference between Vm and Vo is just 90 degree and quadreture outputs are obtained. In other words, CML is also a kind of quadrature signal generators owing to the characteristic of the output nodes.
The D-FFs implemented in CML are composed of a clocked differential sensing amplifier pair and inversely clocked latching pair as shown in Fig. 3-8. The two D flip-flops are operate periodically and alternately between two modes. When the input
- 38 -
VCO signal is low, one of the D-FF is in the sensing mode, while the other D-FF is in the latching mode. In contrast with common CML circuits, the bias current source is eliminated increase the maximum operating frequency about 10% [22].
Only NMOS transistors are used in this circuit because the drain parasitic capacitance and power dissipation should be minimized. The trans-conductance of clock transistors has to be large and then the small input signals can drive them from the linear region to the saturation region. Therefore the sensitivity to the DC level of input signals is increased. Due to omitting the current source, the DC bias point of the circuit is determined by the size and Vgs-Vt of the clock transistors, the DC level of the input, and the value of the load resistance.
The load resistance is another key parameter since the dominant pole is decided by the load resistance and parasitic capacitance from transistors, interconnection, and next stage. To make this pole high enough, the R must be small, which inevitable leads to increased power consumption to set the DC output.
3.2.3 2-to-1 Multiplexer
(a)
- 39 -
(b)
Fig. 3-9 (a) Schematic of multiplexer (b) Gain of the multiplexer vs. the input frequency
The 2-to 1 multiplexer is to decide that the output is generated from VCO or the Divider. Fig. 3-9 shows the schematic of the multiplexer. Again the current source is removed to relax the voltage headroom problem [23]. When Vsel is high, MS2 is off and the output is only from the VCO. On the other hand, when Vsel is low, MS1 is off and the output is only from the divider. Because the output frequency covers a wide range of spectrum, the gain must insensitive to the operating frequency. The load inductors and capacitors should be designed as large as possible to alleviate the impedance variation with the frequency. Therefore, the bias-tee is chosen as the load impedance. The inductor and capacitor in the bias-tee can be treated as infinitely large at the multi-GHz frequency. For this reason, the load impedance is approximately on RL (50Ohm).
3.3 Chip Layout and Simulation Results
- 40 -
A signal generator is designed and simulated by Eldo RF simulator. The chip size is 0.95×0.65mm2 including the pads and fabricated using TSMC 0.18µm mixed-signal/RF CMOS 1P6M technology. Fig. 3-10 shows the layout of this circuit, which is kept symmetry to equalize the amplitude of the differential outputs. The power consumption of each block is listed in Table 3-1.
Fig. 3-10 The chip layout
Table 3-1 Power consumption of each block
power current
VCO 7.1 mW 7.9 mA
Divider 8.16 mW 4.5 mA
MUX 20.53 mW 11.4 mA
total 35.8 mW 21.06 mA
The simulation result shows that the tuning range is 6.05~8.14 GHz for the total 10 curves. Overlapping between curves is necessary to avoid the process variation and cover the entire band as shown in Fig. 3-11
- 41 -
Fig. 3-11 Tuning range curves of different banks
In Fig. 3-12, the band switching is completed in about 0.61 nsec. In consequence, both of the periods are much shorter than the required time 9.5 nsec.
Fig. 3-12 Output waveform switching from bank (0,0,0,0) to (1,1,1,1)
- 42 -
When the digital input is (0,0,0,0) with the control voltage of 1V, the oscillation frequency is 7.920 GHz. The output swing is 0.95 Vpp (3.6dBm) and the phase noise is -110 dBc/Hz. Through the frequency divider, output frequency at 3.960 GHz is generated. These results are shown in Fig. 3-13 and Fig. 3-14
Fig. 3-13 Output waveform of VCO and frequency divider
Fig. 3-14 Phase noise with oscillation at 7.920 GHz
- 43 -
When the digital input is (0,0,1,0) with the control voltage of 0.95V, the oscillation frequency is 7.392GHz. The output swing is 0.9 Vpp (3dBm) and the phase noise is -111 dBc/Hz. Through the frequency divider, output frequency at 3.692 GHz is generated.
These results are shown in Fig. 3-15 and Fig. 3-16
Fig. 3-15 Output waveform of VCO and frequency divider
Fig. 3-16 Phase noise with oscillation at 7.392 GHz
- 44 -
When the digital input is (1,0,0,0) with the control voltage of 0.73V, the oscillation frequency is 6.864GHz. The output swing is 0.82 Vpp (1.8dBm) and the phase noise is -113 dBc/Hz. Through the frequency divider, output frequency at 3.692 GHz is generated. These results are shown in Fig. 3-17 and Fig. 3-18
Fig. 3-17 Output waveform of VCO and frequency divider
Fig. 3-18 Phase noise with oscillation at 6.864 GHz
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When the digital input is (1,0,1,1) with the control voltage of 0.4V, the oscillation frequency is 6.336GHz. The output swing is 0.75 Vpp (0.2dBm) and the phase noise is -114 dBc/Hz. Through the frequency divider, output frequency at 3.692 GHz is generated. These results are shown in Fig. 3-19 and Fig. 3-20
Fig. 3-19 Output waveform of VCO and frequency divider
Fig. 3-20 Phase noise with oscillation at 6.336 GHz
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Table 3-2 Summary performance of the carrier frequencies Output Frequency Voltage Swing Phase noise @ 1MHz FOM
6.336 GHz 0.73VPP -114 dBz/Hz 183
6.864 GHz 0.82 VPP -113 dBz/Hz 182.8
7.392 GHz 0.9 VPP -111 dBz/Hz 182.1
7.920 GHz 0.95 VPP -110 dBz/Hz 181
Table 3-3 VCO tuning range and power dissipation for different corner
Corner TT FF SS
Tuning Range (GHz) 6.05~8.14 6.36~8.32 5.75~7.99
Power Dissipation 35.8 mW 45.26mW 29.16mW
Table 3-4 VCO tuning range and power dissipation for different power supply
VDD 0.9V 0.81V 0.99V
Tuning Range(GHz) 6.05~8.14 6.05~8.17 6.04~8.1
Power Dissipation 35.8mW 33.4mW 39.45mW
Table 3-5 VCO phase noise of the carrier frequency for different corner
Corner TT FF SS
7.920GHz -110 -109 -111
7.392GHz -111 -110 -112
6.684GHz -113 -110 -111
6.336GHz -114 -113 -109
Table 3-6 VCO phase noise of the carrier frequency for different power supply
Corner 0.9V 0.81V 0.99V
7.920GHz -110 -110 -111
7.392GHz -111 -111 -112
6.684GHz -113 -112 -113
6.336GHz -114 -113 -114
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3.4 Measurement results and Discussion
The multi-band controlled oscillator is designed for on-wafer testing. Therefore the arrangement of each pad must satisfy rules of CIC’s (Chip Implementation Center’s) probe station testing rules. The measurement equipments contain Agilent E5052A signal source analyzer, E4407B spectrum analyzer, and E3615A DC power supply. Also the whole chip photograph is shown in Fig. 3-21
Fig. 3-21 Chip photograph
According to Fig. 3-22, the 10 tuning range curves cover each other and signal at GHz can be generated. Comparing with 6.05~8.14 GHz bandwidth in the simulation results, the total tuning range is a little shrunk. Because the gain of the VCO is little change in Table 3-7, the compressed tuning range is mainly from the overestimated capacitors in SCA.
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Fig. 3-22 Measured tuning range curves with different banks
Table 3-7 KVCO comparison between the simulation and measurement Simulation Measurement
- 49 -
Following the tuning range, the output power and phase noise performance is measured in Fig. 3-23 and Table 3-8. The measure value of the phase noise is approximately equal to the simulated one.
(a) 6.336GHz
(b) 6.864 GHz
- 50 -
(c) 7.392GHz
(d) 7.920GHz
Fig. 3-23 Measurement of output power and phase noise
Table 3-8 Measurement of output power and phase noise performance Output Frequency Output Power Phase noise @ 1MHz FOM
6.336 GHz 3.64 -116 dBz/Hz 185
6.864 GHz 1.51 -114 dBz/Hz 184
7.392 GHz 2.27 -112 dBz/Hz 183
7.920 GHz 3.84 -112 dBz/Hz 183
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Besides the VCO, the performance of the divider-by-2 circuit is measured in Fig.
3-24. The multiplexer suppresses the VCO signal about 20dB when the frequency divider is selected. But at 7.3GHz the divider doesn’t work properly in Fig. 3-25. The reason is likely that the parasitic effect at the output nodes of the divider is not completely extracted and the behavior can’t be accurately predicted in the post-simulation.
(a) (b)
(c)
Fig. 3-24 Output power of the carrier frequency at (a) 2.94 and (b) 3.174 GHz (c) 3.440 GHz
- 52 -
As a result, the control voltage of VCO is tuned and the locking range of the frequency divider is up to 7.27GHz. The measurement is shown in Fig. 3-26. Finally, the power dissipation of each block in the measurement is very close to the result in the simulation.
Fig. 3-26 Maximal frequency in the locking range of the divider
The performance in the measurement is close to the results in the simulation except that 3.96 GHz signal is not generated successfully. To improve this, the layout parasitic extraction by EM software has to be more detailed although this will take a longer time. Besides, the bias point of divider design should be checked and fine-tuned.
The summary of this work is listed in Table 3-9. In addition, the comparison with other wideband VCOs is shown in Table 3-10. Through the calculation of the figure-of-merit (FOM), this work really achieves better performance.
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Table 3-9 Performance summary of the multi-band VCO
Performance Post-Simulation Measurement
Supply Voltage 0.9V
Tuning Range 6.05~8.14 GHz 5.85~7.93GHz
Phasenoise@1MHz -110~-114dBc/Hz -112~-116dBc/Hz
Power Consumption 35.8 mW 36.2
Output Power 2.2~4.5 dBm 1.51~3.84 dBm
FOM 181~183 183~185
Table 3-10 Comparison with the multi-band VCOs This work ISCAS 2005
[25]
MWCL 2005 [24]
Technology 0.18μm CMOS 0.18μm CMOS 0.18μm CMOS Supply
Voltage 0.9 V 1.5V 1.8V
Tuning range 5.85~7.93 GHz 3.5~5.3 GHz 5.5~6.7 GHz Phase noise
(dBc/Hz) -116 @ 1 MHz -115 @ 1 MHz -114 @ 1 MHz Power
Dissipation
36.2 mW (7 mW
in VCO core) 6 mW 5.8 mW
FOM 185 182 180
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Chapter 4 Conclusion and Future Work
4.1 Conclusion
In chapter two, we discuss two kinds of VCO based on transformer：feedback to the Back-gate and the source. In order to achieve higher frequency operation, transformer is feedback to the back gate. The measured results reveal that the power consumption is 6.2mW for 1.5V supply voltage, the tuning rage is between 8.14~8.61 GHz, the phase noise is -113dBc/Hz@1MHz. Adopting transformer feedback from drain to source enables ultra-low power application. The measured results reveal that the tuning rage is between 5.13~5.42 GHz, the phase noise is -114dBc/Hz @1MHz, the power consumption is only 0.57mW under 0.5V supply voltage. In chapter three, for MB-OFDM UWB system, the VCO generates the carrier frequency for Band 6~9, the divider generate Band 1,2, and multiplexer select the signal from the VCO or Divider.
The measured results reveal that the tuning rage is between 5.85~7.93 GHz, the phase noise is best -116dBc/Hz @1MHz, the total power consumption is 36.2mW.
Finally, we introduce an ultra-wide band low noise amplifier in the appendix. It uses the intrinsic capacitance of transistors to achieve the input matching and the complicated input matching network is replaced. The simulation result of UWB LNA demonstrates S11 < -10dB and S22 < -10dB from 3.1 to 10.6 GHz. The power gain (S21) is 15dB. The minimum noise figure is 4.2dB.
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4.2 Future Work
From chapter 2, the X-band back gate TF-QVCO could be modified as shown in Fig. 4-1. We insert a resistor between the bias transistor as current source and the core circuit [6]. Low frequency bias noise is the dominant factor for the 1/f3 phase noise.
The filtering resistance can isolate the bias transistor from the cross-coupled pair and less bias noise can be upconverted into the 1/f3 phase noise. As we increase the resistance, the 1/f2 phase noise performance will reach its optimum value and begin to degrade in the same way. This is because the thermal noise contribution overwhelms the phase noise reduction by the harmonic filtering. So there is a tradeoff between 1/f2 and 1/f3 phase noise performance as a function of the filtering resistance.
Fig. 4-1 Revised architecture of back gate TF-QVCO
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Appendix
CMOS Low-Noise Amplifier for UWB System
A.1 Introduction
A low-noise amplifier is the first stage in the receiver block of a communication system. For UWB applications, the criteria to judge its performances are slightly different from narrow system. Because transmitted power spreads over a wide range and is restricted to be less than -41.3 dBm per MHz, the requirement on linearity in UWB system is not such important as in narrow system. The important requirements for UWB applications are wide-band input impedance matching, low power consumption, low noise performance, and enough gain to suppress noise of the next stages.
Fig. A-1 shows the four basic 50 Ohm input matching techniques. However, these topologies have some drawbacks. The four input matching is only suit for narrow band amplifier [26][27][28][29][30].
(a) (b)
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(c) (d)
Fig. A-1 Basic input matching topology. (a) Inductive source degeneration.(b) Direct resistor termination.(c) Shunt-series feedback.(d) Chebyshev band-pass filter Fig. A-1 (a) is traditional source degeneration topology, because it only resonances at one frequency, it can’t achieve wide-band 50 Ohm matching. It realizes only narrow band matching. Fig. A-1 (b) is the resistive termination matching, because of the loading effect, it will loss a lot of voltage if resistive termination matching is used. Fig.
A-1 (c) is feedback method. It can achieve wideband input matching. But because of feedback mechanism, it can’t achieve high gain to suppress noise of the next stages. Fig.
A-1 (d) is LC 3’rd Chebyshev band-pass filter. It can perform good input matching, but it consumes large chip area because of using four inductors for input matching.
The noise performance of an LNA is directly dependent on its input matching.
The wide-band input matching is intrinsically noisier than narrow-band counterparts as the noise performance can not be optimized for a specific frequency. Thus the designer has to be trade off between the input matching and noise.
Distributed amplifiers [31]
The Fig. A-2 shows a basic four-stage single-ended distributed amplifier.
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Fig. A-2 Basic four single-end distributed amplifier
The distributed amplifiers normally provide wide bandwidth characteristics but they consume large dc current due to the distribution of multiple amplifying stages, which make them unsuitable for low-power application. And the distributed amplifiers are not optimized for noise. This bring the challenge of finding a low-power topology that satisfies all the other design requirements, the most stringent one being the input match.
Ultra-wideband low noise amplifier using LC-ladder filter input matching network [32][33]
Recently another topology of wideband LNA has been present. It expands the conventional narrow-band LNA using source degeneration by embedding the input network of the amplifying device in a multisection reactive network so that the overall input reactance is resonated over a wider bandwidth. Fig. A-3 shows a typical narrowband cascode LNA topology and its small-signal equivalent circuit.
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Fig. A-3 Narrowband LNA topology. (a) overall schematic. (b) Small-signal equivalent circuit at the input
The inductor Ls is added for simultaneous noise and input matching and Lg for the impedance matching between the source resistance Rs and the input of the narrowband LNA [14]. Fig. A-3(b) shows the equivalent small-signal circuit. Assume the gate-drain Cgd can be ignored, the impedance of the gate terminal is a series RLC circuit. The reactive part of the input impedance is resonated at the carrier frequency in narrowband design. The basic concept of the LC-ladder input matching is expanded from the input impedance of the narrowband which is a series RLC circuit. Consider a fourth-order bandpass ladder filter, shown as in Fig. A-4.
Fig. A-4 Fourth-order bandpass ladder filter used for impedance matching.
The right part of the bandpass filter looks similar to the equivalent circuit of the inductively degenerated transistor in Fig. A-3(b). Therefore, the bandpass filter can embed the inductively degenerated transistor and obtain the desire input impedance.
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The LC-ladder filter input matching of wideband LNA has two significant drawbacks.
Because the LC-ladder filter at the input mandates a number of reactive elements, which could lead to a larger chip area and noise figure degradation in the case of on-chip implementation.
Ultra-wideband low noise amplifier using the common-gate as the first stage.[34]
In traditional narrow-band receiver the common-gate is not used widely due to its relatively lower gain and higher noise figure than a common-source amplifier. The actual configuration of common-gate stage is shown in Fig. A-5(a).
Fig. A-5 (a) Configuration of a common-gate input stage.
(b) The small-signal equivalent circuit.
From the Fig. A-5(b), we can derive the input impedance
) frequency band of interest.
)
After some mathematical calculation
- 61 - relatively constant within the 3.1-10.6GHz UWB band. The imperfect matching of the common-gate stage throughout the band arise from the frequency dependent Xs(ω) that dominates the imaginary part in the denominator. To get a good matching over the wide band , the LC tank of Xs(ω) formed by Ls and Cgs should be selected such that they resonate at the center of the 3.1-10.6GHz, leaving only a 50Ω real input impedance. The noise figure of the common-gate input stage UWB LNA can be improved by increasing gm1 but it will degrade the input matching.
Wideband matching using the transistor intrinsic gate-drain capacitor [35]
Recently a novel wideband input match has been present. It considers the gate-drain capacitor has significant effect on the circuit performance. The Fig. A-6 show a simple common source amplifier with source degeneration inductor and the drain loaded an equivalent capacitor and resistor from the next stage.
Fig. A-6 The small signal equivalent circuit of common-source with inductive source degeneration
The Cgd and ro are neglected in conventional analysis of low noise amplifier. It is inaccurate numerically. If both Cgd and ro are considered we will find that the input match at high frequency is depend on the resistive load and at low frequency is depend on the capacitive load. We can achieve wideband match without external input
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match network. It also can achieve low noise match. Therefore, we will adopt this wideband matching method as a part of the proposed LNA.
A.2 Design Consideration
A.2.1 Wideband matching technique[35]
Consider a small signal equivalent circuit of a source degeneration low noise amplifier which is shown in Fig. A-7. CL and RL present the parasitic capacitance and resistance which is contributed from the next stage.
Fig. A-7 The small signal equivalent circuit of source degeneration
To derive the input impedance we consider that the load of the circuit is divided into two parts, one of which is only a resistor RL which dominates at the high frequency and another is the capacitor CL dominates at the low frequency. The circuit of resistive loading is shown in Fig. A-8
Fig. A-8 The equivalent small signal circuit of resistive loading
- 63 -
Fig. A-9 The equivalent small signal circuit of capacitive loading
One of the two branches is looking into the capacitor Cgs and another is looking into the capacitor Cgd. Yα is the impedance looking into the Cgd and Zβ is the impedance
- 64 - rearranged as a simpler RLC circuit as shown in Fig.4-10
- 64 - rearranged as a simpler RLC circuit as shown in Fig.4-10