Chapter 1 Introduction
1.2 Thesis organization
This thesis will discuss about the two kinds of circuit and implementation for ultra-wideband applications. The contents consist of two major topics:” Design of current-reused LNA for UWB ” and “ 9−26GHz Wideband CMOS LNA Design ” , respectively in chapter 2 and chapter 3. In these chapters, we will propose the architecture and explain the circuit. The circuit principles, design consideration and Layout consideration will be analyzed.
In chapter 2, we discuss several researches recently. By improving their drawback, we proposed current-reused amplifier which stacking NMOS and PMOS. The input impedance can be achieved 50 over the frequency band of interest and the gain will not reduce due to the enhancement of transconductance. The details will be explained in chapter2.
In chapter 3. Base on the technology of the narrowband LNA, we use the LC matching and five-stage common source cascade architecture to achieve a wideband 9 – 26 GHz and low noise circuit. The details will be explained in chapter 3.
Chapter 2
Design of Current-Reused LNA for UWB 2.1 Introduction
The ultra-wideband (UWB) system is a high data rate , low power consumption and for a short range wireless personal area network technology [2][3]. Because it can handle the requirement of high transmission speed for the multimedia material ( for example phantom and sound ) , it becomes more and more popular for wireless system. The FCC has defined 7500 MHz bandwidth in 3.1 - 10.6 GHz frequency range ( lower band : 3.1 – 5 GHz ; upper band : 6 – 10.6 GHz ) for the UWB standard IEEE 802.15.3a.
One of the challenges is to design the front-end LNA. Because it is the first block in the radio receiver, its performance will affect the sensitivity of the overall system. Thus, it is necessary for an LNA to boost the desired signal power while adding as little noise and distortion as possible so that the retrieval of this signal is possible in the later stages in the system.
2.2 Numerous topology of wideband LNA
Because of the input matching can directly affect the noise performance of an LNA.
Thus, there are some researches that can provide 50 input impedance over a wide bandwidth will be discussed as follow.
Fig.2.1 (a) The transformer feedback amplifier
(a) The transformer feedback amplifier[4][5]
The transformer feedback topology has good input matching entire frequency band of interest.
There is no input matching devices in the input gate of the purpose circuit, so that the LNA can achieve lower NF. However, the transformer silicon set up is very sensitive to the
technology dispersions thus strengthening the design hardness.
Fig.2.1 (b) Resistive shunt-feedback amplifier
(b) Resistive shunt-feedback amplifier[6]
The resistive shunt-feedback topology could have better bandwidth than conventional low noise amplifier, but it has limited input matching or NF and vice versa. In other words, the resistive shunt-feedback amplifier exhibits trades off in terms of bandwidth, input matching and NF. Indeed, its lower voltage gain will cause the noise of next stage won’t be suppressed.
Fig.2.1 (c) The common-gate amplifier
(c) Common-Gate amplifier[7]
The input impedance is approximately as
gs m
in g jwC
Z 1
. In the low frequency, the input impedance is approximately as
m
in g
Z 1
. It is easy to be matched to the 50 . However,
with the increasing of the operating frequency, the parasitic transistor capacitance (C ) gs degrades the amplifier performance in the high frequency. In addition, its noise is also larger
than that of the other topologies.
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Fig.2.1 (d) The distributed amplifier
(d) Distributed amplifier[8]
The distributed amplifier that can provide wide bandwidth and relatively flat gain over entire frequency band of interest. However, due to multiple transistor stages and much inductors are used so that the drawback is large power consumption and occupies large die size, respectively. In one word, it will make them unsuitable for integration.
Here, we proposed a LC ladder with current-reused topology for input matching as shown in Fig.2.2. To combine a NMOS and a PMOS transistor using the same supply voltage allows LC ladder technology to be low voltage compatible[9].
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Fig.2.2 The LC ladder with current-reused topology
2.3 Conventional current-reused amplifier
Fig.2.3 shows the topology of current-reused amplifier. The current reused configuration can be considered as two-stage casade amplifier [10] [11], where the first stage M1 and the second stage M2 are two common-source amplifiers. The function of L1 and C1 is to perform a series-resonant with C of gs M for a low impedance path, and the impedance of 3
L2 is quite large to provide a high impedance path to block RF signal. Consequently, the RF signal can be amplified twice by this co-current structure. Because the resonate circuit
composed of L1 and C1 presents a narrowband characteristic, the current reused topology is designed to boost the gain at upper end of the required band. R1 and L is used to 3 compensate the high gain roll-off of the circuit. Due to the increased impedance of the L1 and C1 path, the function of current reused amplification is degraded at lower end of the designed band. However, by using LC ladder at input with current reused topology, an overall wideband flat-gain performance can be achieve.
Fig.2.3 The current-reused amplifier topology
2.4 Architecture
The proposed UWB LNA as shown in Fig.2.4 employs three stages. This circuit is designed to require three bias voltage sources of 1.0V (V ), 0.7V (dd V ) and 1.2V (g Vbias). The first input stage including LC ladder and M1p, M1n is current-reused configuration. It can provide wideband matching. The second stage M2 and the third stage M3 are current-reused configuration, too. A large resistor RL (5K ) is employed in bias circuit to isolate noise of voltage source from internal circuit. The function of C in input stage is to make the gate g wideband flat-gain performance can be achieve.
Fig.2.4 Schematic of the proposed UWB LNA
2.5 Design Considerations 2.5.1 Input matching analysis
The proposed LNA use a fourth-order bandpass ladder filter to match 50 . The fourth-order bandpass ladder filter is shown in Fig.2.5[12].
Fig.2.5 Fourth-order bandpass filter used for impedance matching
From the results of recent research, we can find that the input impedance of the fourth-order bandpass ladder filter across the overall passband from WL to W is equal to a constant U resistance R as shown in Fig.2.6.
Fig.2.6 Input impedance of the bandpass filter versus frequency
By means of a first approximation of the upper frequency (W ) and the lower frequency (U WL) of this LC ladder filter is given by:
1 ladder filter can provide a real impedance over a frequency band of interest. Because of the Fig.2.5 shows, the equivalent circuit of the inductively degenerated transistor in Fig.2.5 looks like the right part of the bandpass filter. Therefore the overall input matching small signal equivalent circuit is shown in Fig.2.7.
Fig.2.7. The overall input matching small signal equivalent circuit
According to the novel wideband feedback mechanism proposed by [13].CL and RL are the parasitic capacitance and resistance which is contributed from the next stage. The capacitor CL dominates at low frequency and the resistor RL dominates at high frequency. The LNA input equivalent circuit at high frequency is shown in Fig.2.8.
Fig.2.8 Input small signal equivalent circuit at high frequency
While we assume that WLS,tot<<
tot
WCgs,
1 ,WLS,tot<<R and we can find the input L
impedance can be expression as following equation :
g
Fig.2.9 Input small signal equivalent circuit at low frequency
The LNA input equivalent circuit at low frequency is shown in Fig.2.9. In order to analysis the input impedance, we apart this circuit into two branches. Therefore, we can find the input
impedance is 1 ) Therefore, when the values of the inductors are designed properly, the input impedance will approach the 50 .
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Fig.2.10 Simulated input reflection coefficients
Fig.2.11 Simulated input reflection coefficients
Fig.2.10 and Fig2.11 shows the simulated input reflection coefficients (S11) and the simulated output reflection coefficients (S22), respectively. As can be seen, the curve is near by the center of the Smith chart when frequency increases from 3.1GHz to 10.6GHz. In other words, this design can achieve wideband input matching successfully.
2.5.2 Gain analysis
Because of the current-reused configuration, the stacking NMOS and PMOS increase transconductance from g to approximately 2m g .In addition, by using m L4 and C2 is to perform a series-resonant with C of gs M4 for a low impedance path, and the impedance of
L is quite large to provide a high impedance path to block RF signal. Consequently, the RF 3
signal can be amplified twice by two current-reused configuration, respectively.
2.6 Chip implementation and simulated result 2.6.1 Layout considerations
The chip layout of the proposed LNA is shown in Fig.2.12, The skill of layout is very important for radio frequency circuit design, because high frequency will make more coupling and parasitic effects occur to influence performances. To get the high speed that the 0.18 m gate length was chosen. All elements with guard-rings can prevent noise and interference from substrate. Because the RF pad has parasitic capacitance that will degraded the RF signal, the RF pad with its size is 50 × 50 m2 will be used. The smaller pad size can lead to a smaller parasitic capacitance. The bypass capacitors are used between each voltage source node and ground node to ensure voltage working like ground in AC and filter out noise. All connection wires are simulated by ADS momentum to extract parasitical effect.
Fig.2.12 Chip layout of the UWB LNA.
2.6.2 Simulated result
The chip size of the proposed LNA is 0.9690.895mm and it is fabricated using TSMC 2 0.18 m mixed-signal/RF CMOS 1P6M technology. The total consumption is 17.758mW with bias voltage source of 1.0V and 1.2V. The simulated result of the input return loss (S11) and the output return loss (S22) in Fig2.13 and Fig2.14 is lower than -10 dB, respectively. The gain (S21) in Fig2.15 is 13dB~14.3dB over 3.1 ~10.6 GHz. The noise figure (NF) performance is shown in Fig.2.17. The simulated NF has maximum 4.65dB and minimum 3.34dB. The simulated input-referred third-order intercept point (IIP3) at three frequency points are shown in Fig.2.18 (a) ~ (c). The simulated IIP3 shows -9dB at 3.1GHz, -7dB at 6.8GHz, -6.2dB at 10.6GHz. The simulated input-referred 1dB compression point (P1dB) are
shown in Fig.2.19 (a) ~ (c). The simulated P1dB shows -23.4dB at 3.1GHz, -21.2dB at 6.8GHz, -20.3dB at 10.6GHz. The performance summary is listed in table 2.1.
The performances of the proposed UWB LNA are compared with other works for UWB band listed in Table2.2.
Fig.2.13 Simulated result of S11
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Fig.2.15 Simulated result of S21
Fig.2.16 Simulated result of S12
Fig.2.17 Simulated result of NF
(a)
(b)
(c)
Fig.2.18 Simulated results of IIP3 at (a) 3.1GHz. (b) 6.8GHz. (c) 10.6GHz.
(a)
(b)
(c)
Fig2.19 Simulated results of P1dB at (a) 3.1GHz. (b) 6.8GHz. (c) 10.6GHz
Specification Post Simulated Input Return Loss (dB) -20.9 ~ -10.9
Output Return Loss (dB) -17.4 ~ -11.1
Gain (dB) 13 ~ 14.3
Isolation (dB) -34.7 ~ -80.0
IIP3 (dB) -9 ~ -6.2
P1dB (dB) -23.4 ~ -20.3
NF (dB) 3.34 ~ 4.65
V (V) dd 1.0V
Power Consumption 17.75mW
Table 2.1 Performance summary of the proposed LNA
Table 2.2 Comparison of UWB LNA
Chapter 3
9−26GHz Wideband CMOS LNA Design 3.1 Introduction
Square Kilometer Array (SKA) is one the most advanced radio telescope technology. Its observation and operation frequencies are 100MHz - 25GHz. The Square Kilometre Array (SKA) is a radio telescope in development which will have a total collecting area of approximately one square kilometre. It will operate over a wide range of frequencies and its size will make it 50 times more sensitive than any other radio instrument. By utilizing advanced processing technology it will be able to survey the sky more than ten thousand times faster than ever before.In the outer space communication aspect, in NASA Space Communication and Navigation Architecture Recommendations for in 2005-2030 of Space Communication Architecture Working Group (SCAWG) has the very clear introduction to the future outer space communication construction[14]. It divides SCA into approximately four regions : earth, moon, mars vicinity and deep space. And it uses the frequency of UHF, S, L, K, Ku and Ka frequency bands. For example, Ground-based Earth Element to Near-Earth Relay Element is use 13 ~ 15 GHz and Launch Vehicles、Earth Orbital User、Lunar Surface and Orbital User is use 22 ~ 27 GHz. Therefore, that is the reason we chose 9 – 25 GHz frequency band to design LNA. The table.3.1 shows the used frequency band of the applications.
Application Frequency Band
Astronomy SKA 100MHz – 25GHz
Military EW / ECM 9 – 26 GHz
Satellite Communication Lower Ka-band 17.7 – 21.2 GHz Space Communication Ground to Space 13 – 15 GHz Space Communication Space to space 22 – 27 GHz
Table.3.1 The used frequency band of the applications
3.2 The principles of narrowband LNA
Fig.3.1 (a) The input part of a typical narrowband LNA Fig.3.1 (b) The small signal equivalent circuit
The input part of a typical narrowband LNA is shown as Fig.3.1 (a). The inductor L is g added for the simultaneous input matching and low NF [15]. Fig.3.1 (b) shows the small signal equivalent circuit for the input part of the narrowband LNA, where C is the gs gate-source capacitance of the transistor M1. The input impedance of the narrowband LNA
can be represented as T S frequency of M1. The reactive element can be designed to resonate at the interest frequency such that Z becomes a real value with in wTLS being to R . Therefore, we can match the S input impedance to 50 .
3.3 Architecture
The schematic of the proposed LNA is shown in Fug.2.2. This circuit uses two bias voltage sources of V and dd V . It employs five-stage common source cascade architecture to g enhance the gain. The inductors which are inserted between each stage are to boost the gain and to match the circuit. The capacitances which are inserted between each stage are to block DC signal and to match the circuit, too.
Fig.3.2 The schematic of the proposed LNA
3.4 Design Considerations
Fig.3.3 The overall input matching small signal equivalent circuit
The overall input matching small signal equivalent circuit is shown in Fig.2.2.
According to the novel wideband feedback mechanism proposed by [13].CL and RL are the parasitic capacitance and resistance which is contributed from the next stage. The capacitor CL dominates at low frequency and the resistor RL dominates at high frequency. Therefore, the wideband circuit can be divided into two parts. The LNA input equivalent circuit at high frequency is shown in Fig.2.6
Fig.3.4. Input small signal equivalent circuit at high frequency
While we assume that WL <<S WCgs
1 , WL <<S R and we can find the input L
impedance can be expression as following equation where
]
Fig.3.5. Input small signal equivalent circuit at low frequency
The LNA input equivalent circuit at low frequency is shown in Fig.2.3. In order to analysis the input impedance, we apart this circuit into two branches. Therefore, we can find the input impedance is Z =in
Y Z
1. (3-4)Y = 1 ) 1
Fig.3.6 and Fig3.7 shows the simulated input reflection coefficients (S11) and the simulated output reflection coefficients (S22), respectively. As can be seen, the curve is near by the center of the Smith chart when frequency increases from 9GHz to 26GHz. In other words, this design can achieve wideband input matching successfully.
Fig 3.6 Simulated input reflection coefficients
Fig 3.7 Simulated output reflection coefficients
Insert the power trace into layer2 and layer 4 ground rings. It will be equal an inductance to avoid signals feedback as Fig3.8 shows.
Fig.3.8 The power line of the proposed LNA
In order to achieve high gain, we use five-stage common source cascade architecture.
Therefore, the RF signal can be amplified by five common source amplifiers.
Unlike other complex LC matching network, this proposed LNA uses only one inductor in the input stage. Therefore, the proposed LNA will achieve low noise figure over the frequency band of interest.
3.5 Chip implementation and simulated result
The chip size is 0.974 X 1.294 (mm ) and is fabricated on TSMC 0.18 2 m mixed-signal/RF CMOS 1P6M technology as shown in Fig.3.9. Complete simulated results were simulated by ADS momentum. We will present two different biases voltages condition. The total power consumption is 100 mW at Vg 0.8V , Vd 2.0V and the other one is 64.8 mW at
V
Vg 0.8 , Vd 1.4V . The total performance summary will show in table3.2 and table3.3, respectively.
Fig.3.9 Chip layout of the UWB LNA
3.5.1
When Vg 0.8V and Vd 2.0V :The simulated result of the input return loss (S11) and the output return loss (S22) in Fig.3.10 and Fig.3.11 is lower than -10 dB, respectively. The gain (S21) in Fig.3.12 is 20dB~21.2dB over 9 ~ 26GHz. The maxi mum variation of power gain is about 1dB.
The noise figure is between 2.4dB ~ 5.4dB as shown in Fig.3.14.The simulated input-referred third-order intercept point (IIP3) at three frequency points are shown in Fig.3.15 (a) ~ (c). The simulated IIP3 shows -17dB at 9 GHz, -11dB at 18 GHz, -8dB at 26 GHz. Fig.3.16 presents stable factor K, Mu, and B. When Mu > 1, K >1, and B >0, the proposed circuit will be unconditional stable. The performance summary is listed in table 3.2.
Fig.3.10 Simulated result of S11
Fig.3.11 Simulated result of S22
Fig.3.12 Simulated result of S21
Fig.3.13 Simulated result of S12
Fig.3.14 Simulated result of NF
Fig.3.15 Simulated results of IIP3 at (a) 9 GHz.
Fig.3.15 Simulated results of IIP3 at (b) 18 GHz.
Fig.3.15 Simulated results of IIP3 at (c) 26 GHz.
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Fig.3.16 Simulated result of Stability (K: Dot line; Mu: Solid line; Thin line)
Specification Post Simulated
Input Return Loss (dB) -10.4 ~ -29.9 Output Return Loss (dB) -10.0 ~ -18.9
Gain (dB) 20 ~ 21.2
Isolation (dB) -68.5 ~ -91.1
IIP3 (dB) -17 ~ -8
Max. NF (dB) 5.4
Min. NF (dB) 2.4
V dd 2.0V
Power Consumption 100 mW
Table3.2 Performance summary of the proposed LNA
3.5.2
When Vg 0.8V and Vd 1.4V :The simulated result of the input return loss (S11) and the output return loss (S22) in Fig.3.16 and Fig.3.17 is lower than -10 dB, respectively. The gain (S21) in Fig.3.18 is 17.8dB~18.3dB over 9 ~ 26GHz. The maximum variation of power gain is less than 1dB. The noise figure is between 2.7dB ~ 5.8dB as shown in Fig.3.20. The simulated input-referred third-order intercept point (IIP3) at three frequency points are shown in Fig.3.21 (a) ~ (c). The simulated IIP3 shows -16dB at 9 GHz, -10dB at 18 GHz, -9dB at 26 GHz. Fig.3.22 presents stable factor K, Mu, and B. When Mu > 1, K >1, and B >0, the proposed circuit will be unconditional stable. The performance summary is listed in table 3.3.
Fig.3.17Simulated result of S11
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Fig.3.18Simulated result of S22
Fig.3.19Simulated result of S21
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Fig.3.20imulated result of S12
Fig.3.21Simulated result of NF
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Fig.3.22Simulated results of IIP3 at (a) 9 GHz.
Fig.3.22Simulated results of IIP3 at (b) 18 GHz.
Fig.3.22Simulated results of IIP3 at (c) 26 GHz.
Fig.3.23Simulated result of Stability (K: Dot line; Mu: Solid line; Thin line)
Specification Post Simulated Input Return Loss (dB) -10.3 ~ -36.4
Output Return Loss (dB) -10.6 ~ -19.9
Gain (dB) 17.8 ~ 18.3
Isolation (dB) -65.7 ~ -89.6
IIP3 (dB) -16 ~ -9
Max. NF (dB) 5.8
Min. NF (dB) 2.7
V dd 1.4V
Power Consumption 64.8 mW
Table3.3 Performance summary of the proposed LNA
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Chapter 4
Conclusion and Future Work
4.1 Conclusion and Future Work
This thesis contains two studies: the low noise amplifier with current reused topology, and the 9 – 26GHz CMOS ultra-wideband low noise amplifier. For the first circuit, the LC ladder current reused configuration is used as input matching with low voltage. The current reused configuration can be considered as two-stage casade amplifier. Therefore, the RF signal can be amplified twice by this co-current structure to achieve high gain. The simulated result shows the good input and output matching will be achieved and maximum 14.3dB power gain is attained. The simulated noise figure is between 3.134 ~ 4.65dB within the wideband.
For the second circuit, we propose a 9 - 26 GHz wide band 0.18μm MOS low noise amplifier.
It is five-stage cascade circuit topology and match input impedance by output RC loading and source inductance. This amplifier achieves a 20.6 ± 0.5 dB power gain, 2.4 ~ 5.4dB noise figure, and good input、output matching at Vg 0.8V and Vd 2.0V . Indeed, the other
bias voltage condition Vg 0.8V and Vd 1.4V , this amplifier achieves a 18 ± 0.2 dB power gain, 2.7 ~ 5.8dB noise figure, and good input、output matching .Obviously, the design of this circuit can tolerate the large variation of bias voltage. The result indicates that the amplifier has lower noise figure by using output RC loading and source inductance to match impedance, and standard 0.18μm MOS process can work for millimeter-wave wideband applications.
References
[1] WPAN High Rate Alternative PHY Task Group 3a (TG3a), IEEE 802.15, 2007 [Online].
Available: http://www.ieee802.org/15/pub/TG3a.html
[2] G. R. Aiello and G. D. Rogerson, “Ultra-wideband wirelesssystems,” IEEE Microwave Mag., vol. 4, pp. 36-47, June2003.
[3] S. Roy, J. R. Foerster, V. S. Somayazulu, and D. G. Leeper,“Ultrawideband radio design:
the promise of high-speed,shortrange wireless connectivity,” Proc. IEEE, vol. 92, pp.295-311, Feb. 2004.
the promise of high-speed,shortrange wireless connectivity,” Proc. IEEE, vol. 92, pp.295-311, Feb. 2004.