Chapter 1 Introduction
1.3 Thesis Organization
We will propose a new structure of nonvolatile memory without complex oxide-nitride-oxide gate stack in chapter 2. In chapter 3, the fabrications and electrical characteristics of Segmented n-MOSFET will be demonstrated. Then the Segmented p-MOSFET with the same fabrication processes is demonstrated. Finally the conclusions and future work of this thesis will be given in chapter 5.
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Chapter 2
Characteristics of Nonoverlapped Implantation Nonvolatile Memory
2.1 Introduction
SONOS memories have been developed as two-bit-per-cell operation for high density nonvolatile memory (NVM). Novel operating schemes and array designing offer improved performance and cell area, such as CHISEL and buried diffusion bit-line ,etc.[20]
Nevertheless, such SONOS devices are facing difficulties while scaling down, such as two-bit operation and oxide-nitride-oxide down scaling. Recently, the use of SiN spacers as the charge trapping media has provided another means of these issues [21]. Fuduka et al.[22]
reported SiN sidewall between silicon oxide spacer and polysilicon gate for NV applications.
Jeng el al.[23] reported nonoverlapped implantation (NOI) devices with SiN spacer as trapping media. The NOI devices can be manufactured without additional masks and complex process such as ONO dielectrics. For two-bit operation, the trapping spacers are physically separated by the gate electrode and gate oxide, so the scaling risk of two-bit charge merging can be avoided in NOI devices. Furthermore, these advantages are attractive for embedded NVM applications in standard logic CMOS technologies to improve the system operation speed. We choose HfO2 and HfSiOx for trapping layer under the SiN spacer for these NVM devices. The structure is shown in Fig. 2-1.
2.2 Device Fabrication
The schematic diagram of the fabrication process is illustrated in Fig. 2-2. First, the
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active region was defined by LOCOS process. Then 100Å gate oxide was grown in dry oxide furnace after RCA clean. Subsequently, 2000 Å amorphous silicon was deposited as gate electrode. After poly gate was defined and etched, 50 Å TEOS oxide or dry oxide was deposited as tunneling oxide and blocking oxide. We noted that the dry oxide can provide better interface quality than TEOS oxide as the tunneling oxide since the oxide is grown from single crystal silicon, but the dry oxide on the sidewall might show worse quality than TEOS oxide because the dry oxide is grown from amorphous silicon. After solid phase crystallization (SPC) was performed, 50 Å high-k trapping layer was deposited as trapping layer. SiN was then deposited and etched to form spacer, which has higher k value than SiO.
Nanocrystal trapping layer was performed at 900℃ for 60 sec. Fig. 2-3 is the TEM picture of the nanocrystal, which is grown just for a capacitor structure and then annealed at the same conditions. Gate, source and drain were doped by a self-aligned ion implantation. After S/D formation, which was activated at 1000 ℃ for 10 sec, SiO passavation and AlSiCu metallization were performed to complete the spacer trap NVM. This gate stack contains only dray oxide and gate electrode, so this process is similar to the logic devices. For example, if the LDD and other dopants are implanted before spacer formation, this device might be used as logic device. The logic device structure is shown is Fig. 2-4.
2.3 Results and Discussion
2.3.1 Measurement of Threshold Voltage
The threshold voltage measurement is constant current method in Id-Vg curve. We observed that Id was limited at small Vd, due to the channel resistance under the spacer is large. Therefore, the drain voltage is applied at 2V in our Id-Vg measurement for threshold voltage.
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2.3.2 Drain Current vs Gate Voltage
The ID-VG curves are shown in Fig. 2-5(a),(b), and the characteristics is shown in Table 2-1. We choose 10V gate stress and 8V drain stress for 1ms to measure the programmed state.
The subthreshold swing is about 200~300mV/decade at erase state. Because the region of the substrate under the spacer is not implanted as LDD source/drain, the channel under the spacer is more difficult to turn on than the channel under the gate electrode. Thus the subthreshold swing is large. After programmed, the channel under the spacer with larger resistance regress the subthreshold swing to 250~450mV/decade.
2.3.2 Programming Characteristics 2.3.2.1 Programming Mechanism
In this chapter, the programming scheme is executed by using channel hot electron injection (CHEI) to move charge in trapping layer, thus threshold voltage could be changed.
Fig. 2-6 shows the hot electron injection scheme and band diagram in this spacer trap NVM.
The electrons are hot because they are accelerated in the channel and heated into high-energy state. A part of the electrons owns energy which is higher than the barrier height of the SiO2/Si conduction band, so the electrons can surmount the barrier and are injected into the trapping layer.
2.3.2.2 Programming Properties
The program characteristics with different tunneling/blocking oxide are shown in Fig.
2-7. The TEOS oxide provides better programming speed at long stress due to the oxide quality above the NOI channel because the TEOS oxide contains more interface states than dry oxide grown from single crystal silicon and the TEOS oxide can provide more tunneling
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paths. The program characteristics with different gate bias are shown in Fig. 2-8. The programming speed is faster with the higher gate voltage because the charges are with more energy. Furthermore, the gate bias provides larger electric field and enhances the tunneling.
The program characteristics with different drain bias are shown in Fig. 2-9. The programming speed isn’t corresponding to the drain voltage. We can see that the best programming efficiency isn’t with the largest drain voltage. There are two possible explanations. First, the distribution of the electrons in the spacer of smaller programming voltage might cause more threshold voltage shift. Second, the gate oxide might be destroyed at high programming voltage.
2.3.3 Erasing Characteristics 2.3.3.1 Erasing Mechanism
The erase scheme is executed by band-to-band hot hole, which is shown in Fig. 2-10.
The drain is applied on a positive voltage while the gate is applied on a negative voltage. The holes have high energy while they reach the oxide are injected in to the trapping layer to neutralize the trapped electrons and the threshold voltage decreases.
2.3.3.2 Erasing Properties
Fig. 2-11 shows the erase characteristics with different tunneling/blocking oxide after pre-programming. 1V threshold voltage shift pre-programming. The pre-programming time is about 0.1ms and the pre-programming gate/drain voltages are 10V/8V. The TEOS oxide on sidewall provides better blocking ability for gate injection than amorphous-Si dry oxide. Due to the gate injection from gate into nanocrystal at sidewall of poly gate, we observe that the erase curve raise after 1ms. Fig. 2-12 shows the erase characteristics with different gate bias.
Before 10μs, 10V gate voltage provides little better erase speed, but the gate injection is also
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Retention is an important reliability issue for non-volatile memory. The de-trapping of the electrons trapped in the trapping layer decreases the threshold voltage, thus the window between program-state and erase-state becomes narrower. Normally, there’s more charge loss at higher temperature.
2.3.4.2 Retention Properties
As shown in Fig. 2-14(a),(b) , after 1.5V of threshold voltage shift by programming, the retention properties is almost remain at the same threshold voltage for 1000s at 25℃. After 1000s the threshold voltage even increases with waiting time. Like most retention characteristics, the retention curves for 125℃ are under 25℃, so the charge loss is more at higher temperature.
However, it’s not a typical trend in a retention curve for NVM that the threshold voltages increase by time. The threshold voltage drops or remains at first 1000s, and then some of the threshold voltages are raised after. One possible reason is that the device might be programmed while measuring ID-VG curves. But after measuring ID-VG for 20 cycles at 0s and 10000s, the threshold voltage doesn’t change as the retention curve. So this non-typical trend isn’t caused by the programming effect at the ID-VG measurement after each waiting time. The mechanism of the threshold voltage raising may be caused by the thermal migration of the charge in nitride spacer. As shown in Fig. 2-15, the migration of trapped charges changes the threshold
10 voltage. According to the equation,
, where Q0 is the oxide trapped charge, C0 is the oxide capacitance, d is oxide thickness, and x0 is the distance from gate electrode to trapped charge. While the trapped electrons move to the substrate, the flat-band voltage is affected more due to the increasing of x0.
2.3.5 Disturbance Characteristics 2.3.5.1 Disturbance Mechanism
The read disturbance takes place under the applied stress while reading the cell. The applied read voltage might turn on the channel or enhances tunneling to make electrons in the substrate into trapping layer and then the threshold voltage changes. Memory cells are often put in arrays to reduce the memory area and to simplify outside electric circuits. Therefore, the drain disturbance and gate disturbance need to be considered while neighboring cells especially un-programmed cells are stressed during some cell is being programmed. Fig. 2-16 shows the schematic circuitry of a memory array. During programming cell A, gate disturbance occurs in the cell B and same for those cells connected with the same word-line because the gate stress is applied to the same word-line (WL). This is called gate disturbance.
During programming cell A, drain disturbance occurs in the cell C and same for those cells connected with the same bit-line because the drain stress is applied to the same bit-line (BL).
This is called drain disturbance.
2.3.5.2 Disturbance Properties
Fig. 2-17~19 show the read, gate, and drain disturbance characteristic, respectively. The threshold voltage shifts with the stress time, especially after 100s for all three kinds of
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disturbance. After 100s of stress, electrons are programmed into the trapping layer due to the high gate voltage in gate disturbance measurement, high drain voltage in drain disturbance measurement, and the channel which the carriers are “not so hot” with lower energy than the programming operation causes read disturb. And the dry oxide provides better blocking ability than the TEOS oxide above the NOI channel.
2.4 Summary
The programming speed of these devices shows programming properties by CHE programming mechanism. However, the erase saturation limits the erase properties. The retention is good, but the charge injected into the nitride spacer redistribution make the threshold voltage increase by waiting time. The disturbance curves show that these devices are a little programmed after 100s gate/drain/read stress.
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trapping layer tunneling/blocking oxide initial SS(mV/decade)
programmed SS(mV/decade)
HfSiOx dry oxide 274 402
HfSiOx TEOS oxide 231 278
Table 2-1 electrical properties of nonoverlapped implantation nonvolatile memory
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source drain
gate
gate channel NOI channel
parasitic trapping layer blocking oxide
tunneling oxide SiN spacer
trapping layer
4
Fig. 2-1 structures of nonoverlapped implantation nonvolatile memory
14 1. Si Substrate
2. Gate oxide
3. α-Si gate electrode
4. Gate definition
5. Tunneling/blocking oxide (dry oxide/TEOS)
6. High-k trapping layer
7. SiN spacer, SPC, and high-k annealing
8. S/D implantation and activation
Fig. 2-2 fabrication process of nonoverlapped implantation nonvolatile memory
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SiO2 SiO2
HfSiOx nanocrystal
Fig. 2-3 TEM picture of nonoverlapped implantation nonvolatile memory
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source drain
gate
gate channel LDD
spacer stack
Fig. 2-4 structure of logic device with similar fabrication process of nonoverlapped implantation nonvolatile memory
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dry oxide / HfSiOx initial state SS=274 dry oxide / HfSiOx programmed state SS=402
ID (A)
TEOS oxide / HfSiOx initial state SS=231 TEOS oxide / HfSiOx programmes state SS=278
ID (A)
VG (V)
Fig. 2-5 ID-VG curves of two states with (a) dry oxide (b) TEOS oxide as the tunneling/blocking oxide
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hot electron tunneling oxide
blocking oxide
SiN spacer
trapping layer parasitic trapping layer
poly-Si gate electrode
Si substrate cold electron
Fig. 2-6 channel-hot-electron injection programming mechanism
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1E-6 1E-5 1E-4 1E-3 0.01 0.1
0 1 2 3 4 5
TEOS / HfSiOx VG=9 VD=8 dry oxide / HfSiOx VG=9 VD=8
VTH shift(V)
Program Time(s)
Fig. 2-7 programming characteristics with different tunneling/blocking oxide
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1E-6 1E-5 1E-4 1E-3 0.01 0.1
0 1 2 3 4 5 6
dry oxide / HfSiOx VG=8 VD=8 dry oxide / HfSiOx VG=9 VD=8 dry oxide / HfSiOx VG=10 VD=8
VTH shift(V)
Program Time(s)
Fig. 2-8 programming characteristics with different gate bias
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1E-6 1E-5 1E-4 1E-3 0.01 0.1 0
1 2 3 4 5 6
dry oxide / HfSiOx VG=10 VD=7 dry oxide / HfSiOx VG=10 VD=8 dry oxide / HfSiOx VG=10 VD=9
VTH shift(V)
Program Time(s)
Fig. 2-9 programming characteristics with different drain bias
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h+
tunneling oxide blocking oxide
SiN spacer
trapping layer parasitic trapping layer
poly-Si gate electrode
Si substrate
e
-Fig. 2-10 band-to-band-hot-hole injection erasing mechanism
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1E-6 1E-5 1E-4 1E-3 0.01
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
TEOS / HfSiOx VG=-11 VD=8 dry oxide / HfSiOx VG=-11 VD=8
VTH shift(V)
Erase time(s)
Fig. 2-11 erasing characteristics with different tunneling/blocking oxide
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1E-6 1E-5 1E-4 1E-3 0.01 -2.0
-1.5 -1.0 -0.5 0.0 0.5 1.0
1.5 dry oxide / HfSiOx VG=-10 VD=8 dry oxide / HfSiOx VG=-11 VD=8 dry oxide / HfSiOx VG=-12 VD=8
V T H sh if t( V )
Erase time(s)
Fig. 2-12 erasing characteristics with different gate bias
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1E-6 1E-5 1E-4 1E-3 0.01
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
1.5
dry oxide / HfSiOx VG=-12 VD=8 dry oxide / HfSiOx VG=-12 VD=9 dry oxide / HfSiOx VG=-12 VD=10
V T H s h ift( V )
Erase time(s)
Fig. 2-13 erasing characteristics with different drain bias .
(a)
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10 100 1000 10000
0 1 2
dry oxide / HfSiOx 25C dry oxide / HfSiOx 125C
VTH shift (V)
Wait time(s)
(b)
10 100 1000 10000
0 1 2
TEOS / HfSiOx 25C TEOS / HfSiOx 125C
VTH shift (V)
Wait time(s)
Fig. 2-14 retention characteristics with (a)dry oxide (b)TEOS oxide as the tunneling/blocking oxide
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(b)
Fig. 2-15 electrons trapped in the spacer (a)before (b)after the charge migration
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A C
B
Fig. 2-16 NOR array circuit for nonvolatile memory
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Fig. 2-17 read disturbance characteristics with (a)dry oxide (b)TEOS oxide as tunneling/blocking oxide
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dry oxide / HfSiOx VG=10
VTH shift(V)
Fig. 2-18 gate disturbance characteristics with (a)dry oxide (b)TEOS oxide as tunneling/blocking oxide
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Fig. 2-19 drain disturbance characteristics with (a)dry oxide (b)TEOS oxide as tunneling/blocking oxide
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Chapter 3
Characteristics of Segmented n-MOSFET
3.1 Introduction
Recently, body-tied FinFETs built on bulk silicon (Si) wafer have been demonstrated experimentally [24][25][26] and have shown several advantages over SOI FinFETs while keeping nearly the same scaling down characteristics [27] as those of SOI FinFETs. The device is called bulk FinFETs to differentiate from SOI FinFETs. The bulk FinFETs have been considered as a promising candidate for future CMOS technology because the devices have several advantages such as low cost, low defect density, no floating body effect, high heat transfer rate to the substrate, and nearly the same process flow as conventional bulk CMOS technology.
3.2 Device Fabrication
The fabrication process steps are illustrated in Fig. 3-1. First, a bulk silicon wafer was defined active region by shallow trench isolation process. After well formation and threshold voltage-adjust ion implantation, the STI oxide was recessed by a small amount for split conditions. Then the poly gate was formed and defined, just prior to the gate oxide oxidation.
As a result, a tri-gate structure was achieved. After LDD and pocket implants, gate spacer was formed. Then the source/drain and gate was implants as self-alignment. The activation process and metal silicidation were the final steps of the front-end-of-line process. Fig. 3-2 is the TEM picture of the FIN structure.
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3.3 Results and Discussion
3.3.1 Device Structure of 3-point SegFETs
The SegFET devices were fabricated by 28 nm CMOS process, for different gate lengths, gate widths, and FIN numbers. The thickness of the gate oxide is about 12~20 Å, and the gate-to-S/D contact length is most 30 nm without body contacts. The diagram of top view of the devices is shown in Fig. 3-3.
3.3.2 Drain Current vs. Gate Voltage Curve
Fig. 3-4 shows the ID-(VG-VTH) curves for the SegFet devices, where VTH is extracted by constant drain current method. Ion-Ioff ratio reaches 108. And the curve between each STI-recess thickness is near to each other in the same gate length, so the channel properties are nearly beside threshold voltage. We noted that Ion/(W/L) increases with channel length. The trend is not typical as the short channel effect for short channel length devices. It will be explained after.
3.3.3 FIN Number and Electrical Properties
As shown in Fig. 3-5, the on current, which is the drain current divided by the FIN number, isn’t much dependent on the FIN number. Fig. 3-6 shows that the threshold voltage is also independent with the FIN number. So we assume that the interactions between the neighbor depletion regions which are parallel. The uniformity of the devices is good, since each FIN shows similar properties.
3.3.4 Drain Current vs. Gate Length
In Fig. 3-7, the normalized Ion is small at short channel region for each STI-recess
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conditions. We conjecture that the pocket implant concentration is too high that the dopants diffuses to the channel surface to increase the threshold voltage or diffuses to the source/drain LDD to increase the series resistance of source/drain. For the same top view width (Wtop), which is the real area of the chip, more recess devices provide larger on current, so the STI recess can maintain the driving current while scaling down. However, the on current of more STI-recess devices with the same real width (Wtotal=Wtop+2*STI recess) provides less normalized on current. Thus, the mobility of the devices with more STI-recess thickness decreases. It might be due to the pocket implant, and the sidewall-channel mobility degrades for more channel dopant concentration.
3.3.5 Threshold Voltage and Subthreshold Swing vs. Gate length
As shown in Fig. 3-8, the threshold voltage increases as the channel length decreases, especially at the sub-100nm region. The short channel effect isn’t the major effect at this region. Therefore, we calculated the subthreshold swing of these devices. Fig. 3-9 shows the subthreshold swing characteristics. The subthreshold swing curves show that the subthreshold swing of the shorter device is worse, and it’s corresponding to the short effect. It’s due to that the source/drain and pocket implantation profile couldn’t match good, thus the series resistance dominates the threshold voltage. Therefore, the on current and threshold voltage trend don’t show the short channel effect. Also, the subthreshold swing degenerates at short channel region because of the pocket implant profile.
We noted the subthreshold swing characteristics of the device with more STI recess thickness in smaller in Fig. 3-9. Obviously the “deeper” devices, which own more STI recess thickness, have smaller threshold voltages, as shown in Fig. 3-8. Fig. 3-10 is the scheme of different STI recess thickness. The deeper FINs’ depletion region from sidewall enhanced
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more volume of the FIN, thus the the inversion layer forms earlier than the device with less STI recess thickness. Therefore, the ”fully-depleted likely” mechanism decreased the threshold voltage and improve the subthreshold swing.
3.3.6 Device structure of 4-point Devices
To verify the fully-depleted effect, we measured other test structures, which have only one FIN but 4-point contacts, for body effect. The diagram of top view of the devices is shown in Fig. 3-11.
3.3.7 Threshold Voltage vs. Gate length on 4-point Devices
Similar to former devices, the threshold voltages decreases as the gate length increases, due to the pocket implant, as shown in Fig. 3-12. Also, 30nm-STI-recess devices own smaller threshold voltage, due to the corner effect and the sidewall depletion region.
3.3.8 Threshold Voltage vs. Gate width on 4-point Devices
Fig. 3-13 shows the relation between the channel width and threshold voltage. Certainly, the threshold voltage of more recess devices is smaller. Otherwise, the threshold voltage increases as the channel width, due to the top-sidewall channel ratio. As shown in Fig. 3-14 the sidewall channel affects more at narrower width, so the threshold voltage is suppressed.
3.3.9 Body Effect on 4-point Devices
To verify that the depletion region of sidewall helps the inversion of channel, we
To verify that the depletion region of sidewall helps the inversion of channel, we