Chapter 3 Characteristics of Segmented n-MOSFET
3.3.10 Kink Effect
the threshold voltage will increase with VSB . Fig. 3-15 shows the threshold shift-channel width curves. In deep-recess devices, the body voltage is blocked by the sidewall depletion region, so the threshold voltage shift is not much as shallow-recess devices. Similarly, the body voltage is blocked in the devices with narrower gate width.
3.3.10 Kink Effect
Fig. 3-16 shows the ID-VD curves of SegFET 3-point devices. The kink effect is obvious in 10 and 15 nm-recess devices but not obvious in 30nm-recess devices. The kink effect usually takes place at the partially-depleted devices on SOI wafer, but not in fully-depleted devices. According to Fig. 3-10, we may say that the depletion region of sidewall help the inversion earlier than conventional inversion mechanism of planar devices, so deep-STI-recess devices shows “fully depleted likely” characteristics.
3.4 Summary
The recess of STI oxide improves some characteristics of the devices. The operation speed is improved by the recess because the subthreshold swing is improved. However, the doping profiles of the LDD and pocket implant don’t match well so we couldn’t compare the short channel effect. We also noted that the sidewall depletion region affects the threshold voltage by corner effect. After measuring the body effect, the body voltage is blocked, and is dependent to the recess thickness and FIN width. Besides, the ID-VD curves also show that the FIN structure may cause fully depleted characteristics, like the devices on SOI wafer.
37
•6. LDD & pocket implantation
•7. Spacer formation
•8. S/D implantation
•5. Poly–Si gate electrode and gate definition
Fig. 3-1 fabrication process of Segmented MOSFET
38
Si FIN STI oxide
Poly-Si Silicide
contact
Fig. 3-2 TEM pictures of Segmented MOSFET
39 1
2 3
… N
W
Wtop=N*W
Wtotal=N*(W+2*STI recess )
G
S D
L
Fig. 3-3 scheme of top view of Segmented MOSFET
40
W=30 L=27 N=20 STI recess=10 W=30 L=27 N=20 STI recess=15 W=30 L=27 N=20 STI recess=30
ID/(W/L) (A)
W=30 L=27 N=20 STI recess=10 W=30 L=50 N=20 STI recess=10 W=30 L=100 N=20 STI recess=10 W=30 L=200 N=20 STI recess=10 W=30 L=1000 N=20 STI recess=10
ID/(W/L) (A)
VG-VTH (V)
Fig. 3-4 ID-VG curves for(a) different STI recess thickness (b) different gate length
41
STI recess=10, W=30, L=100 STI recess=10, W=30, L=55 STI recess=10, W=30, L=45 STI recess=10, W=30, L=32
ID/(W/L) (A)
STI recess=15, W=30, L=100 STI recess=15, W=30, L=55 STI recess=15, W=30, L=45 STI recess=15, W=30, L=35
ID/(W/L) (A)
STI recess=30, W=30, L=100, STI recess=30, W=30, L=55 STI recess=30, W=30, L=45 STI recess=30, W=30, L=32
ID/(W/L) (A)
N
Fig. 3-5 on current vs. FIN number for (a)10nm (b)15nm (c)30nm STI oxide recess
42
W=30, L=32, STI recess=10 W=30, L=45, STI recess=10 W=30, L=55, STI recess=10 W=30, L=100, STI recess=10
VTH (V)
W=30, L=32, STI recess=15 W=30, L=45, STI recess=15 W=30, L=55, STI recess=15 W=30, L=100, STI recess=15
VTH (V)
W=30, L=32, STI recess=30 W=30, L=45, STI recess=30 W=30, L=55, STI recess=30 W=30, L=100, STI recess=30
VTH (V)
N
Fig. 3-6 threshold voltage vs. FIN number for (a)10nm (b)15nm (c)30nm STI oxide recess
43 (a)
10 100 1000
1E-5
W=30 STI recess=10 N=20 W=30 STI recess=15 N=20 W=30 STI recess=30 N=20
Ion/(Wtop/L) (A)
L (nm)
(b)
10 100 1000
1E-5
STI recess=10,W=30,N=20 STI recess=15,W=30,N=20 STI recess=30,W=30,N=20
Ion/(Wtotal/L) (A)
L (nm)
Fig. 3-7 on current vs. gate length which on current is normalized by (a) top gate width (b) total gate width
44
10 100 1000
0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
W=30, STI recess=10, N=20 W=30, STI recess=15, N=20 W=30, STI recess=30, N=20
V T H ( V )
L (nm)
Fig. 3-8 threshold voltage vs. gate length
45
100 1000
65 70 75 80 85 90 95
STI recess =10 W=30 N=20 STI recess= 15 W=30 N=20 STI recess= 30 W=30 N=20
S S ( V /d e c a d e )
L(nm)
Fig. 3-9 subthreshold swing vs. gate length
46
Fig. 3-10 scheme of sidewall depletion region with different STI recess thickness
47 W
G
S D
B
LFig. 3-11 scheme of top view of 4-point FINFET
48
10 100 1000
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
W=500, STI recess=10 W=500, STI recess=15 W=500, STI recess=30
V T H ( V )
L (nm)
Fig. 3-12 threshold voltage vs. gate length on 4-point FINFET
49
100 1000 10000
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
L=50, STI recess=10 L=50, STI recess=15 L=50, STI recess=30
V T H (V )
W (nm)
Fig. 3-13 threshold voltage vs. gate width on 4-point FINFET
50
Fig. 3-14 scheme of sidewall depletion region with different gate width
51
100 1000 10000
0.0 0.1 0.2 0.3 0.4 0.5
L=50, STI recess=10 L=50, STI recess=15 L=50, STI recess=30
VTH shift (V)
W (nm)
Fig. 3-15 body effect between different gate width
52 STI=10 W=30 L=27 N=20 VG=0.5 STI=10 W=30 L=27 N=20 VG=1 STI=15 W=30 L=27 N=20 VG=0.5 STI=15 W=30 L=27 N=20 VG=1 STI=30 W=30 L=27 N=20 VG=0.5 STI=30 W=30 L=27 N=20 VG=1 STI=30 W=30 L=27 N=20 VG=1.5
ID (A)
VD (V)
Fig. 3-16 ID-VD curves for (a) 10nm (b) 15nm (c) 30nm STI oxide recess
53
Chapter 4
Characteristics of Segmented p-MOSFET
4.1 Introduction
In chapter 3, the characteristics of Si-bulk segmented n-MOSFET were shown. We’ll show the characteristics of Si-bulk segmented p-MOSFET with the same CMOS process.
4.2 Device Fabrication
As last chapter, the fabrication process steps are illustrated in Fig. 3-1. First, a bulk silicon wafer was defined active region by shallow trench isolation process. After well formation and threshold voltage-adjust ion implantation, the STI oxide was recessed by a small amount for split conditions. Then the poly gate was formed and defined, just prior to the gate oxide oxidation. As a result, a tri-gate structure was achieved. After LDD and pocket implants, gate spacer was formed. Then the source/drain and gate was implants as
self-alignment. The activation process and metal silicidation were the final steps of the front-end-of-line process.
4.3 Results and Discussion
4.3.1 Device Structure of 3-point SegFETs
The same as NMOS chapter 2, the P-SegFET devices were fabricated by 28 nm CMOS process, for different gate lengths, gate widths, and FIN numbers. The thickness of the gate oxide is about 12~20 Å, and the gate-to-S/D contact length is most 30 nm without body contacts. The diagram of top view of the devices is shown in Fig. 3-3.
54
4.3.2 Drain Current vs. Gate Voltage Curve
Fig. 4-1 shows the ID-(VG-VTH) curves for the SegFet devices, where VTH is extracted by constant drain current method. Ion-Ioff ratio reaches 108. And the curve between each STI-recess thickness is near to each other in the same gate length, so the channel properties are nearly beside threshold voltage. We noted that Ion/(W/L) increases with channel length. The trend is not typical as the short channel effect for short channel length devices, the same as NMOS devices.
4.3.3 FIN Number and Electrical Properties
As shown on Fig. 4-2, Ion, which is the drain current divided by the FIN number, isn’t much dependent on the FIN number. Fig. 4-3 shows the threshold voltage is also independent to the FIN number. So we assume that the interaction between the neighbor depletion regions which are parallel. The uniformity of the devices is good, since each FIN shows similar properties.
4.3.4 Drain Current vs. Gate Length
In Fig. 4-4 , the normalized Ion is small at short channel region for each STI-recess conditions. We conjecture that the pocket implant concentration is too high that the dopants diffuses to the channel surface to increase the threshold voltage or diffuses to the source/drain LDD to increase the series resistance of source/drain. For the same top view width (Wtop), which is the real area of the chip, more recess devices provide larger on current, so the STI recess can maintain the driving current while scaling down. However, the on current of more STI-recess devices with the same real width (Wtotal=Wtop+2*STI recess) provides less normalized on current. Thus, the mobility of the devices with more STI-recess thickness decreases. It might be due to the pocket implant, and the sidewall-channel mobility degrades
55 for more channel dopant concentration.
4.3.5 Threshold Voltage and Subthreshold Swing vs. Gate length
As shown in Fig. 4-5, the threshold voltage increases as the channel length decreases, especially at the sub-100nm region. The short channel effect isn’t the major effect at this region. Therefore, we calculated the subthreshold swing of these devices. Fig. 4-6 shows the subthreshold swing characteristics. The subthreshold swing curves show that the subthreshold swing of the shorter device is worse, and it’s corresponding to the short effect. It’s due to that the source/drain and pocket implantation profile couldn’t match good, thus the series resistance dominates the threshold voltage. Therefore, the on current and threshold voltage trend don’t show the short channel effect. Also, the subthreshold swing degenerates at short channel region because of the pocket implant profile.
We noted the subthreshold swing characteristics of the device with more STI recess thickness in smaller in Fig. 4-6. Obviously the “deeper” devices, which own more STI recess thickness, have smaller threshold voltages, as shown in Fig. 4-5. Like NMOS, Fig. 3-10 is the scheme of different STI recess thickness. The deeper FINs’ depletion region from sidewall enhanced more volume of the FIN, thus the inversion layer forms earlier than the device with less STI recess thickness. Therefore, the ”fully-depleted likely” mechanism decreased the threshold voltage and improve the subthreshold swing.
4.3.6 Device structure of 4-point Devices
To verify the fully-depleted effect, we measured other test structures, which have only one FIN but 4-point contacts, for body effect. The diagram of top view of the devices is shown in Fig. 3-12.
56
4.3.7 Threshold Voltage vs. Gate length on 4-point Devices
Similar to NMOS devices, the threshold voltages decreases as the gate length increases, due to the pocket implant, as shown in Fig. 4-7. Also, 30nm-STI-recess devices own smaller threshold voltage, due to the corner effect and the sidewall depletion region.
4.3.8 Threshold Voltage vs. Gate width on 4-point Devices
Fig. 4-8 shows the relation between the channel width and threshold voltage. Certainly, the threshold voltage of more recess devices is smaller. Otherwise, the threshold voltage increases as the channel width, due to the top-sidewall channel ratio. As shown in Fig. 3-14, the sidewall channel affects more at narrower width, so the threshold voltage is suppressed.
4.3.9 Body Effect on 4-point Devices
To verify that the depletion region of sidewall helps the inversion of channel, we measured the body effect. The threshold voltage shift is the difference of threshold voltage between |VSB|=0V and |VSB|=2V. According to the Eq.
The threshold voltage will increase with |VSB|. Fig. 4-9 shows the threshold shift-channel width curves. In deep-recess devices, the body voltage is blocked by the sidewall depletion region, so the threshold voltage shift is not much as shallow-recess devices. Similarly, the body voltage is blocked in the devices with narrower gate width.
4.4 Summary
57
The segmented p-MOSFET has similar properties to segmented n-MOSFET. The recess thickness of STI oxide improves some characteristics of the devices. The operation speed is improved by the recess because the subthreshold swing is improved. However, the doping profiles of the LDD and pocket implant don’t match well so we couldn’t compare the short channel effect. We also noted that the sidewall depletion region affects the threshold voltage by corner effect. After measuring the body effect, the body voltage is blocked, and is dependent to the recess thickness and FIN width. This phenomenon shows that the FIN structure may cause fully depleted characteristics, like the devices on SOI wafer.
58
W=30, L=27, N=20, STI recess=10 W=30, L=27, N=20, STI recess=15 W=30, L=27, N=20, STI recess=30
ID/(W/L) (A)
W=30, L=27, N=20, STI recess=10 W=30, L=50, N=20, STI recess=10 W=30, L=100, N=20, STI recess=10
ID/(W/L) (A)
|VG-VTH| (V)
Fig. 4-1 ID-VG curves of (a) different STI recess thickness (b) different gate length
59 (a)
0 5 10 15 20
1E-5
STI recess=10, W=30, L=32 STI recess=10, W=30, L=45 STI recess=10, W=30, L=55 STI recess=10, W=30, L=100
ID/(W/L) (A)
N
(b)
0 5 10 15 20
1E-5
STI recess=15, W=30, L=32 STI recess=15, W=30, L=45 STI recess=15, W=30, L=55 STI recess=15, W=30, L=100
ID/(W/L) (A)
N
(c)
0 5 10 15 20
1E-5
STI recess=30, W=30, L=32 STI recess=30, W=30, L=45 STI recess=30, W=30, L=55 STI recess=30, W=30, L=100
ID/(W/L) (A)
N
Fig. 4-2 on current vs. FIN number for (a)10nm (b)15nm (c)30nm STI oxide recess
60
STI recess=10, W=30, L=32 STI recess=10, W=30, L=45 STI recess=10, W=30, L=55 STI recess=10, W=30, L=100
VTH (V)
STI recess=15, W=30, L=32 STI recess=15, W=30, L=45 STI recess=15, W=30, L=55 STI recess=15, W=30, L=100
VTH (V)
STI recess=30, W=30, L=32 STI recess=30, W=30, L=45 STI recess=30, W=30, L=55 STI recess=30, W=30, L=100
VTH (V)
N
Fig. 4-3 threshold voltage vs. FIN number for (a)10nm (b)15nm (c)30nm STI oxide recess
61 (a)
10 100 1000
1E-5 STI recess = 10, W=10, N=20
STI recess = 15, W=10, N=20 STI recess = 30, W=10, N=20
Ion /(Wtop)/L (A)
L (nm)
(b)
10 100 1000
1E-5
STI recess = 10, W=10, N=20 STI recess = 15, W=10, N=20 STI recess = 30, W=10, N=20
Ion /(Wtotal)/L (A)
L (nm)
Fig. 4-4 on current vs. gate length which on current is normalized by (a) top gate width (b) total gate width
62
100 1000
0.2 0.3 0.4
0.5 STI recess=10, W=30, N=20
STI recess=15, W=30, N=20 STI recess=30, W=30, N=20
|VTH| (V)
L (nm)
Fig. 4-5 threshold voltage vs. gate length
63
100 1000
65 70 75 80 85 90 95 100
SS (mV/decade)
L (nm)
STI recess=10,W=30,N=20 STI recess=15,W=30,N=20 STI recess=30,W=30,N=20
Fig. 4-6 subthreshold swing vs. gate length
64
10 100 1000
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
W=500, STI recess=10 W=500, STI recess=15 W=500, STI recess=30
|V T H | (V )
L (nm)
Fig. 4-7 threshold voltage vs. gate length on 4-point FINFET
65
100 1000 10000
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
L=50, STI recess=10 L=50, STI recess=15 L=50, STI recess=30
|V T H |( V )
W (nm)
Fig. 4-8 threshold voltage vs. gate width on 4-point FINFET
66
100 1000 10000
0.0 0.1 0.2 0.3 0.4 0.5
L=50, STI recess=10 L=50, STI recess=15 L=50, STI recess=30
|V TH s h if t| (V )
W (nm)
Fig. 4-9 body effect between different gate width
67
Chapter 5
Conclusion and Future Work
5.1 Conclusions
In this thesis, for the chapter 2, we propose a non-overlapped implantation nonvolatile memory, without oxide-nitride-oxide gate stack. The trapped charges are stored in the HfSiOx nanocrystal under the nitride spacer. The device exhibits programming characteristics with channel-hot-electron injection. And the band-to-band-hot-hole injection provides about 0.8V threshold voltage shift during the erase operation. However, the erase saturation is caused by the electrons injected from gate electrode into the parasitic trapping layer or nitride spacer.
The threshold voltage almost has no drop at room temperature in the first 1000s during the retention measuring, but the migration of the trapped charges is the reason of the raising of the threshold voltage after 1000s. During the disturbance measuring, the threshold voltage is programmed higher after 100s disturbance stress. This device shows some nonvolatile memory characteristics, so the fabrication may be useful of NVM which is embedded with logic devices.
In chapter 3, we fabricated the segmented n-MOSFET with recess of shallow-trench-isolation oxide on silicon bulk. The recess reduces the threshold voltage and subthreshold swing by the sidewall depletion region and corner effect. However, the short channel effect is not observed due to the pocket implantation dose. Similar to the STI oxide recess, reducing of FIN width also decreases the threshold voltage. The body voltage is blocked at narrow FIN width or thicker STI oxide recess while measuring the body effect. So the FIN structures not only help some of the performance of the devices on SOI wafers, but also improve the performance on Si bulk wafers.
68
In chapter 4, the segmented p-MOSFET with the same fabrication process is discussed.
Most of the trend is the same as the segmented n-MOSFET, so this structure can be used in CMOS devices.
5.2 Future work
5.2.1 Future Work of Nonoverlapped Implantation Nonvolatile Memory
These NOI devices need to be improved in erase properties by better quality of tunneling and blocking oxide. How to make the thickness of tunneling oxide and blocking oxide impendent is important to improve the erase characteristics without sacrificing the programming and retention properties. The spacer size control and junction profile need to be research for two-bit operation and charge re-distribution. Moreover, the spacer material can be replaced by other kinds of high-k material to reduce the NOI channel resistance. Also, the relatively logic devices should be fabricated to study about the NVM devices embedded in logic devices with similar process.
5.2.2 Future Work of Segmented MOSFET
The pocket implantation needs to be controlled in a better profile so that we can compare the short channel effect between each condition. Also, we might want to design these devices in circuits for some applications in order to research the advanced applications in the future.
69
References
[1] D.Kahng and S. M. Sze, Bell Syst. Tech. J., 46, 1288 (1967).
[2] S. M. Sze, “Physics of Semiconductor Devices,” 2nd Edition, John Wiley and Sons, p504, 1983.
[3] Boaz Eitan, Paolo Pavan, Ilan Bloom, Efraim Aloni, Aviv Formmer, and David Finzi,
“NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Cell,” IEEE Electron Device Letters, Vol. 21, No. 11, November 2000.
[4] Jinkang Bu, and Marvin H. White, “Effects of Two-step High Temperature Deuterium Anneals on SONOS Nonvolatile Memory Devices,” IEEE Electron Device Letters, Vol. 22, No. 1, January 2001.
[5] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, T. H. Ng, and B. J. Cho, “High-κ HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation,”
IEDM Tech. Dig., 2004, pp. 889~892.
[6] W. J. Zhu, Tso-Ping Ma, Takashi Tamagawa, J. Kim, and Y. Di, “Current Transport in Metal/Hafnium Oxide/Silicon Structure,” IEEE Electron Device Letters, Vol. 23, No. 2, pp.
97~99, February 2002.
[7] G. D. Wilk, R. M. Wallace, J. M. Anthony, “High-κ gate dielectrics: Current status and materials properties considerations,” Applied Physics Review, Vol. 89, No. 10, pp. 5243~5275, May 2001.
[8] Y. H. Lin, C. H. Chien, C. H. Lin, C. Y. Chang, and T. F. Lei, “Novel Two-Bit HfO2 Nanocrystal Nonvolatile Flash Memory,” IEEE Trans. Electron Devices, Vol. 53, No. 4, pp.
782~789, April 2006.
[9] Yuan Taur, Douglas A. Buchanan, Wei Chen, David J. Frank, Khalid E. Ismail, Shih-hsien Lo, George A. Sai-halasz, Raman G. Viswanathan, Hsing-Jen C. Wann, Shalom J.
70
Wind and Hon-Sum Wong, “CMOS Scaling into the Nanometer Regime,” Proceeding of the IEEE, pp.486~504, 1997.
[10] International Technology Roadmap for Semiconductions(ITRS), 2007 edition.
[11] Y. K. Choi, K. Asano, N. Lindert, V. Subramanian, T. J. King, J. Bokor, and Chenming Hu, “Ultrathin-Body SOI MOSFET for Deep-Sub-Tenth Micron Era,” IEEE Electron Device Letters, vol. 21, pp. 254~255, 2000.
[12] B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R. A. Roy, O. Dokumaci, Z. Ren, F. F.
Jamin, L. Shi, W. Natzlem, H. J. Huang, J. Mezzapelle, A. Mocuta, S. Womack, M.
Gribelyuk, E. C. Jones, R. J. Miller, H-S P. Wong, and W. Haensch, “Extreme Scaling with Ultra-Thin Si Channel MOSFETs,” IEDM Tech. Dig., pp. 267~270, 2002.
[13] X. Huang, W. C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H.
Takeuchi, Y. K. Choi, K. Asano, V. Subramanian, T. J. King, J. Bokor, and Chemming Hu,
“Sub 50-nm FinFET: PMOS,” IEDM Tech. Dig., pp. 67~70, 1999.
[14] B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios and R. Chau, “High Performance Fully-Depleted Tri-Gate CMOS Transistors,” IEEE Electron Device Letters, vol.24, pp. 263~265, 2003.
[15] Jong-Tae Park, and Colinge, J.-P., “Multiple-gate SOI MOSFETs: device design guidelines,” IEEE Trans. Electron Devices, Vol. 49, No. 12, pp. 2222~2229, December 2002.
[16] K. H. Yeo, S. D. Suk, M. Li, Y. Y. Yeoh, K. H. Cho, K. H. Hong, S. Yun, M. S. Lee, N.
Cho, K. Lee, D. Hwang, B. Park, D. W. Kim, D. Park, and B. I. Ryu, “Gate-All-Around(GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires, ” IEDM Tech. Dig., 2006.
[17] W. Tsai, L. –A. Ragnarsson, L. Pantisano, P. J. Chen, B. Onsia, T. Schram, E. Cartier, A.
Kerber, E. Young, M. Caymax, S. De Gendt, and M. Heyns, “Performance comparison of sub 1 nm supptered TiN/HfO2 nMOS and pMOSFETs,” in IEDM Tech. Dig., pp. 311~314, 2003.
[18] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M.Brazier, M. Buehler,
71
A. Cappellani, R. Cham, C.-H. Choi, G. Ding, K. Fischer, I. Ghari, R. Grover, W. Han, D.
Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S.
Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Lin, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S.
Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, I. Reynolds, J.
Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Ihomas, I.
Inoeger, P. Vandervoom, S. Williams, and K. Zawadzki, “A 45nm Logic Technology with High-k + Metal Gate Transistors, Stained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100％ Pb-free Packaging,” IEDM Tech. Dig., pp. 247~250,2007.
[19] J. W. Yang and J. G. Fossum, “On the Feasibility of Nanoscale Tri-Gate CMOS Transistors,” IEEE Transactions on Electron Devices, Vol.52, pp. 1159~1164, 2005.
[20] Tahui Wang, Chun-Jung Tang, C.-W. Li, Chih Hsiung Lee, T.-F. Ou, Yao-Wen Chang, Wen-Jer Tsai, Tao-Cheng Lu, K.-C. Chen, and Chih-Yuan Lu, “A Novel Hot-Electron
[22] M. Fukuda, T. Nakanishi, and Y. Nara, “New nonvolatile memory with charge-trapping sidewall,” IEEE Electron Device Lett., vol. 24, no. 8, pp. 490~492, Jul. 2003.
[23] Erik S. Jeng, Chia-Sung Chiu, Chih-Hsueh Hon, Pai-Chun Kuo, Chen-Chia Fan, Chien-Sheng Hsieh, Hui-Chun Hsu, and Yuan-Feng Chen, “Performance Improvement and Scalability of Nonoverlapped Implantation nMOSFETs With Charge-Trapping Spacers as Nonvolatile Memories” IEEE Trans. Electron Devices, Vol. 54, No. 12, pp. 3299~3307, December 2007.
72
[24] T.-S. Park, E. Yoon, and J.-H. Lee, “A 40 nm body-tied FinFET (OMEGA MOSFET) using bulk Si wafer,” Physica E, vol. 19, no. 1, pp. 6–12, Jul. 2003.
[25] T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi, S. H.
Hong, S. J. Hyun, Y. G. Shin, J. N. Han, I. S. Park, U. I. Chung, J. T. Moon, E. Yoon, and J.
H. Lee, “Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers,” in VLSI Symp. Tech. Dig., 2003, pp. 135–136.
[26] T. Park, H. J. Choe, S. Y. Han, S.-M. Jung, B. Y. Nam, O. I. Kwon, J. N. Han, H. S.
Kang, M. C. Chae, G. S. Yeo, S. W. Lee, D. Y. Lee, D. Park, K. Kim, E. Yoon, and J. H. Lee,
“Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs),” in IEDM Tech. Dig., Dec. 2003, pp. 27–30.
[27] J.-H. Lee, T.-S. Park, E. Yoon, and Y. J. Park, “Simulation study of a new body-tied FinFETs (Omega MOSFETs) using bulk Si wafers,” in Proc. Si Nanoelectron. Tech. Dig., 2003, pp. 102–103.
73
個人簡歷(vita)
姓名：陳宣凱 性別：男
出生：民國72年7月30日 籍貫：台灣省台中市
住址：台中市華美街103巷8號5樓之1 學歷：國立交通大學電子工程學系 [ 90年9月 – 95年6月 ]
國立交通大學電子研究所碩士班 [ 95年9月 – 98年9月 ]
碩士論文題目：
矽基板上新穎結構的非揮發性記憶體與互補式金氧半場效電晶體的研究 Novel Structures of nonvolatile memory and CMOS on Bulk Silicon