Chapter 1 Introduction
1.2 Thesis Organization
In the Chapter 2 of the thesis, two typical layouts of the monolithic inductor and the fabrication parameters of commercial 0.18 um process are reviewed. In addition, the simplified lumped-element circuit model and the definition of inductor quality factor are shown and explained shortly. Finally, the loss mechanisms of the on-chip inductor in typical CMOS technology are analyzed.
In Chapter 3, the theoretical analysis of the proposed miniature inductor is shown.
From the viewpoints of the transmission line theory, the expressions of effective inductance and quality factor are derived and some design considerations are mentioned as well. Besides, the novel transmission line structure suited to monolithic integration, HS-CPS, is introduced. Lastly, the design flow of the proposed miniature inductors structure, which includes two different patterns, is illustrated.
In Chapter 4, the proposed miniature inductors with two patterns are designed and implemented in UMC 0.18 technology. The occupied area, Q-factor, and self-resonant frequency are compared with the symmetric spiral inductor. Moreover, the circuit application, a fully monolithic CMOS 5GHz VCO, is shown and the
inductor size, phase noise, and tuning range are displayed for the comparison with the single turn spiral inductor.
In the last chapter, a summary of the thesis is made and some future works about the proposed miniature inductor are provided simultaneously.
Chapter 2
Basic concepts of the monolithic spiral inductors
In this Chapter, some information of the commercial 0.18 um CMOS process used in this thesis is given in section 2.1. In addition, two typical layouts of monolithic inductors, asymmetric and symmetric patterns, are presented. They are very common in single-ended and differential excitation circuits, respectively. Section 2.2 summarizes the loss mechanisms of the on-chip inductors and section 2.3 analyzes the definition of the inductor quality factor.
2.1 Monolithic inductor
2.1.1 0.18 um CMOS Process
Fig. 2.1 the cross section of the 0.18 um CMOS process Active region
Si-Substrate
Field Oxide M1 M2 M3 M4
CTM
MIM capacitor
M5 M6
polysilicon
As depicted in Fig. 2.1, the 0.18 process provides six metal layers (M1-M6) for interconnect and one polysilicon layer for the gate oxide of MOS transistor. Each of the first five metal layer has a thickness about 0.5 um and the top metal layer (M6) is thicker ALCu metal (physical thickness: 2 um) in order to lower the sheet resistance and to enhance the quality factor of on-chip spiral inductor. The dielectric constant,εr
between the metal layers is about 4. The Metal-Insulator-Metal (MIM) formed by the special metal layer (CTM) between the M6 and M5 has the unit capacitance of about 1 fF/um2. Besides, the resistivity of the Si-substrate is about 10 Ω-cm.
2.1.2 Inductor Categories
Fig. 2.2(a) (b) shows the two typical layout of the on-chip spiral inductor. In Fig. 2.2(a), the asymmetric inductor layout is shown and it consists of a rectangular spiral metal track wound on the silicon substrate, using one or two of the available standard metal layers. If the routing angle larger than 45-degree is allowed in the corresponding process, octagonal or circular spiral can be used. Octagonal or circular has lower series resistance than the traditional rectangular spiral with the aid of more smooth shape. Consequently, the better quality factor of octagonal or circular inductor
Fig. 2.2 Typical asymmetric and symmetric inductor Asymmetric
(a)
Symmetric (b)
can be achieved. On the other hand, the symmetric inductor pattern is shown in Fig.2.2 (b). Without being wound as a continuous metal spiral, the structure of the symmetric coil is connected to the inner turn by the different metal level. The symmetric inductors provide not only the area-saved solutions to the differential circuits but the higher quality factor, while it is differentially-driven, as shown in Fig.
2.3.[4]. Furthermore, the symmetric-shape layout is useful for the balanced circuit applications to show better common-mode noise rejection.
2.2 Loss mechanism of the monolithic inductor
In order to ease the latch-up issue in circuit designs, the CMOS process has been a highly doped substrate. However, it leads to the more severe losses of monolithic inductors. The on-chip inductor losses can be categorized to two parts: conductor losses and substrate losses. The conductor losses contain the DC resistive losses and skin effect influence.
Fig.2.3 Quality factors of symmetric inductors for single-ended /differential excitation
Q
differentialQ
single-ended2 4 6 8
0 10
0 5 10
-5 15
Frequency (GHz)
Quality factor (Q)
Besides, the substrate losses include the substrate parasitic and eddy current effect. The following section will study these loss mechanisms related to the on-chip inductors.
2.2.1 Conductor Loss 2.2.1.1 DC resistive loss
The monolithic inductors are constructed by different layers of metal strip, typically aluminum. Even though the interconnect which is made of copper or gold is available, the finite conductivity of metal strip still causes resistive loss significantly.
The resistance of a uniform slab of metal strip can be expressed as
)
where ρ and t represent the resistivity and thickness of the metal strip. The area of the conductor is the same as the product of the conductor length (l) and width (w).
The expression may be denoted as
where Rsh is the sheet resistance having units of Ω/square. From (2.2), the lower metal strip resistance of the inductor can be achieved with the reduced sheet resistance. In modern CMOS process, different layer metals have individual sheet resistance.
Especially for RF application, the top metal layer is thicker in order to lower the sheet resistance and to enhance the on-chip inductor performance. For TSMC 0.18 um 1P6M standard process as example, the thickness of the sixth metal layer is 2um and that of other layers is 0.5um. Consequently, the sheet resistance of the top metal layer can be reduced to 0.018Ω but that of other layer metals is 0.078 Ω.
From (2.1), another way to shrink the resistive loss is to make the width of metal track wider. Though it is an easy way to reduce the resistance without the process limitations, the too wider track width introduces large parasitic capacitance to enlarge the capacitive coupling to lossy substrate and to degrade self-resonant frequency. In general, in RF applications, the optimal width is ranged from 10um to 20um.
Above all, it is still not possible to eliminate the resistive losses in standard process. Nevertheless, in case the wider and thicker metal track made of the high conductivity material like copper or gold is adopted, the issues of DC resistive losses can be alleviated.
2.2.1.2 Skin effect influence
At low frequencies, the series resistance of the inductor is dominated by the DC resistive losses. At high frequencies, the current in the metal track tends to shift to the surface of the conductor, resulting in a non-uniform current distribution. This phenomenon is called skin effect. Thus, the series resistance of the inductor is no longer determined by the DC metal track resistance. The parameter of evaluating the skin effect is the skin depth which is defined as
) 3 . 2 f (
πµ δ = ρ
where ρ is the resistivity of the metal strip, μ is the permeability of the metal material, and f is the operating frequency. The skin depth is also known as the figure of penetration since it describes the degree of the penetration by electric field and magnetic flux into the metal track at high frequency. The severity of the skin effect is judged by the ratio of the skin depth and the conductor thickness. Generally speaking, the skin effect is insignificant in case the skin depth is much larger than the conductor thickness.
2.2.2 Substrate losses
In this section, we will study the substrate losses, which include the substrate parasitic effects and the losses caused by eddy current.
2.2.2.1 The substrate of CMOS Process
The cross section of the two typical substrates is shown in Fig. 2.4. The substrates include the lightly doped (1~30 Ω-cm) substrate shown in Fig. 2.4(a) and heavily doped substrate (10-20 mΩ-cm) shown in Fig. 2.4(b). The lightly doped substrate consists of a lightly doped bulk (P-bulk) and a thin layer of oxide. However, the high impedance substrate may cause latch-up problem in digital circuits. Thus, the typical epi substrate is composed of a lightly doped epitaxial layer grown on a degenerately doped. It is very low impedance but lossy substrate
2.2.2.2 Substrate parasitic
A main drawback of CMOS process is the conductive substrate. It degrades the performance of an on-chip inductor by three different coupling. In this section, we will study these coupling mechanisms individually.
The first kind is the resistive coupling. For a doped semiconductor, the conductivity can be calculated as
(
n n p p)
(2.5)q µ µ
σ = • +
where q is the electric charge, n , p are the carrier concentration of the donor and acceptor, respectively. The μn and µprepresent the mobility of the n type and p type carriers respectively. Due to the finite conductivity of the substrate, the electric
Fig. 2.4 Two types of CMOS substrate (a) P-substrate (b) P-epi layer on top of P-substrate
field leaking to the substrate produces the potential drop. As the operating frequency increases, the undesired energy dissipation in the substrate becomes more severe.
Consequently, the loss reduction methodology like patterned ground shielding (PGS), as illustrated in Fig. 2.5, is proposed to block the electric field from entering silicon substrate.
The second type is the capacitive coupling. For an on-chip inductor, the substrate parasitic has resistive and capacitive effect. The substrate effects can be modeled by a three-element network comprised of Cox, Rsi, and Csi, as shown in Fig. 2.6. The typical length of the on-chip inductor can be several hundred micro-meters. Therefore, large parasitic capacitances which consist of the capacitance between adjacent strips and strips to substrate are introduced. The capacitance between inductor and substrate can be calculated as :
.
oxide
P- substrate P- substrate oxide
epi - layer
(a) (b)
Fig. 2.5 Patterned Ground Shield (PGS)
metal-poly
contact poly
Fig. 2.6 The substrate lumped circuit model
) 4 . 2 (
ox ox l w tox
C = • •ε
where єox and tox denote the effective dielectric constant and thickness of the oxide layer between the inductor and substrate. The l and w represent the length and width of the inductor. Apparently, the more turns the inductor is, the more significant capacitive parasitic effect will be. By virtue of the increased spacing to p substrate, using the higher level metal layer is effective to reduce the capacitance.
As far as the penetration of the electric field into the semiconductor is concerned, the capacitance of the substrate can be neglected at low frequency but the high frequency capacitive effect is compatible to the resistive effect in the bulk. Both of the capacitive effects create the equivalent parallel capacitor that resonates with the inductor. The LC combination represents the upper useful frequency limit of the inductor.
Cox
Cox
Cs Rs
Finally, the inductive coupling is also called “eddy currents”. That is, as the magnetic field penetrates into the conductive substrate, the opposite current will be introduced, as shown in Fig. 2.7. The induced current not only lowers the inductance but deteriorates the quality factor, especially at high frequency. It is noted that the magnetic coupling to the substrate can be neglected for lightly doped substrate since the substrate conductivity is typically low.
Fig. 2.7 Schematic representation of magnetically induced current
2.3 Definition of Inductor Quality factor ………..
The quality of an inductor is determined by its Q, quality factor. Several
Impressed device current
Induced eddy current
Magnetic field
the fundamental one is: 2 energylossinoneoscillationcycle
stored energy
Q = π •
However, (2.6) also defines the Q of an LC tank. In a sense, (2.6) provides the physical insight but does not specify what stores or dissipates the energy. The main distinction is based on the form of energy storage. As far as an inductor is concerned, the energy stored in the magnetic field is of interest. Any energy stored in the electric field, due to the unavoidable parasitic effects in an on-chip inductor, is counterproductive. Thus, the energy stored can be interpreted as the difference between peak magnetic energy and electric energy. In contrast, for a LC tank, the energy stored is equal to the sum of the average electric and magnetic energy.
Provided that an inductor is initially modeled as a simple parallel RLC circuit, it can be shown that [2]:
where R, L are the equivalent parallel resistance and inductance, respectively, and ω0 is the resonant frequency. Alternatively, the quality factor can be derived by the ratio of imaginary and real part of the input impedance. The expression is valid for two different excitations. If the inductor is single-ended driven, one terminal of the spiral inductor is excited by the ac source while the other terminal is connected to the common reference port (e.g. the supply voltage or ground). The corresponding input impedance is the impedance seen at one terminal as the other terminal is connected to the ground. On the other hand, for the differential-driven (i.e., voltages and currents at
two terminals are 1800 out of phase), the differential input impedance is the impedance seen between two terminals.
Moreover, Inductor quality factor is a frequency-dependent function and it is vital to introduce some indexes used in the thesis. An inductor is at self-resonance as the peak magnetic and electric energy is equal. Thus, the quality factor will vanish to zero at the self-resonant frequency (FSR), as shown in Fig. 2.8. Above the resonant frequency, no energy is available from an inductor to the external circuit. Besides, the frequency where the maximal quality factor (QMAX )is attained is called as fQMAX..
Fig. 2.8 The quality factor of monolithic inductor
3 6 9 12
0 15
-2 0 2 4 6 8
-4 10
freq, GHz
Q
0 Q
MAXf
Qmaxf
SRFrequency
CHAPTER 3
Theoretical analysis and structure of the miniature inductor
In this chapter, the proposed miniature inductors utilizing a high slow-wave-factor coplanar stripline (HS-CPS) are presented. The design flow of the proposed miniature inductors, which include the two patterns, shifted and folded inductors, is demonstrated. Some design equations and considerations are shown from the transmission line theory. They provide useful design guidelines to optimize the proposed inductor. Finally, the simulation results are shown and the effects of the metal shunting, the arrangement of the MIM capacitors, different phase constant, and folded structures are also studied.
3.1 Theoretical Analysis and Design Considerations
Fig. 3.1 shows the common single stub matching with a short circuit terminated transmission as the inductive element. The input impedance of a lossy line of length l can be expressed:
(3-1) The effective inductance and quality factor below the first resonant frequency is defined respectively by:
From (3-1), (3-2) and (3-3), we have
According to the transmission line theory, the propagation constant of a lossless transmission line is given as β =ω LC where L and C are the distributed inductance and capacitance per unit length along the transmission line. Eq. (3-4) shows that in case the βl product keeps constant, the shorter length of transmission line can be achieved with the larger value ofβ.
Fig. 3.1 Transmission line with short circuit terminal as the inductive element
Coplanar Stripline (CPS) is an attractive uniplanar transmission line for on-chip interconnects, as shown in Fig.3.2 (a), (b). As compared to the conventional
- L
Z L = 0 Z o , β
V (Z) , I (Z)
0 z
microstrip structure, CPS is insensitive to the properties of substrate and is simple implementation of open- or short- ended strips. Especially for standard CMOS process, its balanced structure is useful for the ease of substrate loss. Furthermore, HS-CPS is proposed to decrease the occupied area and total attenuation as compared to the conventional coplanar stripline [5]. The structure of HS-CPS is depicted in Fig.
3.2 (a), (c). With the aid of enhanced β in HS-CPS structure, the overall length of inductor can be shorter, as above elucidated.
According to (3-5), the Q factor can be optimized with the lower α and the appropriate βl product. Energy dissipation mainly arises from the lossy Si substrate and the resistivity due to non-ideal conductors. Not only the nature of differentially excitation, but the additional MIM capacitors alleviate the energy coupling to the substrate. That is to say, electric field is largely confined near the region of MIM capacitors. Only a fraction of electric field penetrates into the silicon. Thus, the issue of substrate loss is insignificant. As to the metal loss, the Metal 6 and Metal 5 are shunted to obtain the lower line resistance. On the other hand, from (3-5), it can be observed that the sinusoid function included in Q expression approaches the maximum as the product of lβ goes to 45o. It is favorable to optimize Q at a given frequency by tuning the lβ product up to 40o~45o.
3.2 Proposed Miniature Inductor Structure
The design flow of the proposed miniature inductors, which contains two patterns, is illustrated in Fig.3.3. Since the length of the proposed miniature inductor will be as long as several hundred micrometers, the inductors are folded to save the
(a)
(b)
CPS HS-CPS
Metal6 8 um
450 um
Dielectric (SiO2)
Si Substrate
2 um
CPS
Metal6
(c)
Fig. 3.2 Monolithic coplanar stripline (a) Top view of the conventional CPS and HS-CPS. Cross-sectional view of (b) the conventional CPS and (c) HS-CPS
occupied area. Thanks to the mutual coupling between two paralleled HS-CPS, the distributed inductance per unit length (L) and phase constant (β) are enhanced, and it leads to more length reduction.
The crossed pattern consists of the HS-CPS which is crossed and folded in the center as shown in Fig.3.3 (a)-(3), (4) respectively. Besides, the other inductor pattern is the shifted of Fig.3.3 (b).The conventional CPS is shifted and folded orderly as the depiction in Fig.3.3 (b)-(3), (4). As compared with the crossed pattern, the shifted can achieve the higher quality factor and self-resonant frequency due to the removal of the underpass between two metal layers.
Metal6
8 um
450 um
Dielectric (SiO
2)
Si Substrate
2 um
HS-CPS
Metal6
MIM capacitors
Fig. 3.3.Design flow of miniature inductor patterns
(1) (2)
(3) (4)
(a) Crossed
(1) (2)
(b) Shifted
(3) (4)
3.3 Inductor design
In this section, the simulation results of three inductor configurations, the symmetric spiral, the crossed miniature, and the shifted miniature inductors, are shown for comparisons. A commercially available, 2.5 D EM simulation software, ADS Momentum, is used to extract the S-parameters and corresponding electrical parameters in all the patterns.
3.3.1 Simulation results
In order to quantify the improvement in area reduction, two inductor patterns, the crossed and the shifted miniature inductor, (with nominal inductance 1nH) have been designed and implemented in UMC 0.18um CMOS technology. The total length of these inductors is expected to be shorter than 200 um (folded). Furthermore, the maximal quality factor is designed near 10 G-Hz to manifest the facility in Q tuning, as mentioned in section 3.1
From (3-4), the propagation constant β and the real part characteristic impedance R of the miniature inductor are derived as 1.8 (rad/mm) and 75 Ω for the required inductance (1nH) and βl product. The HS-CPS line consists of 8um-wide traces separated by 75um gap. Five MIM capacitors, each of 16 fF, are needed to be distributed in the CPS to meet the sufficient β. The total length of the miniature inductors is 172 um and the spacing between MIM capacitors, 64 um, can be decided by the quotient (2*172 /5). The design flow of the proposed miniature inductor is shown in Fig. 3.4.
Fig. 3.5 shows the layout of one spiral and two proposed miniature inductor. The
Fig. 3.4 The design flowchart of the proposed miniature inductor Start
Decide a configuration width
Choose a strip width
Zo= 75 Ω Add MIM capacitors
between CPS
Proper quality factor Q
Zo > 75 Remove a few
MIM capacitors
Zo < 75
END
Derive the required length for 1nH
Acceptable overall length
No
Yes
Q < needed
(a)
(b) Shifted miniature inductor 100 um
172 um
Spiral symmetric inductor 115um
172 um
(c)
Fig. 3.5 Layout of (a) the spiral symmetric inductor, (b) the crossed and (c) the shifted miniature inductor
sizes of the spiral inductor and miniature inductors are 172µm by 115µm and, 172µm
sizes of the spiral inductor and miniature inductors are 172µm by 115µm and, 172µm