Chapter 2 Basic concepts of the monolithic spiral
2.2 Loss mechanism of the monolithic inductor
2.2.2 Substrate losses
2.2.2.2 Substrate parasitic
A main drawback of CMOS process is the conductive substrate. It degrades the performance of an on-chip inductor by three different coupling. In this section, we will study these coupling mechanisms individually.
The first kind is the resistive coupling. For a doped semiconductor, the conductivity can be calculated as
(
n n p p)
(2.5)q µ µ
σ = • +
where q is the electric charge, n , p are the carrier concentration of the donor and acceptor, respectively. The μn and µprepresent the mobility of the n type and p type carriers respectively. Due to the finite conductivity of the substrate, the electric
Fig. 2.4 Two types of CMOS substrate (a) P-substrate (b) P-epi layer on top of P-substrate
field leaking to the substrate produces the potential drop. As the operating frequency increases, the undesired energy dissipation in the substrate becomes more severe.
Consequently, the loss reduction methodology like patterned ground shielding (PGS), as illustrated in Fig. 2.5, is proposed to block the electric field from entering silicon substrate.
The second type is the capacitive coupling. For an on-chip inductor, the substrate parasitic has resistive and capacitive effect. The substrate effects can be modeled by a three-element network comprised of Cox, Rsi, and Csi, as shown in Fig. 2.6. The typical length of the on-chip inductor can be several hundred micro-meters. Therefore, large parasitic capacitances which consist of the capacitance between adjacent strips and strips to substrate are introduced. The capacitance between inductor and substrate can be calculated as :
.
oxide
P- substrate P- substrate oxide
epi - layer
(a) (b)
Fig. 2.5 Patterned Ground Shield (PGS)
metal-poly
contact poly
Fig. 2.6 The substrate lumped circuit model
) 4 . 2 (
ox ox l w tox
C = • •ε
where єox and tox denote the effective dielectric constant and thickness of the oxide layer between the inductor and substrate. The l and w represent the length and width of the inductor. Apparently, the more turns the inductor is, the more significant capacitive parasitic effect will be. By virtue of the increased spacing to p substrate, using the higher level metal layer is effective to reduce the capacitance.
As far as the penetration of the electric field into the semiconductor is concerned, the capacitance of the substrate can be neglected at low frequency but the high frequency capacitive effect is compatible to the resistive effect in the bulk. Both of the capacitive effects create the equivalent parallel capacitor that resonates with the inductor. The LC combination represents the upper useful frequency limit of the inductor.
Cox
Cox
Cs Rs
Finally, the inductive coupling is also called “eddy currents”. That is, as the magnetic field penetrates into the conductive substrate, the opposite current will be introduced, as shown in Fig. 2.7. The induced current not only lowers the inductance but deteriorates the quality factor, especially at high frequency. It is noted that the magnetic coupling to the substrate can be neglected for lightly doped substrate since the substrate conductivity is typically low.
Fig. 2.7 Schematic representation of magnetically induced current
2.3 Definition of Inductor Quality factor ………..
The quality of an inductor is determined by its Q, quality factor. Several
Impressed device current
Induced eddy current
Magnetic field
the fundamental one is: 2 energylossinoneoscillationcycle
stored energy
Q = π •
However, (2.6) also defines the Q of an LC tank. In a sense, (2.6) provides the physical insight but does not specify what stores or dissipates the energy. The main distinction is based on the form of energy storage. As far as an inductor is concerned, the energy stored in the magnetic field is of interest. Any energy stored in the electric field, due to the unavoidable parasitic effects in an on-chip inductor, is counterproductive. Thus, the energy stored can be interpreted as the difference between peak magnetic energy and electric energy. In contrast, for a LC tank, the energy stored is equal to the sum of the average electric and magnetic energy.
Provided that an inductor is initially modeled as a simple parallel RLC circuit, it can be shown that [2]:
where R, L are the equivalent parallel resistance and inductance, respectively, and ω0 is the resonant frequency. Alternatively, the quality factor can be derived by the ratio of imaginary and real part of the input impedance. The expression is valid for two different excitations. If the inductor is single-ended driven, one terminal of the spiral inductor is excited by the ac source while the other terminal is connected to the common reference port (e.g. the supply voltage or ground). The corresponding input impedance is the impedance seen at one terminal as the other terminal is connected to the ground. On the other hand, for the differential-driven (i.e., voltages and currents at
two terminals are 1800 out of phase), the differential input impedance is the impedance seen between two terminals.
Moreover, Inductor quality factor is a frequency-dependent function and it is vital to introduce some indexes used in the thesis. An inductor is at self-resonance as the peak magnetic and electric energy is equal. Thus, the quality factor will vanish to zero at the self-resonant frequency (FSR), as shown in Fig. 2.8. Above the resonant frequency, no energy is available from an inductor to the external circuit. Besides, the frequency where the maximal quality factor (QMAX )is attained is called as fQMAX..
Fig. 2.8 The quality factor of monolithic inductor
3 6 9 12
0 15
-2 0 2 4 6 8
-4 10
freq, GHz
Q
0 Q
MAXf
Qmaxf
SRFrequency
CHAPTER 3
Theoretical analysis and structure of the miniature inductor
In this chapter, the proposed miniature inductors utilizing a high slow-wave-factor coplanar stripline (HS-CPS) are presented. The design flow of the proposed miniature inductors, which include the two patterns, shifted and folded inductors, is demonstrated. Some design equations and considerations are shown from the transmission line theory. They provide useful design guidelines to optimize the proposed inductor. Finally, the simulation results are shown and the effects of the metal shunting, the arrangement of the MIM capacitors, different phase constant, and folded structures are also studied.
3.1 Theoretical Analysis and Design Considerations
Fig. 3.1 shows the common single stub matching with a short circuit terminated transmission as the inductive element. The input impedance of a lossy line of length l can be expressed:
(3-1) The effective inductance and quality factor below the first resonant frequency is defined respectively by:
From (3-1), (3-2) and (3-3), we have
According to the transmission line theory, the propagation constant of a lossless transmission line is given as β =ω LC where L and C are the distributed inductance and capacitance per unit length along the transmission line. Eq. (3-4) shows that in case the βl product keeps constant, the shorter length of transmission line can be achieved with the larger value ofβ.
Fig. 3.1 Transmission line with short circuit terminal as the inductive element
Coplanar Stripline (CPS) is an attractive uniplanar transmission line for on-chip interconnects, as shown in Fig.3.2 (a), (b). As compared to the conventional
- L
Z L = 0 Z o , β
V (Z) , I (Z)
0 z
microstrip structure, CPS is insensitive to the properties of substrate and is simple implementation of open- or short- ended strips. Especially for standard CMOS process, its balanced structure is useful for the ease of substrate loss. Furthermore, HS-CPS is proposed to decrease the occupied area and total attenuation as compared to the conventional coplanar stripline [5]. The structure of HS-CPS is depicted in Fig.
3.2 (a), (c). With the aid of enhanced β in HS-CPS structure, the overall length of inductor can be shorter, as above elucidated.
According to (3-5), the Q factor can be optimized with the lower α and the appropriate βl product. Energy dissipation mainly arises from the lossy Si substrate and the resistivity due to non-ideal conductors. Not only the nature of differentially excitation, but the additional MIM capacitors alleviate the energy coupling to the substrate. That is to say, electric field is largely confined near the region of MIM capacitors. Only a fraction of electric field penetrates into the silicon. Thus, the issue of substrate loss is insignificant. As to the metal loss, the Metal 6 and Metal 5 are shunted to obtain the lower line resistance. On the other hand, from (3-5), it can be observed that the sinusoid function included in Q expression approaches the maximum as the product of lβ goes to 45o. It is favorable to optimize Q at a given frequency by tuning the lβ product up to 40o~45o.
3.2 Proposed Miniature Inductor Structure
The design flow of the proposed miniature inductors, which contains two patterns, is illustrated in Fig.3.3. Since the length of the proposed miniature inductor will be as long as several hundred micrometers, the inductors are folded to save the
(a)
(b)
CPS HS-CPS
Metal6 8 um
450 um
Dielectric (SiO2)
Si Substrate
2 um
CPS
Metal6
(c)
Fig. 3.2 Monolithic coplanar stripline (a) Top view of the conventional CPS and HS-CPS. Cross-sectional view of (b) the conventional CPS and (c) HS-CPS
occupied area. Thanks to the mutual coupling between two paralleled HS-CPS, the distributed inductance per unit length (L) and phase constant (β) are enhanced, and it leads to more length reduction.
The crossed pattern consists of the HS-CPS which is crossed and folded in the center as shown in Fig.3.3 (a)-(3), (4) respectively. Besides, the other inductor pattern is the shifted of Fig.3.3 (b).The conventional CPS is shifted and folded orderly as the depiction in Fig.3.3 (b)-(3), (4). As compared with the crossed pattern, the shifted can achieve the higher quality factor and self-resonant frequency due to the removal of the underpass between two metal layers.
Metal6
8 um
450 um
Dielectric (SiO
2)
Si Substrate
2 um
HS-CPS
Metal6
MIM capacitors
Fig. 3.3.Design flow of miniature inductor patterns
(1) (2)
(3) (4)
(a) Crossed
(1) (2)
(b) Shifted
(3) (4)
3.3 Inductor design
In this section, the simulation results of three inductor configurations, the symmetric spiral, the crossed miniature, and the shifted miniature inductors, are shown for comparisons. A commercially available, 2.5 D EM simulation software, ADS Momentum, is used to extract the S-parameters and corresponding electrical parameters in all the patterns.
3.3.1 Simulation results
In order to quantify the improvement in area reduction, two inductor patterns, the crossed and the shifted miniature inductor, (with nominal inductance 1nH) have been designed and implemented in UMC 0.18um CMOS technology. The total length of these inductors is expected to be shorter than 200 um (folded). Furthermore, the maximal quality factor is designed near 10 G-Hz to manifest the facility in Q tuning, as mentioned in section 3.1
From (3-4), the propagation constant β and the real part characteristic impedance R of the miniature inductor are derived as 1.8 (rad/mm) and 75 Ω for the required inductance (1nH) and βl product. The HS-CPS line consists of 8um-wide traces separated by 75um gap. Five MIM capacitors, each of 16 fF, are needed to be distributed in the CPS to meet the sufficient β. The total length of the miniature inductors is 172 um and the spacing between MIM capacitors, 64 um, can be decided by the quotient (2*172 /5). The design flow of the proposed miniature inductor is shown in Fig. 3.4.
Fig. 3.5 shows the layout of one spiral and two proposed miniature inductor. The
Fig. 3.4 The design flowchart of the proposed miniature inductor Start
Decide a configuration width
Choose a strip width
Zo= 75 Ω Add MIM capacitors
between CPS
Proper quality factor Q
Zo > 75 Remove a few
MIM capacitors
Zo < 75
END
Derive the required length for 1nH
Acceptable overall length
No
Yes
Q < needed
(a)
(b) Shifted miniature inductor 100 um
172 um
Spiral symmetric inductor 115um
172 um
(c)
Fig. 3.5 Layout of (a) the spiral symmetric inductor, (b) the crossed and (c) the shifted miniature inductor
sizes of the spiral inductor and miniature inductors are 172µm by 115µm and, 172µm by 100µm respectively. In the case for the conventional spiral inductor, the spacing(s) between conductors is 2 um, and the strip width is similarly chosen as 8 um for comparison. In this example, the miniature inductors uses only 87 % of the area to achieve the same inductance as the spiral inductor and the peak Q of the miniature inductor occurs approximately near 10GHz, as shown in Fig. 3.6. However, the miniature inductor decreases self-resonance frequency to 25.5 GHz with 18.6 % degradation of the quality factor, from 22.8 to 17.2.
Moreover, Fig. 3.7 displays the effective inductance and quality factor of the crossed and the shifted miniature inductors with the same area. The shifted miniature inductor increases the quality factor by 6 %, from 16.2 to 17.4, without any degradation of self-resonance frequency. Note that the improvement in Q benefits
100 um
Crossed miniature inductor
172 um
Fig. 3.6 Effective inductance (Leff) and quality factors (Q) of the spiral and the shifted miniature inductors
Fig. 3.7 Effective inductances (Leff) and quality factors of the crossed and shifted miniature inductors.
5 10 15 20 25
Table 3.1 Inductor Comparison
from the removed underpass of the shifted miniature inductor, as demonstrated previously. The performances of the symmetric spiral inductor and the miniature inductors are summarized and compared in Table 3.1.The reduction in Q is for the reason that the energy is saved in the MIM capacitors in the form of electric energy as the phase constant β is enlarged by the increased capacitance per unit length along the transmission line. The quality factor of an inductor is defined as [2]:
Namely, it will be counterproductive that any energy is stored in the inductor’s electric field.
Frequency >30GHz 25.5 GHz 26GHz Area (um2)
3.3.2 The effect of the metal layer shunting
As shown in equation (2.1) of section 2.2, the DC series resistance can be reduced by increasing the effective thickness of the metal strip. Shunting several metal layers is a simple solution in the commercial multilevel interconnects technology without any process modifications. However, shunting of metal layers will also reduce the oxide thickness between inductor and silicon substrate and the Cox, as shown in Fig.2.6, becomes larger. It degrades the quality factor at low frequency compared to a single-layer inductor built by using only the top metal. Therefore, the tradeoff between reducing the series resistance and minimizing the Cox should be concerned. In this thesis, the inductors of a single metal layer (M6), shunted M6/M5 layers, and shunted M6/M5/M4 layers are investigated (with nominal inductance 1nH).
The quality factor of the three cases is illustrated in Fig. 3.8. It is found that the maximal quality factor can be achieved for the M6/M5 coil compared to the M6 and M6/M5/M4 inductors, especially at our design frequency (10GHz), without any degradation of self-resonant frequency. Since the M6/M5 inductor has the lowest real part of the input impedance, as depicted in Fig.3.9, the shunting of M6/M5 is the optimal choice for our design. Besides, according to the maximal quality factor of three cases, layer shunting is beneficial at lower frequencies (i.e. lower than 10 GHz in this case) where coil losses dominate but are less advantageous at higher frequencies where substrate losses are significant. The observation is also consistent with the published early work [3].
5 10 15 20
Quality factor (Q) M6M5
M6M5M4
Quality factor (Q) M6M5
M6M5M4 M6 M6M5 M6M5M4 M6
Fig. 3.8 Quality factor comparison of shunting of three (M6/M5/M4), two (M6/M5), and the top metal layer (M6)
5 10 15 20
Fig. 3.9 Quality factor comparison of shunting of three (M6/M5/M4), two (M6/M5), and the top metal layer (M6)
3.3.3 The effect of the arrangement of MIM capacitors
In order to find out the effect of the arrangement of MIM capacitors, the performance of two miniature inductors containing eight 3.16x3.16um2 and two 6.32x6.32 um2 MIM capacitors respectively, as shown in Fig.3.10, are compared with the aforementioned miniature inductor including five 16x16um2 MIM capacitors. That is, the total inserted capacitance remains the same but the number of MIM capacitors is different. Fig.3.11 and Fig.3.12 show the simulation results of the effective inductance and quality factor of three miniature inductors individually. It is found that there is no significant difference between three miniature inductors. In other words, the arrangement of MIM capacitors does not matter.
172 um
100 um
8 um 6.32 um
(a)
172 um
100 um
8 um 3.16 um
(b)
Fig. 3.10 The miniature inductors of (a) two 6.32x6.32 um2
5 10 15 20
Leff (nH) 5 cell8 cell
2 cell
Leff (nH) 5 cell8 cell
2 cell
Quality factor 5 cell
8 cell
Quality factor 5 cell
8 cell
3.3.4 The performance of the inductor consists of different phase constant (β) HS-CPS
In order to evaluate the relationship between phase constant (β) and inductor parameters, two analyses are conducted.
First, this analysis is under the constraint that the inductor is made of constant characteristic impedance transmission line. The strip width of the HS-CPS can be reduced and the capacitance of MIM capacitors can be inserted for higher inductance and capacitance per unit length along the HS-CPS. Therefore, the higher phase constant (β) and shorter required length can be obtained. However, as the strip width shrinks, the series resistance of the HS-CPS would rise up leading to the degraded quality factor. That is, the trade-off between phase constant and series resistance should be made. Three HS-CPS structures of different strip width, 3μm, 8μm, and 13μm, as depicted in Fig.3.13, are investigated. Through the simulator, ADS momentum, MIM capacitors of different capacitance, 21.6fF, 16fF, and 13.1 fF are used in the three HS-CPS structures respectively to maintain the same characteristic impedance, 70 Ω at 10 GHz. Phase constant (β), quality factor of the inductors, and imaginary part of characteristic impedance, overall attenuation, i.e. the product of attenuation constant and inductor length, are given in Fig.3.14 and Fig. 3.15 (a), (b), (c). The corresponding phase constant at 10 GHz of HS-CPS of three strip width is 1.63, 1.38, and 1.14, respectively. According to equation (3.4), the inductors with effective inductance 1nH are designed and overall length of three configurations, 0.449 mm, 0.558 mm, and 0.643 mm, is required.
As shown in Fig.3.14 and 3.15(a), the highest phase constant is obtained by the HS-CPS of 3µm strip width with value about 1.63 but the quality factor is the lowest
13µm strip width has the least phase constant but the most superior quality factor.
According to (3.5), the imaginary part of characteristic impedance of the HS-CPS of 13µm strip width reaches the highest value with 0.858 and compensates the significant overall attenuation, as given in Fig. 3.15(b), (c), Although the HS-CPS of 8µm strip width shows the least overall attenuation, the imaginary part of characteristic impedance is not large enough to maximize the quality factor.
Second, the inductors are formed by the HS-CPS with different characteristic impedance and phase constant. Three HS-CPS structures of different MIM capacitors spacing, 32 μm, 64 μm, and 128 μm, depicted in Fig.3.16, are investigated. The strip width and spacing between strips is fixed at 8μm and 84 μm. The MIM capacitors are inserted for higher capacitance per unit length along the HS-CPS.
Therefore, the higher phase constant (β) and shorter required lengthcan be obtained.
Through the simulator, ADS momentum, the phase constant (β), real part of characteristic impedance, quality factor is given in Fig.3.17 and Fig. 3.18(a), (b). As shown in Fig.3.17 and Fig. 3.18(a), the corresponding phase constant of three HS-CPS configurations is 1.78, 1.31, and 1.14, respectively. According to equation (3.4), the inductors with effective inductance 1nH are designed and the required length is 0.497 mm, 0.558 mm, and 0.6 mm, separately. The highest phase constant is obtained by the HS-CPS of 32 µm MIM capacitors spacing with value about 1.78 but the real part of characteristic impedance is the lowest one due to the increased distributed capacitance. The quality factor of the HS-CPS of 1.14 phase constant reaches the highest value about 16.9, as shown in Fig. 3.18(b).
Above all, the trade-off between phase constant and quality factor (Q) should be made. By shrinking the strip width and inserting the MIM capacitors, the higher phase constant and size reduction will be available but the quality factor is degraded
simultaneously.
3.3.5 The influence of folded HS-CPS
In this section, the effect of the folded HS-CPS is studied. Two folded structures, crossed and shifted patterns, are proposed in this thesis and the crossed configuration is taken as an instance. Two HS-CPS structures, unfolded and folded, depicted in Fig.3.19 (a), (b), are analyzed. Both configurations have the same strip width, 8um,
In this section, the effect of the folded HS-CPS is studied. Two folded structures, crossed and shifted patterns, are proposed in this thesis and the crossed configuration is taken as an instance. Two HS-CPS structures, unfolded and folded, depicted in Fig.3.19 (a), (b), are analyzed. Both configurations have the same strip width, 8um,