Chapter 1 Introduction
1.3. Thesis Organization
The organization of this thesis is as follows:
In chapter 1, we introduce that difference clock domains are required in a SoC chip.
Using portable clock generator to replace conventional PLL is feasible.
In chapter 2, we give an overview of PLL related techniques for the proposed ADPLL.
The different PLL approaches are discussed.
In chapter 3, the proposed algorithm is introduced. A detailed description of the idea and simulation are given.
In chapter 4, we utilize the proposed ADPLL described in chapter 3. Detailed structures are then discussed.
In chapter 5, some concluding remarks will be derived from this research. Finally, we describe several design issues that needed to be further explored in the near future.
Chapter 2
Overview of Phase-Locked Loop
As shown in chapter 1, numerous applications, such as video graphics card, microprocessor and telecommunication system, require a clock synthesizer. Several methods exist for realizing frequency multiplication: phase locked loop (PLL), delay locked loop (DDL), and direct digital synthesis (DDS). Each of these methods has advantages and disadvantages for frequency multiplication. DLL approach may offer better jitter performance than PLL approach; but it is not suitable for wide multiplication range applications. The direct digital synthesis applied accumulator and D/A converter mechanism for frequency synthesis. Therefore, we only focus on the PLL approach in this work.
The organization of this chapter is as follows. Section 2.1 describes the basic concept of analog PLL. The architecture and algorithm of different digital PLL are discussed in section 2.2.
2.1. Basic Concept of PLL
A phase-locked loop (PLL) is combined with phase detector (PD), voltage controlled oscillator (VCO), and loop filter (LF). The basic block diagram is shown in Fig. 2.1, where PLL is a negative feedback control loop. The PLL's characteristics are determined by characteristics of PD, VCO and, LF. Its performances are taken careful of two kinds, one is the phase error, the difference between the input phase and output phase; and the other is the frequency range, what range over which it will acquire lock. As a result, PLL can be regarded as a tracking phase system.
Fig. 2.1 Basic block diagram of PLL
2.2. Digital Phase-Locked Loop
The all-digital phase-locked loop (ADPLL) has gained increased attention in recent years.
All analog building blocks are replaced with digital representations in all-digital PLL. Many different DPLL are discussed in literature. This section discusses some DPLL architectures as below: (1) ADPLL with fixed high-speed clock, (2) An adaptive gain control with full-custom DCO, (3) Standard cell-based ADPLL.
2.2.1. ADPLL with fixed High-speed Clock
It is assumed that a high-speed clock is used as reference timing, and all signals must be referred to this clock. Generally, the high-speed clock is faster than input at least 10 times to achieve better performance. The proposed algorithm [1] is illustrated in Fig. 2.2(a) and Fig.
2.2(b) for two conditions. Fig. 2.2(a) shows the case of DCO’s frequency (1/period) which is slower than input signals, i.e. T (DCO) > N (input). Fig. 2.2(b) shows the other case of DCO’s frequency which is faster than input signal, i.e. T (DCO) < N (input).
Fig. 2.2(a) Basic concept for estimating input’s phases and frequencies.
T (DCO) > N (input)
Fig. 2.2(b) Basic concept for estimating input’s phases and frequencies.
T (DCO) < N (input)
2.2.2. Adaptive Gain Control With Full-custom DCO
If the high-speed clock is available, such as in SoC, and the target operation’s speed is not very high, then DCO with fixed high-speed clock can be the choice. However, it may consume large power due to high-speed clock operation. So, an ADPLL [2] was proposed as a frequency synthesizer for microprocessor that did not require external fixed high-speed clock. The ADPLL has a 50 cycle phase lock, has a gain mechanism independent of process, voltage, and temperature.
It separated the frequency acquisition and phase acquisition. A high-resolution frequency comparator with matching delay line was utilized to enhance frequency accuracy. An anchor register is needed to store the baseline frequency. After frequency acquisition is completed, the ADPLL starts to trace the phase relation between reference clock and DCO clock. The phase tracking process was performed with a phase control algorithm and a phase detector.
After the frequency acquisition and phase acquisition, the ADPLL enters phase and frequency maintaining process. However, the cost of this chip area is extremely high due to DCO. Those DCO designs were required to be with full-custom layout. The full-custom DCO make it difficult for porting to difference process as design specification to be changed.
2.2.3. Standard Cell-based ADPLL
To improve performance and decrease costs of system integration, much more requirements and constraints must be taken into account in implementation. For advances and improvements of digital VLSI, all digital methodology has good abilities to satisfy above requirements of computer and communication applications in recent years. A major problem of traditional direct DCO synthesis method is the highly technology dependence. So, the portable design is an important issue in digital VLSI to improve system-on-chip (SOC) turnaround. The key issue is that all of the elements are designed form standard cell library without fully-custom layout. A high-resolution cell-based DCO is shown in Fig. 2.3, which includes two major parts. One is the inverter chain to perform coarse searches, and the other is the fine module. Hence, the operating range is determined by number of cascaded inverters, and the resolution is decided by scale of fine module. So, how to enhance the fine module accuracy is a big challenge of cell-based PLL design.
mux . . .
Fine module Coarse module
DCO clock
DCO controlled words
Fig. 2.3 The structure of cell-based digital controlled oscillator
Fig. 2.4 the binary search ADPLL controller
There are two common algorithms to realize the controller: one is binary search based ADPLL controller; the other is TDC-based fast-locking ADPLL controller. The ADPLL may have two DCOs for low output jitter associated with input reference. An average loop filter is necessary to filter out the rippling and produce smoother digital controlled word with less jumping.
The basic concept of binary search based ADPLL is a “Prune-and-Search” algorithm. Fig.
2.4 illustrates the frequency acquisition process. Whenever the frequency detector’s output changes from up to down or vice versa, the search step is divided by two. And after the search step reduces to one, the frequency acquisition is done. Then the ADPLL controller enters
phase acquisition and phase maintaining mode.
For fast-locking applications, lock-in time is the most critical design issue. Thus a time-to-digital converter (TDC) is used to quickly calculate the nearest control code for DCO to produce the desired frequency. TDC can convert the reference clock’s period information to multiples of delay cell’s delay time. Hence, ADPLL controller can use this information to quickly jump to the desired frequency band. And then ADPLL performs fine-turning to reduce the residual frequency error and phase error. As a result, the lock-in time can be reduced by adding TDC module. The basic structure of TDC is show in Fig. 2.5.
Counter
. . .
Latch & Encoder Latch Input signal
Integrator Output
Fig. 2.5 the structure of time-to-digital converter
However, the controlled code may have small variations due to the following factors:
Phase detector’s dead zone, DCO’s resolution. In phase acquisition process, Phase detector must provide correct phase relationship information about reference clock and divided output clock. The dead zone of phase detector will increase phase acquisition time and final phase error. To minimize the dead zone of Phase detector, several new phase detectors are proposed.
The key component is the digital pulse amplifier. Increasing the sensitivity of pulse amplifier will increase the sensitivity of phase detector and increase accuracy of controller.
Chapter 3
Phase Tracking and Frequency Search Algorithm
As discussion in chapter 2, most ADPLL lock-in process is separated in frequency acquisition and phase acquisition. By the TDC based or adaptive gain control algorithm, the PLL controller controls the internal oscillator’s output frequency to minimize frequency error.
After frequency acquisition is completed, the PLL turns into phase acquisition and phase maintaining mode. The lock-in time of PLL is mainly determined by the frequency acquisition time, thus how to reduce frequency acquisition time is very important to a fast-locking PLL design.
In this chapter, a new phase tracking based algorithm will be proposed. Most previous ADPLL algorithms are frequency searching based algorithms. They may not meet for some applications that depend on phase error. Actually, it can achieve the function of ADPLL either by frequency acquisition or by phase tracking. By the phase tracking algorithm, we only need to focus on how to minimize the phase error; and frequency maintain is done. We don’t need to divider our algorithm into phase acquisition and phase & frequency maintaining modes.
The proposed algorithm is flexible and very suitable for more applications.
The organization of this chapter is as follows. Section 3.1 describes the simple phase tracking process. Section 3.2 gives a new definition of phase tracking process. Section 3.3 explains the challenges of the phase tracking algorithm. The proposed algorithm is introduced in Section 3.4. Section 3.5 introduces the jitter model in this thesis. How to minimize the jitter is discussed in section 3.6. Section 3.7 gives the simulation result with verilog and matlab.
3.1. Basic Concept of Phase Tracking Algorithm
The basic concept of phase tracking algorithm is to minimize the phase error according to the information phase detector provide. The simplest way is very similar to the method in section 2.2.1 but no high speed reference clock. Fig. 3.1 illustrates the phase acquisition process of PLL. If we assume the frequency error between reference clock and divided output clock is very small after frequency acquisition, and the phase error between reference clock
and divided output clock is . And we assume at time = t0, t1 and so on, the phase detector finds that divided output clock lags behind reference clock. The PLL controller will control the internal oscillator to speed up. Without high speed clock, we don’t know the value of
Δ
Δ , so we modify the DCO controlled words with a constant value.
Fig. 3.1 The simple phase tracking process
Clearly, this method is passive and slow. So we think about the other way to speed up phase tracking with TDC aided. Fig. 3.2 illustrates the modified phase acquisition process of PLL for two conditions. Because we have more information about phase error, the value and the direction, we can tune the DCO controlled word with variable value.
Δ1 Δ2
T0 T1 T2
- - Lock
Case 1 : Tnew< T0
T = Tnew
T = T0 T = Tnew T = Tnew
Δ1 Δ2
T0 T1 T2
+ Lock
+
Case 2 : Tnew> T0
T = T0 T = Tnew T = Tnew T = Tnew
Fig. 3.2(a) When T new is smaller than T 0 Fig. 3.2(b) When T new is bigger than T 0
This modified method is similar a phase & frequency maintain algorithm. If we assume that there exists a phase lock before, we get phase error due to the change of reference clock or incorrect DCO frequency. As show in Fig. 3.2(a), when the cycle time of reference clock changes from T0 to T new, the phase detector finds that divided output clock lags behind reference clock, and the TDC tell us the value isΔ . So we subtract a corresponding value 1 ofΔ1from DCO controlled word and get new cycle time, T1.
1 0
1 T
-T = Δ (3-1)
After one reference clock cycle time, we get the phase errorΔ . Again, by subtracting the 2 DCO controlled word and getting a new DCO setting. The period time of new setting is T2.
2 1
2 T
-T = Δ (3-2)
Then we can calculate the correct cycle time of reference clock from equation (3-3), and set the corresponding setting into DCO controlled word.
Fig. 3.2(b) shows the other case of reference clock which is slow than divided output clock. From equation (3-4), we still get the phase & frequency lock at third cycle.
2
But this method is still like other phase & frequency algorithm, which need a phase lock before; that means we need to do the phase acquisition process. So the performance of phase error will be limited by how small phase error that phase acquisition process can achieve is.
3.2. The Definition of Phase Tracking and Frequency Search
In real situations, input information is very important for tracking or recovering desired signals correctly. In order to extract accurately and track immediately input information, it is necessary to estimate both phases and frequencies of input signals continuously. Obviously, the information from phase detector and TDC is still not enough to achieve minimum phase error; we need to find more information to reach the goal.
Fig. 3.4 illustrates the new definition of phase tracking & frequency search problem. The horizontal line means the cycle time of divided output clock or reference clock which is according to the scale of TDC. The vertical line represents the phase relation between divided
output clock and reference clock. The magnitude is according to the value of TDC, too. Fig.
3.4 illustrates the relation between phase error and frequency error. When initial phase error is zero and initial frequency error is zero, we denote this situation as (T target, 0), where T target
is the cycle time of reference clock. When initial phase error is zero and the cycle time of divided output clock is (T target -Δ1), we denote this situation as (T target - , 0). Fig. 3.4(a) shows that where the position at next cycle time while current phase error is zero and DCO controlled word is no change. When divided output clock is faster than reference at current cycle, like a: (T
Δ1
target -Δ , 0), next position will be at b: (T 1 target -Δ ,1 Δ ) if we don’t change the 1 controlled word. It is very easy to been proven from Fig. 3.3. When divided output clock is slower than reference at current cycle, like c: (T target +Δ , 0), next position will be at d: (T 2
target + ,- ) if we don’t change the controlled word. Because both horizontal and vertical line use the same scale, the oblique line will be .
Δ2 Δ2
45o
−
Fig. 3.3 the corresponding waveform at position a and b
One step of
Fig. 3.4(a) Initial phase error is zero
Fig. 3.4(b) illustrates the situation when the initial phase error is not zero. It also can be proven by drawing its corresponding waveform.
One step of TDC
One step of TDC Cycle time
Phase error
lead
lag
short long
Fig. 3.4(b) Initial phase error is not zero
Fig. 3.4(c) illustrates the general condition when the initial phase error is not zero and DCO controlled word applies new setting at current cycle. This also can be proven by drawing its corresponding waveform.
One step of TDC
One step of TDC
New setting
Cycle time
Old phase error
& cycle time
New phase error
& cycle time
Phase error
short long
Fig. 3.4(c) Initial phase error is not zero and DCO controlled word applies new setting
It often waste a lot of time to drawing the waveform to explain the phase tracking &
frequency search problem, and the waveform is usually hard to be understood. We transfer the phase tracking & frequency search problem into the other problem to deal with. The new problem we need to solve is shown in Fig. 3.5. The problem is how to reach the position of (T
target, 0) from any other position in Fig. 3.5. Obviously, the best solution is a straight line from starting point to our goal, as show in Fig. 3.5(a). Actually, that is very hard to achieve it. The greedy solution may be a whirlwind-like curve, as show in Fig. 3.5(b). To solve this problem is to solve the phase tracking & frequency search problem. The following sections all base on the new definition to discuss.
One step of
Fig. 3.5(a) The best solution Fig. 3.5(b) The greedy solution
3.3. Challenges of Phase Tracking and Frequency Search
As discussion in section 3.1, the modified phase & frequency maintaining algorithm only work in special condition. Fig. 3.6 illustrates the scenario. Fig. 3.6(a) is original waveform;
Fig. 3.6(b) is the corresponding diagram by definition. Reference clock changes form T0 to T
new at 0, and then we get a positive phase error, D, from TDC at 1. So we modify the controlled word and get a new phase error, A, at 2. Next cycle we get a phase lock at 3 and get frequency lock at 4. The corresponding value of position by definition is listed at the left of Fig. 3.6(b).
Fig. 3.6(a) Original waveform Fig. 3.6(b) The corresponding diagram
What happen if there is no “really” phase lock before maintaining algorithm? The term
“really” means how small the phase error is. This term will be limited by the dead zoon of phase detector. Fig. 3.7 shows the scenario in this situation. The path will be a close loop, and the magnitude of phase error and frequency error will be cyclic. It never achieves the “really”
phase & frequency lock. Actually, most phase & frequency maintaining algorithms which are discussed in chapter 2 have the same problems even though phase acquisition algorithm and frequency acquisition algorithm are aided. This problem is due to the regularity of tracking process.
D
Fig. 3.7 The scenario of phase tracking & frequency search
3.4. The Proposed Phase Tracking and Frequency Search Algorithm
The flow chart of proposed algorithm is shown in Fig.
3.8. Phase lock begins with frequency acquisition. In this mode an algorithm estimation and calculate the initial frequency. The algorithm also initiates and determines the parameters of coarse and fine tracking algorithm which execute after it. When frequency acquisition is complete, the ADPLL enters coarse tracking algorithm. This algorithm combines phase acquisition and frequency acquisition algorithms based on our definition. The pull-in range is from half to two times of reference clock cycle time. If the accuracy of TDC, which is compared with the accuracy of DCO, is not enough while the input jitter of reference clock is smaller than a single TDC cell, the ADPLL enters the fine tracking algorithm. The fine tracking algorithm also bases on our definition. This algorithm executes binary-search-like process. Its goal is to tune the DCO as accurate as it can. Moreover, there is a watching dog to detect whether the divided output clock is out of pull-in range or not.
Frequency and
3.4.1. Frequency and Phase Acquisition
The basic idea of frequency acquisition is shown in Fig. 3.9. The goal of this mode is
only for fast lock-in time. We just need a coarse initial frequency and phase before coarse algorithm. This mode only need two cycles of reference clock; the first cycle to estimate the minimum cycle time of divided output clock by TDC, and the second cycle to estimate the cycle time of last divided output clock by TDC and calculate the initial control word.
Fig. 3.9 The first cycle of frequency acquisition
Initially, DCO set the minimum cycle time after power on. The controlled word in DCO would be zero. After the first edge of reference clock comes, the controlled word will be added by a constant value, P, at every positive edge of divided output clock. How to determine P depends on the ration of the scales between TDC and DCO. Selecting the value which can be detected the difference in TDC while the multiplication factor sets the minimum value is recommend. After the second edge of reference clock comes, the controlled word will be held and TDC gets the corresponding value. If we assume the DCO is linear, which is shown in Fig. 3.10, we can write the equation (3-4) from the relation of
Initially, DCO set the minimum cycle time after power on. The controlled word in DCO would be zero. After the first edge of reference clock comes, the controlled word will be added by a constant value, P, at every positive edge of divided output clock. How to determine P depends on the ration of the scales between TDC and DCO. Selecting the value which can be detected the difference in TDC while the multiplication factor sets the minimum value is recommend. After the second edge of reference clock comes, the controlled word will be held and TDC gets the corresponding value. If we assume the DCO is linear, which is shown in Fig. 3.10, we can write the equation (3-4) from the relation of