The Proposed Phase Tracking and Frequency Search Algorithm

The flow chart of proposed algorithm is shown in Fig.

3.8. Phase lock begins with frequency acquisition. In this mode an algorithm estimation and calculate the initial frequency. The algorithm also initiates and determines the parameters of coarse and fine tracking algorithm which execute after it. When frequency acquisition is complete, the ADPLL enters coarse tracking algorithm. This algorithm combines phase acquisition and frequency acquisition algorithms based on our definition. The pull-in range is from half to two times of reference clock cycle time. If the accuracy of TDC, which is compared with the accuracy of DCO, is not enough while the input jitter of reference clock is smaller than a single TDC cell, the ADPLL enters the fine tracking algorithm. The fine tracking algorithm also bases on our definition. This algorithm executes binary-search-like process. Its goal is to tune the DCO as accurate as it can. Moreover, there is a watching dog to detect whether the divided output clock is out of pull-in range or not.

Frequency and

3.4.1. Frequency and Phase Acquisition

The basic idea of frequency acquisition is shown in Fig. 3.9. The goal of this mode is

only for fast lock-in time. We just need a coarse initial frequency and phase before coarse algorithm. This mode only need two cycles of reference clock; the first cycle to estimate the minimum cycle time of divided output clock by TDC, and the second cycle to estimate the cycle time of last divided output clock by TDC and calculate the initial control word.

Fig. 3.9 The first cycle of frequency acquisition

Initially, DCO set the minimum cycle time after power on. The controlled word in DCO would be zero. After the first edge of reference clock comes, the controlled word will be added by a constant value, P, at every positive edge of divided output clock. How to determine P depends on the ration of the scales between TDC and DCO. Selecting the value which can be detected the difference in TDC while the multiplication factor sets the minimum value is recommend. After the second edge of reference clock comes, the controlled word will be held and TDC gets the corresponding value. If we assume the DCO is linear, which is shown in Fig. 3.10, we can write the equation (3-4) from the relation of reference clock and divided output clock. In equation (3-4), k = t_m-t₀ / m, where t0 is the TDC value of intrinsic delay time in DCO; tm is the TDC value when control word is m; and X is corresponding controlled word value we want to calculate. We get the control word form equation (3-5) which rewrite from the equation (3-4).

k

When the calculation is complete, ADPLL will wait the coming of third positive edge and apply new controlled word, thus a rough phase and frequency acquisition is complete.

D

Fig. 3.10 The relation between Fig. 3.11 The basic steps of the proposed algorithm

TDC and DCO control word

3.4.2. Coarse Tracking Algorithm

Fig. 3.11 illustrates the basic steps of the proposed algorithm, and its corresponding waveform is shown in Fig. 3.12. There are four fundamental cycles. The initial cycle time of divided output clock is T1 at 1, and we get the phase error, D, between the first and the second cycles. Then we update the DCO setting with T1 + D to form the T2, and get phase error A at 2. Because we want to create a phase lock at 3 and we know the oblique line always is in Fig. 3.11, we can calculate where the position 3 is by the property of the isosceles triangle. Finally, we get frequency lock at 4 by the same method.

45o

−

Form the view of implementation in Fig. 3.12, it is impossible to set new setting into DCO controlled word at current divided output clock cycle time. But we can double the difference and apply the value while divided output clock is zero to form the cycle time we want. In order to sample the complexity of calculation, T3 will be T1 + 2A. Actually, in implementation, T1 and T3 can be been merged into a single cycle, and we can merge T2 and T4 into a single cycle, too. So the proposed algorithm achieves the phase lock and frequency lock within two rounds.

Fig. 3.12(a) First step Fig. 3.12(b) Second step

t1 + D

Fig. 3.12(c) Third step Fig. 3.12(d) Fourth step

Fig. 3.13 illustrates the other situation by the proposed algorithm. Clearly, the proposed algorithm is robust at any position.

A>D=0

D

Fig. 3.13 all situations by the proposed algorithm

3.4.3. Fine Tracking Algorithm

When the sensitivity of TDC is not enough to detect and the input jitter is very small, and we still have a little bits of DCO controlled word that TDC can not sense the difference between them, the ADPLL enters the fine tracking mode. The ADPLL add or subtract the controlled word with a gain register according to the direction which phase detector indicates.

The initial value of the gain register is the corresponding value of one step time of TDC. Fig.

3.14(a) illustrates the behavior when the reference clock within the gain windows which rate is 1.2 : 1 from two points. Clearly, the average phase error will shift up if the average cycle time is smaller than reference clock, otherwise the average phase error will shift down if the average cycle time is bigger than reference clock. In the shift up case in Fig. 3.14(a), the direction will not change after the long running, and the gain register can be reduced to the half. If the reference clock locates on the center of gain, as show in Fig. 3.14(b), the average phase error will never change; so, we subtract the gain register by one.

1.2:1

Gain register value

Gain register value be the half

Phase lock

Reference clock

1:1

Gain register value

Gain register value Subtract by

one

Reference clock

Fig. 3.14(a) Fig. 3.14(b)

In order to maintain the position always locate on the quadrant (-, +) or quadrant (+, -), we need to handle the situation when the position locates on the quadrant (+, +) or (-, - ). The simplest way is to wait the changing of direction. In order to prevent that the ADPLL wait too long, we use the offset register and round register to tune the gain register. The initial value of offset register and round register is one, and we give it a chance when the first event that the direction does not change occurs; but the gain register is reduced and the round register is subtracted by one. If the direction still does not change, the gain register is added by the offset register to speed up the locking process. In order to prevent the offset register grow too quick, we define a rule, the bigger the offset register is, the more chance it has. So every time the offset register grows up, the round register grows up, too. When the round register become to zero, the offset can be been added by one. The more detail of flow chart is shown in Fig. 3.15.

Fig. 3.15 the flow chart of fine tracking algorithm