This thesis is divided into four chapters. In Chapter 1, the background and motivation of poly-Si FinFETs technology are already given above. In Chapter 2, the process flow of FinFETs is described in detail. We monitored the DP process with in-line SEM analysis during the device fabrication. In Chapter 3, we present the electrical characteristics of the fabricated P-channel FinFETs. The characteristics of FinFETs with various channel dimensions and crystallization method are compared and discussed. Finally, in Chapter 4, we conclude the results and suggest the future work.
Chapter 2
Device Structure and Process Flow
2.1 Device Fabrication and Process Flow
The process steps of FinFET fabrication are described as follows, and the fabrication process for the proposed device is shown in Fig. 2-1. First, a 1000nm-thick wet oxide was grown on six-inch silicon wafers to serve as the buried oxide. Next, an a-Si layer was deposited by low-pressure chemical vapor deposition (LPCVD) at 550℃
(Fig. 2-1(a)), and the a-Si thickness was split into 50nm and 100nm. Then, the 50 nm-thick a-Si thin films and part of the 100 nm-thick ones were transformed into polycrystalline by excimer laser annealing (KrF, 480 mJ/cm2), and the remaining 100nm-thick a-Si thin film was transformed into polycrystalline by solid phase crystallization at 600℃ in N2 ambient for 24 hours (Fig. 2-1 (b)). Afterwards, the poly-Si thin film was defined by the A1 and A2 masks with the double patterning (DP) technique (Figs. 2-1 (c) to (e)) to form the active channel regions.
A TEOS-oxide layer was then deposited as gate oxide by LPCVD (Fig. 2-1 (f)), and the gate oxide thickness was either 10nm or 30nm. Subsequently, a 120nm-thick in-situ n+ poly-Si layer was deposited by LPCVD to serve as the gate electrode (Fig.
2-1 (g)). Afterwards, the gate electrode was defined by the G1 and G2 masks with another double patterning process (Figs. 2-1 (h) to (j)).
The first BF2+
ion implantation was used to dope the sidewalls of p+ source/drain for p-channel FinFETs with 10-nm thick gate oxide (at 30keV, 1×1014 cm-2, tilt angle
=60°) or 30-nm thick gate oxide (at 54keV, 1×1014 cm-2, tilt angle =60°), as shown in Fig. 2-1 (k). A 55nm-thick TEOS-oxide layer was deposited by LPCVD (Fig. 2-1 (l)), followed by a dry etching step to form the spacer (Fig. 2-1 (m)), whose width is about 38nm. Afterwards, the second self-aligned BF2 ion implantation was used to dope the topside of p+ source/drain with split of 10-nm thick gate oxide (at 25keV, 5×1015cm-2, tilt angle =0°) and split of 30-nm thick gate oxide (at 46keV, 5×1015 cm-2, tilt angle
=0°), respectively, as shown in Fig. 2-1 (n), followed by rapid thermal annealing (RTA) at 850℃ for 5 seconds. Finally, the passivation layer deposition, contact hole opening, metallization, and H2 sintering processes were done to complete the fabrication of FinFETs.
The split conditions of the fabricated FinFETs are summarized in Table 2-1.
Dimensions of both designed gate length (Lmask) and fin width (Wmask) with double patterning process are shown in Table 2-2.
2.2 Feasibility of Double Patterning Technique
As described in previous section that both the fins and gates were defined by the DP technique. We use an I-line stepper (Table 2-3) to generate photoresist (PR)
patterns, and employed an in-line scanning electron microscope (SEM) and transmission electron microscopy (TEM) to check the fabricated structures of the fins and gates. In Fig. 2-1 (c), the PR pattern generated by the A1 mask is used to preliminarily define the active channel region with the first etching process, and then the PR pattern generated by the A2 mask covers portion of the active channel region (e.g., the bottom half of the active region, as shown in the top view of Fig. 2-1 (d)).
After the second etching process, the overlapped region of A1 and A2 masks defines the final fin channel (Fig. 2-1 (e)).
Figures 2-2 (a) to (d) show the in-line SEM images of the etched poly-Si fins achieved with the DP method. These images obviously evidence that the DP can reliably shrink the poly-Si fin width down to sub-100 nm scale. The results and variations of fin widths are shown in Fig. 2-3 by measuring samples of different designed fin width (Wmask) taken from different locations of the Si wafers. These results confirm that the DP method is capable of not only generating fins with width down to 80 nm and good critical dimension (CD) control, but also providing good process uniformity.
We use another DP process to define the gated region. In Fig. 2-4 (a), the remained poly-Si in the right side is defined using the G1 mask. PR generated by the G2 mask subsequently covers the left side, as shown in Fig. 2-4 (b). In this figure we
can obviously see that a misalignment between the PR and underlying poly-Si occurs in the circled region. An enlarged view of this region is shown in Fig. 2-4 (c), from which we can see that the misalignment is around 84nm, much larger than the overlay spec. of the I-line stepper (Table 2-3). This indicates that the dimensions of the patterns on G1 and G2 masks may deviate from the designed values and lead to the observed misalignment. The aforementioned glitch is likely to be resulted during the manufacturing of the masks considering the fact that the etching of the patterns was done with manual wet processing. Fortunately this issue can be addressed by shifting the wafer stage of the stepper by -80nm along the horizontal direction in the figure during exposure to compensate for the misalignment. Results after implementing the measure are shown in Figs. 2-4 (d) to (e). Obviously the above method works well from the good alignment shown in the figures.
Figures 2-5 (a) to (d) show the in-line SEM images of the poly-Si gates of different dimensions patterned with the 2nd DP process. The variations of gate lengths taken from different locations of the Si wafers are shown in Fig. 2-6. Still, good controls over the gate CD down to 80 nm and uniformity are achievable.
In the gate DP process, we find that the widths of the fin channel beneath the gate electrode will affect the resulted gate lengths. Table 2-4 summarizes the measured gate lengths of the same designed gate length (Lmask) formed on fins of
different widths. The data were collected from structures located in the same die. It is seen that the measured gate length decreases as fin width increases. In-line SEM images of a set of samples with Lmask of 200 nm are shown in Fig. 2-7. This finding is postulated to be related to the different surface morphology of the PR spun on the gate lying over the channel of various widths. As shown in Fig. 2.8, the thickness of the PR gets thinner as the channel width is increased due the action of spinning. A thinner PR would lead to a finer pattern after exposure, as the finding shown above.
Fig. 2-9 shows the cross-section TEM graph of an ELA poly-Si channel, and the measured channel fin width (Wfin) and thickness (TSi) are 132nm and 94nm, respectively, which are smaller than the grain size of ELA poly-Si channel (0.3~0.5μm) [30]. With such a fine channel structure, it is expected that no or only one single grain boundary will be contained in the channel region as the channel length is scaled below half a micron regime. The fabricated devices would thus exhibit high performance but with a high fluctuation.
With in-line SEM and TEM analysis, we can confirm the capability of this novel lithography technique in the fabrication of sub-100 nm FinFET devices.
2.3 Electrical Measurement Setup
In this study, electrical characterizations of the fabricated devices were
performed by a measurement system which consists of an HP-4156A semiconductor parameter for I-V measurements, an Agilent-E5250A switch, and a temperature regulated hot-chuck for keeping the wafer temperature stable. Interactive Characterization Software (ICS) is used to set up all measurement conditions and extract the electrical parameters of the devices.
Chapter 3
Results and Discussion
3.1 Basic Electrical Characteristics of P-channel FinFETs
From the Id-Vg transfer curve measured at Vd = -0.5V, the characteristics of P-channel FinFET can be extracted as follows:
Threshold voltage (Vth) is defined by using the constant current method to be the gate voltage (Vg) needed to achieve the drain current (Id) of 50nA×(Weff/Lg): effective conduction width (Weff) of a channel is the sum of channel fin width (Wfin) and twice the channel thickness (2×TSi), as shown in Fig. 3-1.
Subthreshold swing (SS) can be extracted from the subthreshold current with the following form:
Figure 3-2 shows the characteristics of electrical measurements performed on a device with a narrow Wfin of 80 nm. The device has a steep SS (255mV/dec), a high Ion/Ioff current ratio (109), and low leakage current (<10-14A) owing to its narrow fin enabling a better gate control over the channel. Figure 3-2 (a) also shows good control
(DIBL).
Figure 3-3 shows the transfer characteristics of the fabricated devices with gate length of 0.2μm and various fin widths. Devices with narrow Wfin of 0.08 and 0.1μm
can achieve low SS. However, the Vth becomes more positive and the subthreshold current increases when the fin’s width increases to 0.2μm or wider. For these wider
dimensions, the “fin” channel actually becomes quasi-planar and thus the gate controllability is degraded [31]. As a result, a significant amount of sub-surface punch-through current would conduct and lead to a high subthreshold leakage.
Figure 3-4 and Fig. 3-5 show the transfer characteristics of the fabricated devices with gate length of 0.4μm and 1μm, respectively, and various Wfin. The leakage current of these long channel devices is much lower than that of the device with gate length of 0.2μm because of reduced SCE. In Fig. 3-4, the SS decreases as Wfin decreases because of better gate controllability. In Fig. 3-5, the leakage current increases as Wfin increases owing to the larger sub-surface leakage current.
Figure 3-6 shows the transfer characteristics of devices having the Wfin of 80 nm with various gate lengths (Lg). The devices with longer gate lengths of 0.2, 0.4, and 1μm have good Ion/Ioff current ratio of about 108 to 109. Nonetheless, the Ion/Ioff current ratio is smaller than 10 when the Lg is equal to or smaller than 0.1μm. Obviously here the short-channel effects are significant, implying dopant diffusion from S/D into the
channel occurs [32]. To improve the transfer characteristics of the short-channel devices, it requires a refined S/D annealing scheme with a tighter control over the thermal budget to suppress the undesirable dopant diffusion.
In Fig. 3-6, the SS of Lg of 0.4μm device is better than that of the Lg of 1μm device, which is in conflict with the trend of SCE. The following equation is the relation between the SS and the effective trap-state concentration (Ntrap) for poly-Si
TFTs: with Lg of 0.4μm. Therefore, the number of the grain boundaries could be small and even zero. This would reduce the trap-state concentration and result in better SS over the devices with Lg of 1μm. The Vth roll-off is shown in Fig. 3-7. Since the Vth roll-off
printed channel length. The other is the greatly enhanced gate controllability over the channel as the fin is scaled to nano-scale. In Fig. 3-7 the Vth roll-off is obvious because of SCE, and the SS is the worst in Fig. 3-8. From Fig. 3-9, we confirm that the devices with Lg of 0.2μm exhibit large DIBL, contrary to the devices with Lg ≧ 0.4μm whose DIBL is negligible. The results evidence that SCE dominates the trend
of SS as devices are downscaled to Lg of 0.2μm and beyond.
The dimension of Wfin of 0.08μm is much smaller than the ELA poly-Si grain size (0.3~0.5μm). As mentioned above, the SS of Wfin of 0.08μm devices at Lg of 0.4μm is much lower than the devices with Wfin of 0.4μm and 1μm in Fig. 3-8.
Meanwhile, in Fig. 3-7 and Fig. 3-8, the standard deviations of both Vth and SS characteristics increase as the Wfin decreases at the same Lg, and also increases as Lg decreases at the same Wfin. Although a decrease in Wfin tends to better device performance from the presented results, the uniformity of device characteristics suffers owing to the fluctuation in structural parameters like Wfin and the grain size of ELA poly-Si.
3.2 Device Characteristics of Various Channel Structure
Characteristics of devices with thin channel thickness (TSi) of 50nm are presented and discussed in this section. Figure 3-10 shows the transfer characteristics
of the devices with gate length of 1μm and various fin widths. The SS decreases as Wfin decreases because of better gate controllability. Most of trap centers located at or near the grain boundaries are charged positively as the surface potential of the channel becomes inverted, and the threshold voltage can be expressed as [33]
ox
reflects on the higher on-current shown in the figure.
The low aspect ratio (AR, equal to TSi/Wfin) of the channel at a fixed TSi leads to the poorer gate control over the channel potential [31]. This trend is obviously shown in Fig. 3-11, in which the transfer characteristics of the devices with gate length of 0.4μm and various fin widths are compared. As compare with the results shown in Fig.
3-4 (b) for devices with TSi of 100nm, the SS and subthreshold leakage increase at the same Wfin because the devices with low AR have worse gate controllability [31]. The trend is more obvious as Wfin ≧ 0.4μm.
Figure 3-12 shows the Vth of the devices with various Wfin as a function of Lg. As compared with Fig. 3-7, The Vth roll-off for devices from Lg of 1μm to Lg of 0.4μm is
obvious because of worsened gate controllability. Meanwhile, in Fig. 3-12, the drop in
Vth with decreasing channel length is more obvious for devices with Wfin of 0.4 and 1μm than that for devices with Wfin of 0.08 and 0.2μm. Figure 3-13 shows typical
transfer characteristics of devices measured at Vd = -0.5 and -1.5 V with gate length of 0.4μm and fin widths (Wfin) ranging from 0.08 to 1μm. From the figure, we can see
the devices with Wfin of 0.4μm and 1μm exhibit larger DIBL. This confirms that devices with wider Wfin suffer more serious SCE because of poorer gate controllability.
Figure 3-14 shows the SS for the devices with various Wfin as a function of Lg. The SS for devices with Lg of 0.4μm is better than that for devices with Lg of 1μm at Wfin of 0.08 and 0.2μm. From eq. 3-3, the grain boundary defects would predominantly affect the SS in these devices with a narrow Wfin. In contrast, for device at Wfin of 0.4 and 1μm, the SS for devices with Lg of 0.4μm is higher than that for devices with Lg of 1μm, which is different form that shown in Fig. 3-8 for devices with TSi of 100nm. From Fig. 3-13, the devices with wide Wfin of 0.4 and 1μm at low AR with TSi of 50nm have large DIBL. Fig. 3-14 evidences that SCE dominates the trend of SS in these devices with wide Wfin and low AR.
Figure 3-15 compares the electrical characteristics of two devices with the same effective fin width (Weff = Wfin + 2TSi) at gate length of 0.4μm. Wfin (TSi) for the two
devices are 100 (100) and 200 (50), respectively. The device with TSi of 100nm has steeper SS and lower subthreshold leakage than the device with TSi of 50nm due to improved gate controllability, but the on-current is lower than the device with TSi of 50nm. We further extract the field-effect mobility (μFE) of devices with different TSi, and the μFE is determined by
d ox eff
m g
FE W C V
G
L
(3-5),
where G is the maximum transconductance and m C is the gate capacitance per ox
unit area. As shown in Fig. 3-16, the μFE of the device with TSi of 50nm is larger than that of the device with TSi of 100nm. The reason is postulated to be related to the ELA condition [34]. Note that we used the same excimer laser energy (480mJ/cm2) to crystallize the a-Si films of different thickness. In the thicker TSi film of 100nm, the laser energy might cause only surface melting of the a-Si layer rather than the entire layer (i.e., melting depth < film thickness) [35], as schematically shown in Figs. 3-17 (a) to (c). This results in a smaller grain size and low quality of poly-Si film [36]. In the thinner TSi film of 50nm, the laser energy causes near-complete-melting of the thin film consisting of un-melted discrete silicon islands (i.e., melting depthfilm thickness) [37], as shown in Figs. 3-17 (d) to (f). Because the distance between the nucleation sites of silicon islands is long, the grain size of the poly-Si in this regime is
mobility and on-current for devices with TSi of 50nm are higher than those for the devices with TSi of 100nm.
Figure 3-18 extracts the source/drain series resistance (RSD) of these devices with different TSi by the total resistance method [38]:
channel SD
d d
m R R
I
R V (3-6),
where R is the measured resistance, and m Rchannel is the channel resistance. The RSD
for the devices with TSi of 100nm is about 21kΩ, which is larger than that for the devices with TSi of 50nm (~10kΩ). Note that the implantation and annealing process condition of devices with different TSi are the same as mentioned in last chapter. The reduction in RSD for devices with TSi of 50nm is another reason for the higher on-current and mobility as compared with devices with TSi of 100nm, and is attributed partly to the larger grain size of the 50 nm-thick channel.
Figure 3-19 shows the transfer characteristics of the devices with Weff of 0.3 and 0.6μm and at the same Lg of 0.4μm. The device with Weff of 0.3μm has better SS and
lower subthreshold leakage than the device with Weff of 0.6μm because of better gate controllability. The on-current of the device with Weff of 0.3μm is larger than that of the device with Weff of 0.6μm because the thinner TSi contains less defects.
3.3 FinFETs with Different Crystallization Method of SPC
and ELA
A comparison in the device characteristics between SPC and ELA devices is discussed in this section. Figure 3-20 shows the electrical characteristics of the fabricated devices which have Tsi = 100 nm, Wfin of 80nm, and Tox = 10 or 30 nm.
Because the grain size of SPC poly-Si is smaller than that of ELA [39], the SPC channel has more grain boundaries (GB) and thus more defects than the ELA channel.
As a result, the SS of SPC devices are worse than that of the ELA devices (refer to eq.
3-3), as shown in Fig. 3-20 (a). Also, the subthreshold leakage of SPC devices is higher than that of the ELA devices. In Fig. 3-20 (b), the SPC device has lower drive current than the ELA device with the same Tox of 10nm. The drive current of the ELA device with Tox of 30nm is the lowest because of the much thicker gate oxide. The field-effect mobility of the SPC device is lower than that of the ELA one, as shown in Fig. 3-21, obviously due to more grain boundary defects contained.
Figure 3-22 shows the Vth roll-off characteristics of SPC and ELA devices with Wfin of 80nm as a function of Lg. The Vth of SPC devices with Tox of 10nm, which is comparable to the Vth of ELA devices with Tox of 30nm, becomes more negative than that of the ELA devices with the same Tox of 10nm due to more poly-Si grain boundaries in the SPC channel (eq. 3-4). Nonetheless, the Vth roll-off is comparable for the SPC and ELA samples with same Tox of 10nm. As Tox increases to 30nm,
worse Vth roll-off is observed. Figure 3-23 shows the SS of SPC and ELA devices with Wfin of 80nm as a function of Lg. Since the Vth roll-off from Lg of 1μm to Lg of 0.4μm is not obvious in Fig. 3-22, the grain boundary defects would predominantly affect the SS in the devices with Wfin of 80nm (eq. 3-3). Obviously here the SS of SPC devices with Lg of 0.4μm is much poorer than those of the ELA devices with Lg
of 0.4μm, as shown in Fig. 3-23. As Lg is below 0.4 um, the SS obviously increases for all devices due to serious SCE.
However, the standard deviations of both Vth and SS of SPC devices are lower than those of the ELA devices with the same Wfin of 80nm, as shown in Fig. 3-22 and Fig. 3-23. This is ascribed to the tiny grain size of the SPC poly-Si which is less than
However, the standard deviations of both Vth and SS of SPC devices are lower than those of the ELA devices with the same Wfin of 80nm, as shown in Fig. 3-22 and Fig. 3-23. This is ascribed to the tiny grain size of the SPC poly-Si which is less than