Chapter 3 Results and Discussion
4.2 Suggestions for Future Work
In this work, we have successfully fabricated p-channel poly-Si FinFETs with a novel DP technique. However, some issues still exist, and directions for the future work are discussed as follows.
During the gate DP process, we find that a wider fin channel beneath the gate electrode would result in a shorter printed channel length. This phenomenon would further affect the SCE of the devices with wider fin channel. More efforts are needed to comprehend the root cause of this phenomenon.
The devices with longer gate lengths of 0.2, 0.4, and 1μm have good Ion/Ioff current ratio. However, the Ion/Ioff current ratio is smaller than 10 when the Lg is equal to or smaller than 0.1μm, implying dopant diffusion from S/D into the channel occurs.
It requires a refined S/D annealing scheme with a tighter control over the thermal budget to suppress the undesirable dopant diffusion.
As the fin width of ELA FinFETs is scaled down to sub-100 nm regime, the devices would thus exhibit high performance but with a high fluctuation of electrical characteristics. On the other hand, the SPC FinFETs with tiny grain size would reduce the fluctuation but the device performance suffers. As a result, the fluctuation in
structural parameters and the grain size of poly-Si should be optimized.
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Figures:
Fig. 1-1 2009 ITRS gate length trends of microprocessor unit (MPU) [2].
Fig. 1-2 The 3-D view of a TG FinFET structure [10].
(a)
(b)
(c)
(d)
Fig. 2-1 (a)-(n) Process flow of p-channel FinFETs with double patterning technique.
The left-hand-side figures are top views, and the right-hand-side figures are cross-sectional views.
(e)
(f)
(g)
(h)
Fig. 2-1 (a)-(n) Process flow of p-channel FinFETs with double patterning technique.
The left-hand-side figures are top views, and the right-hand-side figures are cross-sectional views.
(i)
(j)
(k)
Fig. 2-1 (a)-(n) Process flow of p-channel FinFETs with double patterning technique.
The left-hand-side figures are top views, and the right-hand-side figures are cross-sectional views.
(l)
(m)
(n)
Fig. 2-1 (a)-(n) Process flow of p-channel FinFETs with double patterning technique.
The left-hand-side figures are top views, and the right-hand-side figures are cross-sectional views.
(a) (b)
(c) (d) (e)
Fig. 2-2 (a) In-line SEM images of a fabricated device after definition of the poly-Si fin channel with a DP process. Enlarged views of measured (designed) dimension of patterned fins of (b) 86nm (80nm), (c) 103nm (100nm), (d) 208nm (200nm), and (e) 402nm (400nm).
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.00
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
Mean Value Wfin(m)
Wmask(m)
Fig. 2-3 Practical fin width (Wfin) extracted by in-line SEM versus the designed fin width (Wmask). The error bar is the standard deviation (1-σ) of the measured data.
(a) (b) (c)
(d) (e)
Fig. 2-4 In-line SEM images of fabricated gate structures. (a) After etching of poly-Si with photoresist (PR) patterns generated by G1 mask. (b) The PR pattern generated by the G2 mask and (c) an enlarged view of the circled region in (b) showing a
significant misalignment. (d) The PR pattern generated by the G2 mask after calibrating the wafer stage and (e) an enlarged view of the circled region in (d) showing negligible misalignment.
(a) (b)
(c) (d) (e)
Fig. 2-5 (a) In-line SEM images of a fabricated device after definition of the poly-Si gate with a DP process. Enlarged views of measured (designed) dimension of
patterned gates of (b) 70nm (80nm), (c) 93nm (100nm), (d) 196nm (200nm), and (e) 398 (400nm).
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.00
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
Mean Value
Lmask(m) Lgate(m)
Fig. 2-6 Practical gate length (Lgate) extracted by in-line SEM versus the designed gate length (Lmask). The error bar is the standard deviation (1-σ) of the measured data.
(a) (b)
(c) (d)
Fig. 2-7 Measured gate lengths (Lgate) of the gate with designed gate lengths (Lmask) of 200 nm varies with the widths of the fin channel (Wfin). (a) Wfin 80nm, Lgate 182nm, (b) Wfin 200nm, Lgate 180nm, (c) Wfin 400nm, Lgate 163nm, and (d)Wfin 1000nm, Lgate
149nm.
(a) (b)
(c) Fig. 2-8 Surface morphology of the PR spun on the gate lying over the channel of various widths. (a) An example showing the top view of the PR pattern generated with the G2 lithography process. The red line indicates the overlapped region of the PR patterns (left side) and the remained poly-Si defined by G1 mask (right side). (b) and (c) are the cross-sectional views of the surface morphology of red line in (a) with different channel widths. (c) The thicker channel width causes a thinner PR during the action of spinning.
Fig. 2-9 Cross-section TEM graphs of ELA poly-Si channel with designed Wmask = TSi
= 100nm. Practical fin widths (Wfin) and channel thickness (TSi) were measured to be 132nm and 94nm, respectively.
Fig. 3-1 The effective conduction width (Weff = Wfin + 2×TSi) of a channel. and gate length of 0.4μm.
Vg (V)
Fig. 3-3 Transfer characteristics of devices with gate length of 0.2μm and various fin widths (Wfin) ranging from 0.08 to 1μm, (a) un-normalized drain current , and (b) drain current normalized to the effective fin widths (Weff).
Vg (V)
Fig. 3-4 Transfer characteristics of devices with gate length of 0.4μm and various fin widths (Wfin) ranging from 0.08 to 1μm, (a) un-normalized drain current , and (b) drain current normalized to the effective fin widths (Weff).
Vg (V)
Fig. 3-5 Transfer characteristics of devices with gate length of 1μm and various fin widths (Wfin) ranging from 0.08 to 1μm, (a) un-normalized drain current , and (b) drain current normalized to the effective widths (Weff).
Vg(V)
Fig. 3-6 Transfer characteristics of devices with same fin width of 0.08μm and various gate lengths ranging from 1 to 0.08μm.
Fig. 3-7 Mean value and standard deviation of threshold voltage (Vth) as a function of the channel length for devices with various Wfin.
Lg (m)
Fig. 3-8 Mean value and standard deviation of subthreshold swing (SS) as a function of channel length for p-FinFETs.
Vg (V)
Fig. 3-9 Transfer characteristics for devices with channel lengths of 0.4 and 0.2μm.
Vg (V) various fin widths (Wfin) ranging from 0.08 to 1μm. The drain current is normalized to the effective fin widths (Weff). various fin widths (Wfin) ranging from 0.08 to 1μm. The drain current is normalized to the effective fin widths (Weff).
Lg (m)
Fig. 3-12 Mean value and standard deviation of threshold voltage (Vth) as a function of the channel length for devices with various Wfin.
Vg (V)
Fig. 3-13 Typical transfer characteristics of devices measured at Vd = -0.5 and -1.5 V with gate length of 0.4μm and fin widths (Wfin) ranging from 0.08 to 1μm.
Lg (m)
0.0 0.2 0.4 0.6 0.8 1.0 1.2
SS (mV/dec)
100 150 200 250 300 350 400 450 500 550 600 650 700
Wfin 0.08 m Wfin 0.2 m Wfin 0.4 m Wfin 1 m
TSi 50 nm, ELA, Tox 10 nm
Fig. 3-14 Mean value and standard deviation of subthreshold swing (SS) as a function of channel length.
Vg (V)
Vg (V)
-8 -7 -6 -5 -4 -3 -2 -1 0 1
cm2 / V-s)
0 10 20 30 40 50 60
TSi 100nm, Wfin 0.1m, Weff 0.3m TSi 50nm, Wfin 0.2m, Weff 0.3m
Lg 0.4 m Vd = -0.5V
Tox 10 nm, ELA poly-Si
Fig. 3-16 Mobility of the devices characterized in Fig. 3-15.
(a) (d)
(b) (e)
(c) (f)
Fig. 3-17 Re-crystallization schemes as the a-Si film is irradiated with excimer laser irradiation. (a)-(c) are partial-melting process occurring in a thicker film, and (d)-(f) are near-complete-melting process occurring in a thinner film.
Lg (m)
Vg (V)
-8 -7 -6 -5 -4 -3 -2 -1 0 1
Id (A/m)
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3
TSi 50nm, Wfin 0.2m, Weff 0.3m TSi 100nm, Wfin 0.4m, Weff 0.6m
Lg 0.4 m Vd = -0.5V
Tox 10 nm, ELA poly-Si
SS = 326mV/dec SS = 361mV/dec
Fig. 3-19 Transfer characteristics for devices with Weff of 0.3 and 0.6μm and Lg = 0.4μm.
Vg (V)
Vg (V)
Fig. 3-22 Mean value and standard deviation of threshold voltage (Vth) as a function of the channel length for the SPC and ELA devices with Wfin of 80nm.
Lg (m)
0.0 0.2 0.4 0.6 0.8 1.0 1.2
SS (mV/dec)
100 150 200 250 300 350 400 450 500 550 600 650 700
TSi 100nm, ELA, Tox 10nm TSi 100nm, ELA, Tox 30nm TSi 100nm, SPC, Tox 10nm
Wfin 0.08 m
Fig. 3-23 Mean value and standard deviation of subthreshold swing (SS) as a function of channel length for the SPC and ELA devices with Wfin of 80nm.
Tables:
Table 2-1 Split conditions of channel thickness (TSi) and oxide thickness (Tox) for ELA and SPC FinFETs.
Table 2-2 Dimensions of designed gate length (Lmask) and fin width (Wmask) with double patterning process.
Wmask
Table 2-3 Specifications of the Canon FPA-3000i5+ Stepper.
Resolution 0.35 micron (dense lines)
NA 0.63-0.45 (automatically variable)
Reticle Size 5-inch
Reduction Ration 5:1
Field Size 20 mm x 20 mm
Overlay Accuracy Mean + 3sigma ≦ 45 nm
Throughput 100 wph (200 mm)
Table 2-4 Measured gate lengths (Lgate) of various designed dimension on fin channel of various widths (Wfin). The data were measured from structures located in the same die with chan nel thickness of 100 nm.
Wfin (nm) 80 200 400 1000
Lgate (nm) of Lmask 80 nm 79 67 58 42
Lgate (nm) of Lmask 200 nm 182 180 163 149
Lgate (nm) of Lmask 400 nm 379 358 355 353
Vita
姓 名 ： 周 涵 宇 Han-Yu Chou
性 別 ：男
出 生 ：西元 1988 年 05 月 24 日
籍 貫 ：台灣 台北市
電子郵件：[email protected]
求學歷程：台北市立成功高中 2003/09～2006/06
國立交通大學 電子物理系 2006/09～2010/06
國立交通大學 電子研究所 2010/09～2012/09
論文題目：利用雙重微影成像法製作多晶矽鰭式場效電晶體元件之特性研究
A Study on the Device Characteristics of Polycrystalline Silicon
FinFETs Fabricated with Double Patterning Technique
Publication List
[1] H. Y. Chou, C. I Lin, H. C. Lin, and T. Y. Huang, “Fabrication of Poly-Si FinFETs with I-line Double Patterning Technique,” Symp. on Nano Device Technology (SNDT), ND-22, pp.38, 2012. (Excellence Award)
[2] H. Y. Chou, C. I Lin, H. C. Lin, and T. Y. Huang, “Fabrication of Poly-Si FinFETs with I-line Double Patterning Technique (利用I-line雙重微影成像法製作多晶矽 鰭式場效電晶體(FinFET)),” Nano Communication (奈米通訊), vol. 19, no. 2, pp.11-14, 2012.
[3] C. I Lin, H. Y. Chou, H. C. Lin, and T. Y. Huang, “Characteristics of P-Channel Polycrystalline Silicon FinFETs Fabricated with Double Patterning Technique,”
submitted to Int. Electron Devices and Materials Symp.(IEDMS), 2012.