Thesis Organization

Section 2 shows the overview of MIMO-SDPLL from hardware and software. Section 3 illustrates the proposed tracking algorithm. Section 4 is the implementation architecture includes software and hardware. Section 5 presents the simulation result of 2×2 MIMO-SDPLL and future work.

Chapter 2

Overview of MIMO-SDPLL

In this work, the proposed MIMO-SDPLL has feature of software controllability and programmability which integrates CPU with silicon IPs. These silicon IPs include PLL IPs.

Here MIMO-SDPLL is discussed from some parts.

2.1.

Base Concept

In section 1, there are three type of PLL. For SoC implement issue, all-digital approach is suitable and easier. So ADPLL is chosen as basic PLL IPs.

Fig.1 shows conventional ADPLL block diagram. Include phase frequency detector (PFD), time to digital converter (TDC), digital control oscillator (DCO) and frequency divider (Divider N). ADPLL can generate frequency-locked and phase-locked clock output when input reference clock. After power on, PFD detect frequency or phase error between reference clock and divided-by-N clock. TDC converter error pulse received from PFD into digital data.

If TDC output and DCO control tuning word (CTW) is equal then digital date sends to DCO directly. But in practical, digital data output from TDC often need digital processing to calculate CTW. The digital processing block is in Fig. 1. This block also process tracking algorithm or controlling strategy. DCO generate corresponding DCO clock with calculated CTW. In equation (1) shows this relation.

f ( )

DCO =

f CTW (1)

Notice that function f usually not linear. Divider N divide DCO clock by N and output divided clock send back to PFD, equation (2) show this relation.

− − = ^DCO

divided by N

f f

N (2) ADPLL repeat the above actions until frequency-locked and phase-locked.

However, digital processing is hardware implement. This is not flexible for change transformation of CTW, tracking algorithm or controlling strategy. Designer can only change some function by reserved input wires. For example, if users need change control strategy for different application, they can only depend on original hardware function to generate input data bit-by-bit manually. This is time-consuming and hard work. Thus use CPU to replace digital processing is proposed. CPU is more flexible and powerful than original digital processing.

Fig.1. Basic block diagram of ADPLL

2.2. Silicon IP Selection

2.2.1. CPU

In section 2.1 digital processing is replaced with CPU. The selection of CPU is free, open sourced OpenRISC OR1200 CPU released by OpenCores [4] [5]. OpenRISC project is to create a free, open source computing platform available under the GNU (L) GPL license.

The OR1200 is a 32bit scalar RISC with Harvard micro architecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities. Fig 2 shows architecture of OR1200. At UMC 90nm process, OR1200 is about 10k ASIC gates. The reasons for choosing OR1200 are open source and have been implemented in various commercial ASICs and FPGA.

Fig.2. OpenRISC OR1200 overview

2.2.2. BUS

In order to integrate CPU and silicon IPs, this work select OR1200 compatible WISHBONE [8] bus as bus architecture. WISHBONE is a specification maintain by OpenCores. Its purpose is to foster design reuse by alleviating system-on-a-chip integration problems. This is accomplished by creating a common, logical interface between IP cores.

This improves the portability and reliability of the system, and results in faster time-to-market for the end user. The proposed MIMO-SDPLL platform use WISHBONE to connect all IP cores.

2.2.3. PLL

In order to integrate PLL with CPU and IP cores. ADPLL need be partitioned into

different IP cores. The partition step is simple; divider digital processing input part and output part into two IP cores. In fig.1 PFD, TDC and Divider-N generate digital data to digital processing; this is input part and combine to error detector IP core. And output part is DCO independently. Notice that new IP cores need bus interface in order to connect to WISHBONE bus.

2.3. Software

The proposed MIMO-SDPLL control IP cores with software. In common, software can be developed with almost high level languages if there are corresponding compilers. In this work choose C as development language because C is one of the most popular programming languages. It is widely used on many different software platforms, include OpenRISC. And OpenRISC has provided C compiler for OR1200; this is familiar and convenience for programmer to develop software. In fig.3 exhibit software flow of MIMO-SDPLL, it is common and used for a long while.

Fig.3. Software flow of MIMO-SDPLL

2.4. MIMO-SDPLL

In section 2.2 introduce some major IP cores of MIMO- SDPLL. In fig.4, CPU, error

detector, DCO and other IP cores are connected by WISHBONE bus. Flash memory stores the program of tracking algorithm and controlling strategy. Semi asynchronous clock access (SACA) provide system clock of MIMO-SDPLL. It is synchronous rising edge of reference clock and maintains high after count the number user-defined. This can provide enough clock cycle for CPU computing and reach low power and low noise.

Fig.4. MIMO-SDPLL architecture

The working flow of MIMO-SDPLL:

1. After reset, CPU executes instructions and initials all IP cores.

2. CPU start polling error detector 1 ~ N.

3. If one of error detectors detects error, then CPU fetch this value.

4. CPU calculates CTW and sends to correspondence DCO.

5. Return to step 2.

The proposed MIMO-SDPLL can handle N number of error detectors and DCOs, the

number N decide by calculation power of CPU. Further more, all DCO clocks are frequency-locked and phase-locked.

2.5. Architecture Simulator and IP Model

MIMO-SDPLL use software to execute tracking algorithm and controlling strategy. In order to increase software development efficiency and convenience, architecture simulator and system model are used frequently.

2.5.1. Architecture simulator

OpenRISC project provide an architecture simulator OR1ksim. It is a generic architecture simulator capable of emulating OpenRISC based computer systems. Or1ksim has several unique features:

z Free, open source code.

z High level, fast, architecture simulation that allows early code analysis and system performance evaluation.

z Easy addition of new peripheral models.

Or1ksim can execute C program instruction by instruction. This is helpful for debugging.

For MIMO-SDPLL simulation, PLL IP Models can add to Or1ksim.

2.5.2. PLL IP Model

As mentioned at section 2.2.3, there are two IP cores divide from ADPLL, error detector and DCO. For simulation at architecture simulator, these two IP cores are modelled. First, error detector has two inputs and one output. They are input reference clock and input divided clock with frequencyf and_ref f . Output is phase error_div ε_out. In order to model clock, record clock frequency and phase offset is reasonable. The clock modelD can represent as _ref

( , _ )

ref = ref ref offset

D T t

=1/

ref ref

T f

_ =( + _ ) mod

ref offset sys ref init ref

t t t T . (3) AndD is _div

( , _ )

div = div div offset

D T t

T is clock period , t is current system time,_sys t_init is initial time of rising edge and

offset

t represent offset time at t . Phase error is phase difference detected at_sys t ,_sys ε_outcan derive as

_ _

ε_out =t_{div offset}−t_{ref offset} (5)

If D phase lead_div D then_ref ε_out is positive else ε_out is negative. DCO model is similar to error detector. Input CTWd is digital data can use directly. Output DCO clock _ctw D also _dco record clock frequency and phase offset, T define as _dco

= + ⋅

dco intr DCO ctw

T T k d (6)

T is intrinsic period of DCO. intr k_DCOis DCO gain defined as a frequency deviation in response to 1 LSB of the inputd . And_ctw t_{dco offset_} become dco offset dco init sys

dco dco

t and ′T is previous phase offset and clock period. _dco t_{dco init_} is initial phase offset of DCO.

Ideally, whenT_ref =T and 0_div ε_out = is frequency-locked and phase-locked.

Chapter 3

Tracking Algorithm

In PLL domain, high resolution and fast-locking time are important performance factor of tracking algorithm. The target of tracking algorithm is frequency-locked and phase-locked.

It can be separated into three parts, frequency search, phase tracking and phase maintaining.

At this section will discuss in detail from these parts.

As motioned at section 2, the proposed MIMO-SDPLL uses software to design tracking algorithm. The performance gap between software and hardware is a big design challenge.

And the control strategy is complex when many IP cores active at the same time. These issues also will be discussed at this section and a tracking algorithm for MIMO-SDPLL will be proposed.

The organization of this section is as follow. Section 3.1 introduce common concept of frequency search. Section 3.2 shows the concepts of phase tracking. Section 3.3 analyses the tracking problem and introduces a new expression of waveform. Section 3.4 proposes a tracking algorithm can reach frequency-locked, phase-locked and phase maintained.

3.1. Basic Concept of Frequency Search

In tracking algorithm, accurate frequency is essential for phase tracking. If frequency error between reference clock and divided clock is big, then phase error will change at every clock cycle. This let phase acquisition more complex. There are two common frequency search algorithms have been used. One is binary search based and another is TDC-based.

The basic concept of binary search based algorithm is “Prune-and-Search”. DCO search target frequency and divide half of search range at each step. After the search range reduces to

one, the frequency search is done. Then algorithm enters phase tracking and phase maintaining state. Fig.3.1 shows the concept.

Fig.3.1. Binary search concept

However, for fast-locking application, lock-in time is critical design issue. Thus TDC-based algorithm is proposed. It needs TDC converts timing information into digital data.

This is helpful for quickly calculation of the nearest CTW for DCO. With this idea, reference clock period information can be measured by TDC. And DCO quickly jump to the desired frequency as same as reference clock. Obviously, the lock-in time can be reduced. Fig.3.2 is basic structure of TDC. The internal delay chain measure input signal. And counter add one when input signal traverse the delay chain. TDC-based approach is chosen at this work.

Fig.3.2 The structure of time-to-digital converter (TDC)

3.2. Basic Concept of Phase Tracking

The basic concept of phase tracking algorithm is to minimize the phase error provided by phase detector. The simplest way is add constat control word after frequency search. Assume divider clock frequency is close enough to reference clock after frequency search. DCO control word will add (subtract) constant if phase is lag (lead). In fig.3.3 shows this process.

Initial phase error is Δ1, and phase detector report divided clock’s phase is lag. Because phase error Δ1 is unknown, control word subtracts a constant ε to reduce phase error. The Δ2, Δ3 and Δ4 are in similar process. Δ4 adds ε because phase is changed from lag to lead. Obviously, this method is slow and passive.

1

Fig.3.3 The simple phase tracking algorithm

In section 3.1, the TDC-based frequency search algorithm use TDC to speed up

frequency search. As the same idea, phase error can be measured by TDC. With this information, the control word can be calculated accurate. In fig.3.4, assume the same condition of fig.3.3. The divided clock period is as same as reference clock period, denoted as T. Because of frequency is locked, Δ2 equal to Δ1. So T′ can be inserted to fix phase error Δ1. From the derivation of these conditions, phase error becomes zero at Δ3.

initial error Δ1

Fig.3.4. TDC-based phase tracking algorithm

However, the two algorithms above, assuming perfect frequency locked which mentioned at section 3.1. In practical, frequency can’t lock perfectly because of the PFD’s dead zone, TDC’s resolution and DCO’s non-linear. To conquer these restrictions, a new tracking algorithm is proposed.

3.3. The Challenge of Tracking Algorithm

The algorithm of frequency search and phase tracking are discussed at section 3.1 and 3.2. However, phase tracking algorithm is affected by frequency search result considerably.

The information of frequency and phase need consider together. So the tracking problem requires be rechecked at this section.

Before describing the challenge of tracking algorithm, a more powerful expression of waveform is introduced. This expression is proposed at [6]. Fig.3.5 illustrates the new definition of phase tracking & frequency search problem. The horizontal line means the cycle

time of divided output clock or reference clock which is according to the scale of TDC.

TDCmin is TDC minium detectable range. The vertical line represents the phase relation between divided output clock and reference clock. The magnitude is according to the value of TDC, too.

Fig.3.5. Define of waveform expression.

The upper is original waveform and the bottom is anther expression.

For example of fig.3.5, the divided clock is lag Δ1 to reference clock at t0 initially. And divided clock period is longer than reference clock with valueε. So this relationship can be represented as (Tref +ε, -Δ1). The t0 point is located at the quadrant of longer cycle and lag phase. As the same process, t and t can be marked. And t and t shift down frequency error ε

at each cycle. In another case, if the divided clock is shorter than reference clock, the location of new points will be symmetric at Tref. But the direction is opposite to original. Summary, the right-hand side of Tref always shift down and left-hand side shift up. From this new definition, the tracking problem can be explained without drawing complex waveform which is hard to be understood.

In the example of fig.3.5, the DCO control word has not changed. Fig.3.6 shows the situation when setting new DCO control word.

Fig.3.6. Setting new DCO control word.

The tracking problem now can be transferred into another question. How to reach (Tref, 0) at any point of fig.3.6 is new target of algorithm. The straight way is setting new control word to DCO if there is phase error. But the frequency error between divided clock and reference clock let this manner become non-convergence. In fig.3.7, the path of algorithm will be a close loop, and the magnitude of phase error and frequency error will be cyclic. The proposed algorithm will resolve this problem and reach frequency-lock and phase-lock.

0

Fig.3.7. The close loop of tracking problem

3.4. The Proposed Tracking Algorithm

In this section, a new tracking algorithm is proposed. The basic idea comes from [2], and does some modification for MIMO-SDPLL. The algorithm flow is in fig.3.8. It is separated into three main part, frequency search, coarse tracking and fine tracking. Initially, algorithm start at frequency search state to get reference clock period. Second, if watch dog not bark then algorithm enters phase tracking state. The phase tracking has two parts, one is coarse and another is fine. This is decided by the resolution of PFD, TDC and DCO. Because DCO have extra control bit when TDC reach minimum detectable range TDCmin. More accurate tracking can do by these control bit and PFD signal. Phase tracking algorithm does coarse tracking continually, if phase error is bigger than TDCmin. Else algorithm will enter fine tracking state.

Notably, all states of proposed algorithm need tuning frequency and phase, this will explain later.

Fig.3.8 The algorithm flow

3.4.1. TDC and DCO relation mapping

Usually, TDC and DCO relation is known after IP selection. However, this relation will have some variation with PVT issue. Thus the training of this relation is required. Before start tracking algorithm, DCO clock connect to the input of TDC and software set different known control word to DCO. After DCO clock changed, TDC can output digital data of this clock period. The digital data map to the corresponding control word can find out the relation. In fig.3.9 shows this method. However, this method assumes DCO is linear. In practically, DCO has multiple control stages with different resolution. And each stage is close to linear. Thus do this method one time for different stage is suitable. The control bit m is the bit number between two control words c1 and c2. And c1 choose minimum control word and c2 choose maximum control word at each stage. Note that the difference between two control words can’t be too small or the factor K will be imprecise.

2 1

Fig.3.9. TDC value and control word mapping

With the relation factor K between TDC and DCO, phase error can transfer into DCO control word. The equation (7) shows the relation. Phase errorinit is initial error value sent from TDC. CPU will do this transformation.

0

1 1

( / ) 2

, 0

mod , 0

: number of relation fator : bit offset of

3.4.2. Frequency search algorithm

The frequency search algorithm is simple and as mentioned at section 3.1. The reference clock period can be estimated by TDC. For precise value, the half clock pulse is extended to full pulse with a register in fig.3.10. This can avoid unbalanced duty cycle of reference clock.

The period value Dref can transfer into control word and set to DCO. In this step, coarse frequency search is finished if watch dog not bark. Watch dog will bark when phase error value between reference clock and divided clock is bigger than clock period twice.

Fig.3.10 The estimation of reference clock

3.4.3. Coarse tracking algorithm

The basic idea of coarse tracking is fixing frequency error and phase error at this step.

However, DCO control word can’t change after phase error value is estimated at rising edge.

Double the error value, and set new control word maintain half period can solve this problem.

The steps of coarse tracking algorithm are shows in fig.3.11.

Initially, reference clock period is 2T½ and divided clock is 2T'½. The relation of these two clock is 2T'½=2T½+ε. Four steps of coarse tracking algorithm:

z Step 1: PFD detect phase error Δ.

z Step 2: PFD detect phase error Δ+ε. CPU find frequency error ε and calculate T′½+2ε+Δ, 2T′½+ε.

z Step 3: DCO set T′½+2ε+Δ in half period to fix phase error. At the end of clock period, phase is locked.

z Step 4: DCO set 2T′½+ε as new clock period and frequency is locked.

Fig.3.11. Waveform of coarse tracking algorithm

At this method, phase-locked state can represented as that phase error is small than TDCmin. If the frequency and phase is locked after four algorithm steps, algorithm enters fine tracking state. Else it does coarse tracking algorithm again. Fig.3.12 illustrates other situation by the proposed algorithm. Clearly, the proposed algorithm is reliable at different quadrant.

Fig.3.12. Different start position of coarse tracking algorithm

3.4.4. Fine tracking algorithm

After coarse tracking, phase error is smaller than TDCmin. For the reason of high-resolution and DCO has some extra control bit, fine tracking is essential. At this situation, PFD’s lead/lag signal and DCO fine tuning stage are useful information. The idea of fine tracking is binary search based. DCO increase clock period when divided clock is lead. Else decrease clock period when divided clock is lag. Each step decreases half of the search range.

Initial search range is TDCmin. There are four quadrants shows in fig.3.13. I and II are in phase-lead area. III and IV are in phase-lag area. In the idea case, the tracking point stays at II and IV and more and more closer to reference clock at binary search method. Point t1, t2, and

Initial search range is TDCmin. There are four quadrants shows in fig.3.13. I and II are in phase-lead area. III and IV are in phase-lag area. In the idea case, the tracking point stays at II and IV and more and more closer to reference clock at binary search method. Point t1, t2, and

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