Chapter 2 Overview of MIMO-SDPLL
2.5. Architecture Simulator and IP Model
2.5.2. PLL IP Model
As mentioned at section 2.2.3, there are two IP cores divide from ADPLL, error detector and DCO. For simulation at architecture simulator, these two IP cores are modelled. First, error detector has two inputs and one output. They are input reference clock and input divided clock with frequencyf andref f . Output is phase errordiv εout. In order to model clock, record clock frequency and phase offset is reasonable. The clock modelD can represent as ref
( , _ )
ref = ref ref offset
D T t
=1/
ref ref
T f
_ =( + _ ) mod
ref offset sys ref init ref
t t t T . (3) AndD is div
( , _ )
div = div div offset
D T t
T is clock period , t is current system time,sys tinit is initial time of rising edge and
offset
t represent offset time at t . Phase error is phase difference detected atsys t ,sys εoutcan derive as
_ _
εout =tdiv offset−tref offset (5)
If D phase leaddiv D thenref εout is positive else εout is negative. DCO model is similar to error detector. Input CTWd is digital data can use directly. Output DCO clock ctw D also dco record clock frequency and phase offset, T define as dco
= + ⋅
dco intr DCO ctw
T T k d (6)
T is intrinsic period of DCO. intr kDCOis DCO gain defined as a frequency deviation in response to 1 LSB of the inputd . Andctw tdco offset_ become dco offset dco init sys
dco dco
t and ′T is previous phase offset and clock period. dco tdco init_ is initial phase offset of DCO.
Ideally, whenTref =T and 0div εout = is frequency-locked and phase-locked.
Chapter 3
Tracking Algorithm
In PLL domain, high resolution and fast-locking time are important performance factor of tracking algorithm. The target of tracking algorithm is frequency-locked and phase-locked.
It can be separated into three parts, frequency search, phase tracking and phase maintaining.
At this section will discuss in detail from these parts.
As motioned at section 2, the proposed MIMO-SDPLL uses software to design tracking algorithm. The performance gap between software and hardware is a big design challenge.
And the control strategy is complex when many IP cores active at the same time. These issues also will be discussed at this section and a tracking algorithm for MIMO-SDPLL will be proposed.
The organization of this section is as follow. Section 3.1 introduce common concept of frequency search. Section 3.2 shows the concepts of phase tracking. Section 3.3 analyses the tracking problem and introduces a new expression of waveform. Section 3.4 proposes a tracking algorithm can reach frequency-locked, phase-locked and phase maintained.
3.1. Basic Concept of Frequency Search
In tracking algorithm, accurate frequency is essential for phase tracking. If frequency error between reference clock and divided clock is big, then phase error will change at every clock cycle. This let phase acquisition more complex. There are two common frequency search algorithms have been used. One is binary search based and another is TDC-based.
The basic concept of binary search based algorithm is “Prune-and-Search”. DCO search target frequency and divide half of search range at each step. After the search range reduces to
one, the frequency search is done. Then algorithm enters phase tracking and phase maintaining state. Fig.3.1 shows the concept.
Fig.3.1. Binary search concept
However, for fast-locking application, lock-in time is critical design issue. Thus TDC-based algorithm is proposed. It needs TDC converts timing information into digital data.
This is helpful for quickly calculation of the nearest CTW for DCO. With this idea, reference clock period information can be measured by TDC. And DCO quickly jump to the desired frequency as same as reference clock. Obviously, the lock-in time can be reduced. Fig.3.2 is basic structure of TDC. The internal delay chain measure input signal. And counter add one when input signal traverse the delay chain. TDC-based approach is chosen at this work.
Fig.3.2 The structure of time-to-digital converter (TDC)
3.2. Basic Concept of Phase Tracking
The basic concept of phase tracking algorithm is to minimize the phase error provided by phase detector. The simplest way is add constat control word after frequency search. Assume divider clock frequency is close enough to reference clock after frequency search. DCO control word will add (subtract) constant if phase is lag (lead). In fig.3.3 shows this process.
Initial phase error is Δ1, and phase detector report divided clock’s phase is lag. Because phase error Δ1 is unknown, control word subtracts a constant ε to reduce phase error. The Δ2, Δ3 and Δ4 are in similar process. Δ4 adds ε because phase is changed from lag to lead. Obviously, this method is slow and passive.
1
Fig.3.3 The simple phase tracking algorithm
In section 3.1, the TDC-based frequency search algorithm use TDC to speed up
frequency search. As the same idea, phase error can be measured by TDC. With this information, the control word can be calculated accurate. In fig.3.4, assume the same condition of fig.3.3. The divided clock period is as same as reference clock period, denoted as T. Because of frequency is locked, Δ2 equal to Δ1. So T′ can be inserted to fix phase error Δ1. From the derivation of these conditions, phase error becomes zero at Δ3.
initial error Δ1
Fig.3.4. TDC-based phase tracking algorithm
However, the two algorithms above, assuming perfect frequency locked which mentioned at section 3.1. In practical, frequency can’t lock perfectly because of the PFD’s dead zone, TDC’s resolution and DCO’s non-linear. To conquer these restrictions, a new tracking algorithm is proposed.
3.3. The Challenge of Tracking Algorithm
The algorithm of frequency search and phase tracking are discussed at section 3.1 and 3.2. However, phase tracking algorithm is affected by frequency search result considerably.
The information of frequency and phase need consider together. So the tracking problem requires be rechecked at this section.
Before describing the challenge of tracking algorithm, a more powerful expression of waveform is introduced. This expression is proposed at [6]. Fig.3.5 illustrates the new definition of phase tracking & frequency search problem. The horizontal line means the cycle
time of divided output clock or reference clock which is according to the scale of TDC.
TDCmin is TDC minium detectable range. The vertical line represents the phase relation between divided output clock and reference clock. The magnitude is according to the value of TDC, too.
Fig.3.5. Define of waveform expression.
The upper is original waveform and the bottom is anther expression.
For example of fig.3.5, the divided clock is lag Δ1 to reference clock at t0 initially. And divided clock period is longer than reference clock with valueε. So this relationship can be represented as (Tref +ε, -Δ1). The t0 point is located at the quadrant of longer cycle and lag phase. As the same process, t and t can be marked. And t and t shift down frequency error ε
at each cycle. In another case, if the divided clock is shorter than reference clock, the location of new points will be symmetric at Tref. But the direction is opposite to original. Summary, the right-hand side of Tref always shift down and left-hand side shift up. From this new definition, the tracking problem can be explained without drawing complex waveform which is hard to be understood.
In the example of fig.3.5, the DCO control word has not changed. Fig.3.6 shows the situation when setting new DCO control word.
Fig.3.6. Setting new DCO control word.
The tracking problem now can be transferred into another question. How to reach (Tref, 0) at any point of fig.3.6 is new target of algorithm. The straight way is setting new control word to DCO if there is phase error. But the frequency error between divided clock and reference clock let this manner become non-convergence. In fig.3.7, the path of algorithm will be a close loop, and the magnitude of phase error and frequency error will be cyclic. The proposed algorithm will resolve this problem and reach frequency-lock and phase-lock.
0
Fig.3.7. The close loop of tracking problem
3.4. The Proposed Tracking Algorithm
In this section, a new tracking algorithm is proposed. The basic idea comes from [2], and does some modification for MIMO-SDPLL. The algorithm flow is in fig.3.8. It is separated into three main part, frequency search, coarse tracking and fine tracking. Initially, algorithm start at frequency search state to get reference clock period. Second, if watch dog not bark then algorithm enters phase tracking state. The phase tracking has two parts, one is coarse and another is fine. This is decided by the resolution of PFD, TDC and DCO. Because DCO have extra control bit when TDC reach minimum detectable range TDCmin. More accurate tracking can do by these control bit and PFD signal. Phase tracking algorithm does coarse tracking continually, if phase error is bigger than TDCmin. Else algorithm will enter fine tracking state.
Notably, all states of proposed algorithm need tuning frequency and phase, this will explain later.
Fig.3.8 The algorithm flow
3.4.1. TDC and DCO relation mapping
Usually, TDC and DCO relation is known after IP selection. However, this relation will have some variation with PVT issue. Thus the training of this relation is required. Before start tracking algorithm, DCO clock connect to the input of TDC and software set different known control word to DCO. After DCO clock changed, TDC can output digital data of this clock period. The digital data map to the corresponding control word can find out the relation. In fig.3.9 shows this method. However, this method assumes DCO is linear. In practically, DCO has multiple control stages with different resolution. And each stage is close to linear. Thus do this method one time for different stage is suitable. The control bit m is the bit number between two control words c1 and c2. And c1 choose minimum control word and c2 choose maximum control word at each stage. Note that the difference between two control words can’t be too small or the factor K will be imprecise.
2 1
Fig.3.9. TDC value and control word mapping
With the relation factor K between TDC and DCO, phase error can transfer into DCO control word. The equation (7) shows the relation. Phase errorinit is initial error value sent from TDC. CPU will do this transformation.
0
1 1
( / ) 2
, 0
mod , 0
: number of relation fator : bit offset of
3.4.2. Frequency search algorithm
The frequency search algorithm is simple and as mentioned at section 3.1. The reference clock period can be estimated by TDC. For precise value, the half clock pulse is extended to full pulse with a register in fig.3.10. This can avoid unbalanced duty cycle of reference clock.
The period value Dref can transfer into control word and set to DCO. In this step, coarse frequency search is finished if watch dog not bark. Watch dog will bark when phase error value between reference clock and divided clock is bigger than clock period twice.
Fig.3.10 The estimation of reference clock
3.4.3. Coarse tracking algorithm
The basic idea of coarse tracking is fixing frequency error and phase error at this step.
However, DCO control word can’t change after phase error value is estimated at rising edge.
Double the error value, and set new control word maintain half period can solve this problem.
The steps of coarse tracking algorithm are shows in fig.3.11.
Initially, reference clock period is 2T½ and divided clock is 2T'½. The relation of these two clock is 2T'½=2T½+ε. Four steps of coarse tracking algorithm:
z Step 1: PFD detect phase error Δ.
z Step 2: PFD detect phase error Δ+ε. CPU find frequency error ε and calculate T′½+2ε+Δ, 2T′½+ε.
z Step 3: DCO set T′½+2ε+Δ in half period to fix phase error. At the end of clock period, phase is locked.
z Step 4: DCO set 2T′½+ε as new clock period and frequency is locked.
Fig.3.11. Waveform of coarse tracking algorithm
At this method, phase-locked state can represented as that phase error is small than TDCmin. If the frequency and phase is locked after four algorithm steps, algorithm enters fine tracking state. Else it does coarse tracking algorithm again. Fig.3.12 illustrates other situation by the proposed algorithm. Clearly, the proposed algorithm is reliable at different quadrant.
Fig.3.12. Different start position of coarse tracking algorithm
3.4.4. Fine tracking algorithm
After coarse tracking, phase error is smaller than TDCmin. For the reason of high-resolution and DCO has some extra control bit, fine tracking is essential. At this situation, PFD’s lead/lag signal and DCO fine tuning stage are useful information. The idea of fine tracking is binary search based. DCO increase clock period when divided clock is lead. Else decrease clock period when divided clock is lag. Each step decreases half of the search range.
Initial search range is TDCmin. There are four quadrants shows in fig.3.13. I and II are in phase-lead area. III and IV are in phase-lag area. In the idea case, the tracking point stays at II and IV and more and more closer to reference clock at binary search method. Point t1, t2, and t3 meet this case.
Fig.3.13 The problem of fine tracking
However, it is possible enters I and IV within the tracking process. Because the distance between current point and reference clock is unknown. If current point enters I and III, DCO will increase period in phase-lead state and decrease in phase-lag state. This misleads let frequency error become bigger than before. To solve this problem, the fine tracking algorithm need modified.
First, the observation in fig.3.14 shows that there is 50% probability change misleading
area to correcting area in one step. According to this characteristic, the algorithm adds a wait slot when phase not change first time. And do binary search again at next step. Repeat these two steps until phase change. Second, decrease half of search range only at phase changed.
Because phase change means reference clock is located in search range. Finally, if the search range reduce to DCO control word minimal value then algorithm enter frequency maintain state.
Fig.3.14. The observation of mislead area
In fig.3.15 demonstrate the example of fine tracking algorithm. First, initial tracking point is located at II. In order to become closer to reference clock, DCO increase clock period with gain. The value of gain depends on TDC minimal detectable range. The range between dotted line and reference clock is the TDC minimal detectable range in the figure.3.15. The search range record the sum of gain value until phase change.
Cycle time
Fig.3.15. The example of fine tracking algorithm
Second, after increase of DCO period, the phase not changed and the tracking point enters mislead area. As mentioned above, the wait slot is inserted. This wait slot lets DCO period unchanged. And the tracking point shift down because of longer clock period. Third, DCO increase clock period again. Fourth, the phase is changed. This means that the tracking point is in IV, correct area. And the search range is twice of gain. The new tracking point is in half of search range and gain is divided by two because of binary search method. Repeat the above action, tracking point will more and more closer to reference clock.
Fig.3.16 shows the complete working flow of fine tracking algorithm. Period represent divided clock period. Range is search range and wait_fin will be one when tracking point finish wait one time.
Fig.3.16. The working flow of fine tracking algorithm
3.5. Scheduling of MIMO-SDPLL
In MIMO-SDPLL, the number of error detector and DCO can more than one. Because OpenRISC is a single core CPU, it needs handle IP cores switched. It repeats pooling error detector’s error flag. If error flag is high, then CPU do correspondence action. At this work, the proposed MIMO-SDPLL is 2-by-2. Because CPU’s computing power is a restriction. Thus the simplest scheduling is used. The B set of error detector and DCO start tracking algorithm after A set reach frequency maintain state. Fig.3.16. shows this simple scheduling.
IP core A
IP core B
tracking tracking
maintain maintain
CPU time
waiting
Fig.3.16. The scheduling of 2×2 MIMO-SDPLL
However, it is notable that one stage execution time of tracking algorithm need small than the reference clock period of each combination of error detector and DCO. This can promise the correctness of tracking algorithm.
Chapter 4
Implementation and Simulation Result
In this section, the implementation of 2×2 MIMO-SDPLL is discussed at two parts, hardware and software. In hardware section, the implementation details of MIMO-SDPLL architecture are presented. In software section, the method of hardware control via software and software programming are presented. The hardware and software co-simulation result is showed at the end of this section.
4.1. Hardware
The overview of hardware architecture shows in fig.4.1. There are several IP cores include CPU, bus, error detector [3], DCO [7], SACA, memory and flash. The entire IP cores connect to the bus. Only CPU can send transaction request actively at this architecture. The DCO is high-resolution and wide frequency range proposed at [7]. The specification of IP cores list in table 1. The detail of IP cores is mentioned at following sub-section.
After reset signal is asserted, the CPU OpenRISC or1200 start fetching instructions from flash and execution them. These instructions are compiled form C source code. The entire tracking algorithm programmed in C source code. After hardware initial, CPU starts polling error detectors alternative. When reference clock and divided clock have phase error, the error detector will raise error flag signal. CPU then does one tracking algorithm stage for the correspond device.
Fig.4.1. 2×2 MIMO-SDPLL architecture
Table 1 Hardware specification
Item Description Process UMC 90nm SP_RVT Process
CPU
OpenRISC or1200
Maximum clock frequency: 250MHz Gate count: 10k
Bus
WISHBONE bus Architecture: shared bus
Maximum clock frequency: 250MHz
PFD
Minimum error pulse: 200ps
Minimum detectable clock difference: 45ps Gate count: 107
TDC Resolution: 15ps Gate count: 6k
Error detector
Divider
N Range: 1~1023
DCO Frequency range: 660KHz~460MHz Resolution: 10fs
Reference clock Frequency range: 660k/N~460M/N Hz
SACA 103~1231MHz of 64 stage Each stage: 140ps
Memory On FPGA board memory Address space: 8MB
Flash On FPGA board flash Address space: 8MB
4.1.1. Memory Map
There are several I/O devices in MIMO-SDPLL. CPU needs access these devices from bus. The common method is that all I/O devices include memory are treated as a whole memory. Thus software can communication with specific hardware depends on this memory map. Fig.4.2 is the memory map at this work.
Fig.4.2 Memory map of 2×2 MIMO-SDPLL
4.1.2. CPU
The selection of CPU is OpenRISC or1200. Or1200 support cache, MMU and basic DSP capabilities. For direct use and area issue, the above function doesn’t implement in this work.
By default configuration, the divided is simulation by multiplier with the help of compiler. It needs implement because the software is compiled without standard library. At UMC90 process, or1200’s gate count is 10k and has maximum frequency up to 250MHz.
4.1.3. WISHOBONE Bus Protocol
For CPU compatibility and IP cores connection, the WISHBONE [8] bus is chosen.
For CPU compatibility and IP cores connection, the WISHBONE [8] bus is chosen.