Thesis Organization

Following is the main contents of this thesis. In Chap 2 we will discuss the recent low-voltage SRAM design, which including some cell topologies and read/write assist circuit in low-voltage region. Basic SRAM operation and the definition of cell stability and write-ability will also be introduced. An 8T SRAM bit-cell with data-aware write-assist (DAWA) scheme will be introduced in Chap 3, including read/write operation and the simulation result of cell stability and write ability in different PVT condition. The adaptive write time tracing circuit will also be introduced in Chap 3, too.

In Chap 4, a ripple bit-line read scheme with hierarchical global bit-line will be introduced. We will discuss the leakage current topic in SRAM design in this chapter. A Local bit-line keeper design used in this DAWA 8T cell will also be introduced in Chap 4. In Chap 5, we design a Low-VDDMIN 512kb 8T SRAM design in 40nm CMOS process, including the circuits which are refereed in Chap 3 and Chap 4. Performance and power of this low VDDMIN 512kb 8T SRAM will be discussed, too. Chapter 6 finally concludes this thesis.

Chapter 2

Overview of Recent Low-Voltage SRAM

2.1 Introduction

This chapter is a study of basic SRAM operation, basic concept of SRAM bit-cell stability, power dissipation of CMOS technology and recent low-voltage SRAM design.

Typical SRAM array structure and the schematic and operation of conventional 6T SRAM cell are presented in section 2.2. The basic concept of SRAM bit-cell stability and the measurement of SRAM bit-cell stability / write-ability are presented in section 2.3. Power dissipation, consisted of dynamic power dissipation, leakage dissipation and short-circuit dissipation, are introduced in section 2.4. Some recent low-voltage SRAM bit-cells are presented in section 2.5. Recent read-assist or write-assist circuitry in low-voltage SRAM design is presented in section 2.6. We make a summary in section 2.7.

2.2 Conventional SRAM design

2.2.1 Typical SRAM Array Structure

Fig. 2.1 shows a typical SRAM array structure, with four pages of N-rows by M-bits array. We can see the SRAM cell, row decoder, column decoder, sensing- amplifier, write driver, and timing block. Row decoder is gated by appropriate timing signal generated by timing block. Row decoder decodes the X-address signal and selects one of word-lines turning on. Z-decoder decodes the Z-address signal to select the pages. Column decoder, which decodes the Y-address signal, allows sharing a single sense amplifier of multiple columns. In a word-oriented SRAM, each address points to

a word of n bits (common value are 4, 8, 16, 32 or 64 bits). Timing signals in all of SRAM macro are generated by timing block.

Fig.2. 1 SRAM array structure [2.1]

2.2.2 SRAM Column Circuitry

Write Driver

SRAM Array

Precharge Circuit

Fig. 2.2 shows the SRAM column circuitry of a normal single-port SRAM. The pre-charged circuit is composed of two pre-charged PMOS and one equalizer PMOS.

Pre-charged PMOS can pre-charge both bit-lines to VDD on stand-by mode. Equalizer PMOS equalizes both bit-lines to same voltage to solve voltage offset before read/write operation. Write-driver pulls down one of bit-lines to “0” determined by input data. We can also see the schematic of typical differential-based sensing amplifier consisted of cross-couple inverter-type latch. Once the sensing amplifier is activated, it can sense the different voltage between bit-line pair, latch read data through regenerative feedback.

2.2.3 Conventional 6T SRAM Bit-cell

QB Q

WL

BLC BLT

PL PR

NL NR

AXL AXR

Fig.2. 3 Schematic of conventional 6T SRAM bit-cell

Fig. 2.3 shows the schematic of conventional 6T SRAM bit-cell. This SRAM cell consists of two cross-coupled inverters (PL, PR, NL and NR), two pass-gate (AXL and AXR) transistors, one word-line and two complementary bit-lines. Two cross-couple inverters store the binary data and pass-gate transistors provide read/write access into the cell. Word-line controls the bit-line pair connecting to cross-couple inverter by turning on pass-gate transistors M5 and M6. Fig. 2.4 shows the layout view of this 6T

SRAM bit-cell.

Fig.2. 4 Layout view of conventional 6T SRAM bit-cell [2.2]

Fig. 2.5 shows the read operation of conventional 6T SRAM bit-cell. When read operation occurs, both BLC and BLT are pre-charged to VDD initially, and then WL is turn on by WL driver addressed by X-address signal, connecting the cell node to the bit-lines. For each bit-cell in a word, determining by storage data, one of two bit-lines will be discharged. Different signal is generated and send to the sensing-amplifier.

Sensing-amplifiers transfer the different signal into the full swing signal and latch the data at the read output.

Fig.2. 5 Read operation of conventional 6T SRAM bit-cell

Fig. 2.6 shows the write operation of conventional 6T SRAM bit-cell. When write

two bit-lines is pulled down by write driver determined by input data and WL is turn on by WL driver addressed by X-address signal, connecting the cell node to the bit-lines.

Once one of two bit-lines is pulled down and word-line is turn on, data will be flipped and then latched by cross-coupled inverter. Finally input data is written into the cell node.

Fig.2. 6 Write operation of conventional 6T SRAM bit-cell

2.3 SRAM Bit-cell Stability and Write-ability

2.3.1 Static noise margin

During stand-by mode, the WL of the 6T cell is low so that the pass-gate transistor is off. The cross-coupled inverters must maintain bi-stable operating point to properly hold the data. The best common way to measure the stability of cross-coupled inverters is the static noise margin (SNM) [2.3]. We defined Hold SNM as the maximum DC noise voltage which is placed to the gate and the Q/QB of cross-coupled inverters which can be tolerated by the SRAM cell. In other words, hold SNM is the value of the maximum voltage which is placed between the gate and the Q/QB of cross-coupled inverters which can maintain the storage data of the SRAM cell. Fig. 2.7 shows the

setup schematic for measuring the Hold SNM. VN is the DC noise source which is placed to the gate and the Q/QB. When VN is increased, the Hold SNM of cell is changed.

Fig.2. 7 The standard setup of measuring the Hold SNM

Fig. 2.8 shows the butterfly curve, which is the most common way to represent the SNM graphically. The butterfly curve contains the voltage transfer characteristic (VTC) of one of cross-coupled and inverse VTC of the other inverter. The SNM is defined as the length of the side of the largest square which can be fit into the eyes of the butterfly curve.

Fig.2. 8 Butterfly curve of Hold SNM (Conventional 6T SRAM cell) [2.3]

During read operation, the WL of the 6T cell is high so that the pass-gate transistor

hold the data when read operation. The best common way to measure the read stability is the read static noise margin (RSNM) [2.3]. The definition of SNM is defined in the previous section. Fig. 2.9 shows the setup schematic for measuring the Read SNM. WL is on for reading access; BLC and BLT are both set to VDD to indicate the initial condition of read access.

Fig.2. 9 The standard setup of measuring the Read SNM

In conventional 6T cell, read SNM is worse than hold SNM. When read operation, WL is turn on and one of two bit-lines is discharge to a lower voltage. The “0” node will rise a little voltage because of the voltage diving effect between the pass transistor and pull-down transistor. Once the disturb voltage rise near to the trip point of the inverter, data will be flipped. Fig. 2.10 shows the butterfly curve of read SNM and hold SNM of conventional 6T SRAM bit-cell, revealing read SNM is worse than hold SNM in conventional 6T SRAM bit-cell.

Fig.2. 10 Hold SNM vs. Read SNM (Conventional 6T SRAM cell) [2.5]

2.3.2 Write trip point

Although there are many way to measure the write-ability of SRAM bit-cell, find the write trip point (WTP) is the most common and easiest way to measure the write-ability of SRAM bit-cell. WTP is defined as the maximum voltage on the BL which can make the data in the cell be flipped. Fig. 2.11 shows the setup schematic for measuring the WTP. Fig. 2.12 shows the result of finding the WTP. We fix one of the two bit-lines at high voltage and sweep the other bit line from VDD to GND, trying to flip the data in the cell. Once bit-line is lowered to a certain level, data will be flipped, indicating a successful write access. Larger WTP indicates the smaller voltage we need to lower bit-line voltage below VDD for a successful write. If the WTP value is negative, it means that although we lower the voltage of bit-line to GND, the data will not be written in. It is impossible to write data into the cell when WTP is negative, unless we can lower the bit-line voltage to negative level. We make a conclusion that higher WTP represents the better write-ability.

Fig.2. 11 The standard setup of measuring the WTP

VBL(V)

Internode voltage (V)

Fig.2. 12 Write trip point (WTP) of conventional 6T SRAM bit cell [2.7]

2.3.3 The disadvantage of 6T SRAM Bit-cell

In 0.35, 0.18 and 0.13 μm CMOS process, 6T SRAM Bit-cell is the main structure in embedded memory. Due to some disadvantages, 6T SRAM bit-cell is not suitable under 90nm process. It is also not suitable in low-voltage operation.

First is read and half-select disturbs. The reason of generating read disturb is introduced in previous section. Furthermore, in advanced process and low-voltage operation, threshold voltage variation maybe makes the disturb voltage larger than the trip voltage of the other inverter, which can cause losing the original data in the bit-cell.

In additional, there is a half-select disturb in interleaving SRAM structure. When a read/write operation, one of word-lines is turn on, the half-select cells in the same row are also doing pseudo read operation, where read-disturb also occurs. Fig. 2.13 shows the read-disturb of 6T SRAM bit-cell under different process. Cell-switch point voltage and read-down level voltage may overlap under 90nm process.

Fig.2. 13 The read-disturb of 6T SRAM in different process [2.8]

The second is the conflicting requirements between different operations. During stand-by mode, if we want to improve the cell stability, we can higher the trip point of inverters by making the pull-down transistors weaker and pull-up transistors stronger.

We define this ratio as β1 ratio. To improve read SNM and minimize read-disturb, we can make the pull-down transistors stronger and the pass-gate transistors weaker. We define this ratio as β2 ratio. To improve the write-ability of SRAM cell, we can make the pull-up transistors weaker and the pass-gate transistors stronger. We define this ratio as β3 ratio. We can find that one of three β ratios is conflict to each other β ratios, as Fig.

2.14 shows. As mentioned, conventional 6T SRAM cell is susceptible of large PVT variation and local VT mismatch in advanced process. Enlarge β2 and β3 ratio can stabilize the 6T SRAM bit-cell but increased much more area and consume much more power.

Consequently, the tradition 6T bit-cell stability (Hold SNM and Read SNM) and write-ability will degrade dramatically in low-voltage due to the PVT variation and local VT mismatch. Fig. 1.3 shows this result. In addition, as mentioned in chap 1.2, Ion/Ioff ratio decrease dramatically when operating voltage is scaled down. In summary, the VDDmin of 6T SRAM bit-cell is limited to high voltage (e.g. >0.8V at 65nm)

2.4 Power Dissipation

As equation (1.1), power dissipation in CMOS circuit is composed of three main components, dynamic power dissipation, leakage power dissipation, and short-circuit power dissipation. Each kind of power dissipation will be introduced in the following.

2.4.1 Dynamic Power Dissipation

Fig. 2.15 shows a CMOS inverter with loading capacitance CL. The average dynamic power dissipation can be obtained by summarizing the average dynamic power of NMOS and PMOS. The primary dynamic dissipation component is charging and discharging the load capacitance. Suppose the operating frequency of inverter is f and the input Vin is a square wave with a period T, the load capacitance CL will be charged and discharged T * f times. In one complete charge and discharge cycle, a total charge of Q = CL *VDD will be charged or discharged in the CL. The average dynamic power of this inverter is given by



( to the total charge of the loading capacitance

between the period T * f *CL*VDD, the equation 2.1 can be simplified to

f V C

P_D  _L _DD² (2.2)

Because gates usually do not switch every cycle, we must consider switching probability; thus we add a switch factor α into equation 2.2. Dynamic power can be expressed as

f V C

P_D  _L _DD² (2.3)

From equation 2.3, we know that dynamic power of logic gates is proportional to the square of supply voltage, switch factor, operating frequency and loading capacitor.

Fig.2. 15 Circuit diagram of inverter

2.4.2 Leakage Power Dissipation

As shown in Fig. 2.16 I1 is Reverse-bias PN-junction current; I2 is sub-threshold current; I3 is gate oxide tunneling current; I4 is gate hot-carrier injection current; I5 is gate-induced drain current and I6 is channel punch-through current. The mentioned six current are composed of leakage current in CMOS transistors. Sub-threshold current, gate-induced drain current and punch-through current are off-state leakage mechanisms, while Reverse-bias PN-junction current and oxide tunneling current are on-state leakage mechanisms. Gate hot-carrier injection current can occurs either in off-state or

during the transistor bias states in transition. Each source of leakage current will be introduced in the followings.

Fig.2. 16 Leakage current in NMOS transistor [2.13]

Reverse-bias PN-junction Current

Drain and source to well junctions are typically reversing biased, causing PN junction leakage current. There are two main components of a reverse-bias PN junction current, one is minority carrier diffusion/drift near the edge of the depletion region; the other is due to electron-hole pair generation in the depletion region of reversed-biased junction. In nano-scale MOSFETs, due to the use of high junction doping, large junction band-to-band tunneling (BTBT) occurs with drain at VDD and substrate at ground. The junction BTBT exponentially increases with an increase in the drain-to-substrate bias. We model Reverse-bias PN-junction current as following

)) (

0exp( JN DD db

jn

jn I V V

I    (2.4)

Where I_jn0is the junction leakage at V_db = V_DD and _JNis a doping dependent factor. The area of the drain diffusion and the leakage current density has impact on Reverse-bias PN-junction current, which are determined by the doping concentration.

Sub-threshold Current

Sub-threshold or weak inversion conduction current flowing from drain to source during the Vgs is below the threshold voltage (off-state). In the weak inversion, the minority carrier is small, but not zero. For the NMOS transistor, even if Vgs = 0V, there is still a current path in the channel of the NMOS transistor due to the VDD potential of the VDS. Unlike the strong inversion region in which the drift current dominates, the sub-threshold current is dominated by the diffusion current. Due to short-channel effect, the sub-threshold current increases with an increase in the drain bias (Drain Induced Barrier Lowering) and a reduction of channel length (VTH-roll off). Due to the body effect, the sub-threshold current reduces with the application if the reverse body-bias.

We model the sub-threshold current as following / ) the sub-threshold swing factor.

Sub-threshold current roughly increases by a factor of five at each new technology.

Such increase is due to the scaling of sub-threshold voltage and short-current effect, caused by gate length reduction. In summary, sub-threshold current becomes the biggest source of leakage current in modern transistors.

Gate oxide Tunneling Current

Gate oxide tunneling current in transistors with ultra-thin gate oxide is due to the direct tunneling of electrons (or holes) through the gate dielectric. Oxide tunneling current increases exponentially with reduction in the oxide thickness and increase in the electric field across the oxide. Fig. 2.17 shows the components of Oxide tunneling current in a scaled NMOS transistor.

Fig.2. 17 Components of tunneling current [2.13]

Gate oxide tunneling current is composed to the three elements:

1. Major components of oxide tunneling current are gate to source/drain overlap region current (Igdo and Igso).

2. Gate-to-channel-current (Igc), which goes to the source (Igcs) or to the drain (Igcd)

3. Gate-to-Substrate current (Igb)

Therefore, the gate oxide tunneling current can be divided into the following components

1. Gate-to-source (Igs = Igso + Igcs) 2. Gate-to-drain (Igd = Igdo + Igcd) 3. Gate-to-substrate (Igb)

The overlap current dominates the gate oxide tunneling current in the “OFF” state whereas gate-to-channel dominates the gate oxide tunneling current in the “ON” state.

We model gate oxide tunneling current as following

)

0

IgON is the ON state gate-to-drain leakage at |Vgs| = VDD. The magnitude of the gate leakage current increases exponentially with the gate oxide thickness Tox and the Vgs as shown in Fig. 2.18 and Fig. 2.19, respectively. [2-14]

Fig.2. 18 Gate leakage current vs. gate oxide thickness [2.14]

Fig.2. 19 Gate leakage current vs. gate voltage [2.14]

Gate hot-carrier Injection Current

In the short-channel transistor, because of high electric field near the Si–SiO2

interface, electrons or holes can get sufficient energy from the electric field to field to cross the interface potential barrier and enter into the oxide layer. This is known as the gate hot-carrier injection current.

Gate-induced Drain Current

This current from drain to bulk is caused by high electrical fields in the gate-drain overlap region. Gate-induced drain current occurs in large VDB and generates carriers into the substrate and drain from surface traps or band-to-band tunneling. Thinner oxide thickness and higher VDD enhance the electric field and therefore increase GIDL. In addition, at low drain doping, the electric field is not too enough to cause tunneling. By contrast, at very high doping, the depletion width and tunneling volume is restricted, causing less GIDL. In summary, GIDL is worse for moderated drain doping.

Channel Punch-through Current

In short-channel devices, due to the proximity of the drain and the source, the depletion regions at the drain-substrate and source, the depletion regions at the drain-substrate and source-substrate junctions extended into the channel, As the channel length is reduced, if the doping is kept constant, the separation between the depletion region boundaries decreases. An increase in the reverse bias across the junctions (with increase in VDS) also pushes the junctions nearer to each other. When the combination of channel length and reverse bias leads to the merging of the depletion regions, channel punch-through current have occurred.

Leakage current in Tradition 6T SRAM bit-cell

Fig.2. 20 Leakage current in conventional 6T SRAM bit-cell [2.12]

Fig. 2.20 shows all kind of leakage current in conventional 6T SRAM bit-cell,

Fig. 2.20 shows all kind of leakage current in conventional 6T SRAM bit-cell,