Chapter 2 Overview of Recent Low-Voltage SRAM
2.5 Recent Low-voltage SRAM Bit-cell Design
2.5.1 Single-ended 8T SRAM Bit-cell
Fig.2. 21 Single-ended 8T SRAM bit-cell [2.6]
Fig. 2.21 shows this single-ended 8T SRAM bit-cell. This cell added two extra transistors as read buffer, which make cell node decoupled from RBL. Consequently, this cell is read-disturb free and the read SNM of the cell is much better than conventional 6T cell. Because of the separation of read-port and write-port like register
files, we can improve read-stability and write-ability without conflicting requirement.
By using single-ended read port and hierarchical BL scheme. This cell is designed in a high-performance 32kb sub-array in 65nm PD-SOI CMOS process and can operate at 5.3GHz in 1.2V and 295MHz at 0.41V. Fig. 2.22 shows the improvement of Read SNM between this 8T cell and conventional 6T cell
Fig.2. 22 Read SNM of conventional 6T-SRAM & single-ended 8T-SRAM [2.6]
One of ISSCC 2010 paper about Core Implemented contributed by AMD [2.16], it said that single-ended 8T SRAM is commonly used in recent single-VCC microprocessor core for its performance critical low-level caches and multi-ported register-file arrays. However in write operation, once one WWL is pulled-up, all of pass-gate transistors in the same row are turn on. Because of full VDD on WBL and WBLB which are pre-charged in stand-by mode, so once WWL is pulled-up, stored node will be affected by BL, called pseudo read or Half-select disturb. In summary, this 8T cell eliminates read-disturb, improving the read SNM. But this 8T cell still suffers from Half-select disturb.
2.5.2 Differential Data-aware Power-supplied 8T Cell
conventional SRAM cell, the cross-coupled inverter of this cell is supplied by bit-line pair instead of sharing the same power lines. Fig. 2.22(b) and (c) shows the waveform of read and write operations.
Fig.2. 23 (a) The schematic of D2AP 8T cell (b) waveform of write operation (c) waveform of read operation [2.17]
In stand-by mode, ZWL=0, both BL and BLB are pre-charged to VDD and VDDL and VDDR are pre-charged to VDD through PSWL and PSWR. In write-0 operation, ZWL = 0, WL = 1 and BL is pulled-down to 0, VDDL is reduced by PSWL, which improve the write-ability in write-0 operation. In contrast, in write-1 operation ZWL = 0, WL = 1 and BLB is pulled-down to 0, VDDR is reduced by PSWR. In read operation, ZWL and WL are VDD. There is an additional discharge path through PSW and PU transistors either read-1 or read-0. Due to additional discharge path and differential read scheme, the noise immunity and read access time is better than single-ended 8T cell. In
half-select cell, self-negative feedback can reduce VDDL or VDDR, lowering the trigger point of inverter and providing a better cell stability. The disadvantage of this cell is floating “1” on un-selected row because of ZWL = 1. A 39Kb sub-array is designed in 45nm process. The VDDmin is 540mV, 200~240mv better than single-ended 8T SRAM in same array structure.
2.5.3 A Large σVTH/VDD tolerant zigzag 8T SRAM (Z8T)
Fig.2. 24 Schematic of Z8T SRAM cell (b) Layout view of Z8T SRAM cell [2.18]
Fig. 2.24 shows the schematic and layout of σVTH/VDD tolerant zigzag 8T SRAM. In stand-by mode WWL=0 and RWL =1 so both BL and BLB is clamped to VDD through un-selected NR0 and NR1, reducing the BL leakage current. This Z8T cell can have long BL structure.
When read-operation, WWL =0 and RWL = 0. RBL and RBLB will be discharged according to data in the selected cell. Because of cell node decoupled from RBL, the Read SNM of Z8T cell will be improved. The write-operation is similar to conventional 6T cell. A 32Kb sub-array with this Z8T cell is designed in 65nm process. Hierarchical WL structure and differential read and write-back sense amplified are used. The
2.5.4 A Novel Column-Decoupled 8T Cell (CDC-8T)
Fig.2. 25 Selected and half-selected cell of CDC-8T [2.19]
Fig. 2.25 shows the selected cell and half-selected cell of this CDC-8T, which can eliminate half-select condition. On selected cell, GWLE is 0 and BDT0 is 1, so LWLE0 is 1 during read or write operation. On the half-selected cell, GWLE is 0 but BDT1 is.
LWLE1 is 0. By this column-decoupled scheme, read half-select disturb can be eliminated. This CDC-8T cell can also be interleaved to solve the soft-error-rate problem by using simple ECC. The half-select free design enables further voltage scaling. The VDDmin of this cell is 150mv smaller than conventional 6T cell in 1.6Kb sub-array in 90nm PD/SOI process. [2-19]
2.5.5 Schmitt-Trigger-Based SRAM Design (ST cell)
Fig. 2.26 shows a Schmitt-trigger-based SRAM bit-cell (ST cell). In hold operation, due to stack pull-down transistors, the hold SNM is better than conventional 6T cell. Input-dependent transfer characteristics of Schmitt-trigger improve both read-stability and write-ability. Furthermore, the storage node is isolated from the BL/BR because the WWL is off during read. It can improve read stability-too. In write
operation, there are two discharge paths through AXL1/AXR1 and AXL2/AXR2 which can improve write-ability, too. This ST cell proposed 1.6X read-stability, 2X write-ability and 120mv lower read VDDmin compared to iso-area conventional 6T bit-cell in 130-nm CMOS process [2-2][2-20]
Fig.2. 26 ST SRAM bit-cell schematics [2.2] [2.20]
2.5.6 Column Line Assist 10T SRAM cell (CLA-10T)
Fig.2. 27 CLA-10T SRAM (a) schematic (b) layout [2.21]
Fig. 2.27 shows the schematic and layout of CLA-10T cell. The Read SNM is worse than previous bit-interleaving 10T SRAM [2-22] because both outside and inside
pass-gate transistors are pulled-up to VDD when read operation and cell-node is not decoupled of BL. When read operation, WL is pulled-up to VDD, BL and BL/ are pre-charged to VDD in advance and CL and CL/ are pulled down to GND. The read current is larger than prior 10T SRAM due to an additional discharging path from BL to CL.
In write operation, WL is VDD. One of BL pair will be discharged to GND, same as CL pair. There is an additional path from CL to cell node which improves the write-ability of this CLA-10T cell. A 128Kb CLA-10T SRAM array is designed in 45nm process. The VDDmin is 0.56V.