Thesis Organization

This thesis is arranged as follows. In chapter 2, we introduce the basic structure and timing definition of the video display system. A survey and the design challenges of the line-locked PLL are also described. In chapter 3, all the details of the proposed ADPLL clock generator, including the circuit architecture, functional blocks, and control algorithm, are presented. The chip implement, simulation, and measurement results are reported in chapter 4. Finally, we make conclusions and point out several design issues that need to be explored in the future in chapter 5.

Chapter 2

Overview of Video System and Line-Locked PLL

2.1 Video System Basics

The video display system structure, video signal timing definition, and monitor timing specification are presented in this section.

2.1.1 Video Display System Structure

A brief video display system diagram [14] is shown in Fig. 2.1. The essential Red/Green/Blue (RGB) video signals are delivered along with vertical synchronous (Vsync) and horizontal synchronous (Hsync) signals by random access memory digital-analog converter (RAMDAC) of the computer. The main function of the RGB acquisition interface is to convert the analog video signals into digital signals through variable gain amplifier (VGA) and analog-to-digital converter (ADC). The sampling clock of the ADC comes from a clock generator, usually a PLL. This clock generator receives low frequency Hsync from computer and produces high frequency pixel clock according to the screen resolution of the display system. In other words, the pixel frequency is determined by the input Hsync frequency and the horizontal resolution. This pixel clock acts as sampling clock for converting the analog video signals into digital signals. The digital video signals are sent to digital processor and then transmitted to the display system. The multiple between Hsync and pixel clock is proportional to the screen horizontal resolution. Many popular monitor timing specification have been established by video electronics standards association

(VESA). A finer image quality has a higher screen resolution. Take one of the XGA mode as an example, the Hsync frequency is 48.4 KHz while the pixel frequency is 65.0 MHz. The pixel clock is 1344 times the frequency of the Hsync signal. Therefore, the frequency multiplication factor of the clock generator is 1344.

Fig. 2.1. A brief video display system diagram [14]

The stability of this sampling clock plays an important role to the display system performance. The video signal and sampling clock timing diagram [14,16,18,20,25] is shown in Fig. 2.2. The only valid sampling duration is the portion when video signal is stable. On the contrary, the signal transition region is invalid sampling interval. Once the sampling point locates in the invalid intervals, the acquired video data would be corrupted. Consequently, the image on the display screen will be distorted.

Fig. 2.2. Video signal and sampling clock timing diagram

2.1.2 Video Synchronous Signal Timing Definition

The video synchronous signal timing definition [57] is shown in Fig. 2.3. The video synchronous signal is composed of synchronous pulse (Sync), front porch (FP), back porch (BP) and active video subsections. The period of vertical synchronous signal defines the time interval of a display frame, i.e. the refresh time between two images. The period of horizontal synchronous signal defines the time interval of a scan line. The screen is blank from the start of front porch to the end of back porch.

The image pattern only displays on the screen during the active video period. From these definitions, we know that the monitor display area is only the central active part of the screen as shown in Fig. 2.4.

Fig. 2.3. Video synchronous signal timing definition

Fig. 2.4. Monitor display area

Now, taking a closer look at the synchronous signals and the pixel clock. For an MxN display resolution, where M means the active horizontal resolution and N means the active vertical resolution, the period of Vsync is N times of Hsync while the period of Hsync is M times of pixel clock. That is to say, in the active display area, there are N horizontal scan lines in one display frame and there are M pixels in one horizontal scan line in case of an MxN display resolution. The more detail timing diagram [18,19,57] is shown in Fig. 2.5.

Fig. 2.5. Separate Vsync/Hsync signal and pixel clock timing diagram

2.1.3 Monitor Timing Specification

Many industrial standards of monitor timing specification have been developed by VESA for a long time. The most popular display modes are VGA (Video Graphics

Array), SVGA (Super Video Graphics Array), XGA (Extended Graphics Array), SXGA (Super Extended Graphics Array), and UXGA (Ultra Extended Graphics Array). The monitor timing specifications [57] of these modes are listed in Table 2.1.

The active resolution defines the displayed horizontal and vertical ranges, while the total resolution includes the blank area. It is worthy of noticing that the frequency multiple relation between Hsync and pixel clock is the total horizontal resolution not the active one. For instance, the pixel clock is 800 times the frequency of the Hsync instead of 640 times in the 60 Hz refresh rate 640x480 resolution VGA mode.

Table 2.1. Monitor timing specification

2.2 Line-Locked PLL Overview

The so-called line-locked or video capture PLL is a clock generator employed in the video acquisition interface that generates a pixel clock, which is phased-locked with the horizontal synchronous signal as mentioned in the previous section. The large frequency multiplication factor of this kind PLL is inherent in the video display system. We will deliver several line-locked and large multiplication factor PLL examples briefly and make a summary of this section.

2.2.1 A Survey of Line-Locked PLL

The first video line-locked PLL [22] example is illustrated in Fig. 2.6. This PLL is composed of phase detector, frequency detector, charge pump, VCO, clock divider, and control unit. The control mode flow chart of this circuit is shown in Fig. 2.7. The control unit operates in conjunction with phase detector and frequency detector to provide one of five modes of operation: coarse frequency (CFR), fine frequency (FFR), coarse phase (CPH), fine phase (FPH), or hold (HOLD). It needs an external RC as loop filter.

Fig. 2.6. Video line-locked PLL block diagram [22]

Starting from an out-of-lock condition with a large frequency error, the PLL goes into the CFR mode where frequency error is adjusted in approximately ±4%

steps. After stepping the clock frequency within 4% of that desired, the PLL goes into the FFR mode. When the clock frequency is around 2% of that desired, the PLL goes into CPH mode. Finally, when the phase error is within 2 clock periods, the PLL goes into FPH mode. If the input HSRef signal disappears, the PLL goes into the HOLD mode and the VCO control voltage is held fixed until HSRef is restored. In additional, the ÷N counter divides the clock frequency by Nset and outputs ClkDiv pulse. The decimal value of Nset is expected to be between 750 and 2600. There is provision for resetting the phase of ClkDiv to align with HSRef by means of reset pulse Reset generated in CPH mode.

Fig. 2.7. Control mode flow chart [22]

The second example is video capture PLL by Analog Bits Inc. [23]. This PLL circuit is composed of phase/frequency detector, numeric-controlled oscillator, phase interpolator, clock divider, control unit, and two internal PLLs. An internal PLL generates a 5-phase 660MHz clock from a 14.3MHz system reference clock as a high precision time reference. The PLL utilizes a high precision 28-bit digital frequency synthesizer, with a programmable all-digital loop filter making it possible to generate an output clock with less jitter. A 12-bit clock divider can accomplish the frequency multiplication. A controllable fine phase delay line is inserted in the output path for external phase adjustment purpose.

Fig. 2.8. Video capture PLL [23]

Another example is low refresh rate PLL by CEVA Inc. [24]. This is a 2-stage cascaded loops structure. Each stage is composed of phase/frequency detector, charge pump, VCO, and clock divider. The first stage accepts a low refresh rate reference clock and generates a 24-36MHz clock according to mSel. The second stage

multiplies this intermediate clock to a high frequency clock according to nSel. Finally, an output divider can divide the clock to a desired frequency by setting the divSel.

Overall, the target multiplication factor of this PLL can be obtained by properly arranging the setting of mSel, nSel, and divSel.

Fig. 2.9. Low refresh rate PLL [24]

2.2.2 A Survey of Large Multiplication Factor PLL

Because the large frequency multiplication factor is inherent in the video application PLLs, this type of PLL is also described in this section.

One of the large frequency multiplication factor PLL [26] is shown in Fig. 2.10.

This PLL consists of four modules: (1)current-controlled oscillator, (2)frequency control logic, (3)phase control logic, and (4)arithmetic module. The counter counts the number of Fcco cycles during a time frame defined by M cycles of the reference frequency. This number is then compared to the value of N. The desired relation between Fcco and Fref id given by Fcco=Fref*(N/M). The result of the comparison determines the next value of S, which controls the current of CCO. The arithmetic unit is responsible for the implementation of current control formula.

Fig. 2.10. A large frequency multiplication factor PLL [26]

Another example of large frequency multiplication factor PLL is illustrated in Fig. 2.11. This is an all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time [27]. It uses a time-to-digital converter (TDC) as a frequency and phase detector, and a DCO as a frequency variable oscillator. The time resolution of both circuits is determined by a common ring-delay-line (RDL), so the time resolution is always the same, i.e. one individual inverter propagation delay time.

This RDL is a novel ring oscillator composed of even number of inverters and NAND gates [53] that provides 32 poly-phase delay clocks (P1-P32) for TDC and DCO. First, The period of external reference clock CKI is digitized (DA=n) by the TDC circuit with the unit gate delay time of RDL. Next, the ratio of this data and the multiplication factor N is calculated in the digital processing section, and the output clock control data CD is generated (CD=n/N). Then, an output clock CKO with a period TCK corresponding to this control data CD is generated. Finally, one of the 32

poly-phase clocks with its phase is closest to the reference clock is selected to be the output clock. The frequency and phase acquisition process are finished in seven cycles.

Fig. 2.11. A 4 to 1022 multiplication factor PLL [27]

The last example is a 1 to 4096 frequency multiplication factor self-biased PLL [28]. The PLL architecture is shown in Fig. 2.12. It consists of a phase/frequency detector, two charge pumps, loop filter, a voltage-controlled oscillator, and a clock divider. The architecture is similar to a conventional PLL. The key element of this circuit is the two charge pumps with shunt capacitors in the loop filter. This kind of structure can minimize the pattern jitter that will repeat every reference cycle or N output cycles.

Fig. 2.12. A 1 to 4096 multiplication factor PLL [28]

2.2.3 Summary

Some design problems of the early PLLs are listed in Table 2.2. Some problems can be eluded by means of elaborate design techniques. Nevertheless, some of them accompany with the design structure. For instance, the video capture PLL [23] will always suffer the power consumption problem owing to the internal high frequency multiphase clocks.

Table 2.2. Some design problems of early PLL publications

2.3 Design Challenge

In this section, three main design challenges of the line-locked PLL are presented. These are the key factors of designing a pixel clock generator with good performance.

2.3.1 The Difficulty of Large Multiplication Factor PLL Design

The first thorny problem is the difficulty of designing a large frequency multiplication factor PLL. The frequency multiplication factor of line-locked PLL usually ranges from several hundreds to more than two thousand. A tracking jitter problem arises from this large multiplication factor as shown in Fig. 2.13. Assuming that the multiplication factor is N, the oscillator resolution is Δ, and the initial period of output clock is T. The divided clock are well aligned with the input reference clock in the beginning, that is, skew(n)=0. After one reference cycle, the divided clock lags the reference clock. The timing skew occurs at this moment, that is, skew(n+1)=δ.

Afterward the oscillator will speed up through control mechanism in order to catch up the reference clock. Assuming that the period of output clock is adjusted to T-Δ, the timing skew between divided and reference clock becomes skew(n+2)=δ-(N*Δ) after another reference cycle. Since the multiplication factor N is a large number, this accumulated timing skew will not be a small quantity. The loop will emerge unstable owing to the big timing skew unless the oscillator resolution is sufficient small to minimize the timing skew. However, it is never easy to realize an extremely high resolution oscillator as the multiplication factor increases.

For instance, assuming the multiplication factor N equals 2000, and the oscillator resolution equals 1ps. As a result, the timing skew maybe as large as 2ns. In

order to keep the timing skew smaller than 1ns, an oscillator with 0.5ps resolution must be equipped. It is not easy to implement such a high resolution oscillator by current technology.

Fig. 2.13. A tracking jitter problem of large multiplication factor

This timing skew, namely tracking jitter, is strongly related to the multiplication factor as reported in reference [28] as shown in Fig. 2.14. The period jitter can be maintained under 5 percent of the output period even with 4096 multiplication factor.

Oppositely, the tracking jitter is over 100 percent when the multiplication factor is larger than 512. Here we propose a DCO dithering method to enhance the equivalent DCO resolution and tracking ability without degrading jitter performance.

Fig. 2.14. Jitter versus multiplication factor at fixed 240 MHz output [28]

2.3.2 The Effect of Cycle Slipping Phenomenon

The second issue is the effect of cycle slipping phenomenon [29-31]. The cycle slipping in PLL is a statistical nonlinear phenomenon. It occurs when a large frequency error is presented to the phase detector and the loop bandwidth is not sufficient to correct for it in a fast time frame. The phase detector then causes a temporary correction in the opposite direction than it should. The result of this phenomenon is extra time required for the phase detector to lock to the correct frequency. The net impact of cycle slipping is that it increases lock time as shown in Fig. 2.15. The cycle slipping occurs generally in situations where the comparison frequency is very high relative to the loop bandwidth. In general, if the comparison frequency exceeds about 100 times the loop bandwidth, cycle slipping begins to emerge as a problem.

Fig. 2.15. The impact of cycle slipping on lock time

The cycle slipping phenomenon can be explored from the characteristics of a conventional three-state phase detector. The three-state phase detector (PD) was firstly reported in reference [32], it is also a phase/frequency detector (PFD). The conventional three-state phase detector architecture is illustrated in Fig. 2.16(a). It consists of two D-flip-flops (DFF) and a NAND gate. The NAND gate is employed to provide a self-reset path. The state diagram is shown in Fig. 2.16(b). Initially, the

phase detector is in Init state and both UP and DN signals are low. When one of the PFD inputs rises, the corresponding output becomes high. The state of the finite-state machine (FSM) moves from an initial Init state to an Up or Down state. The state is held until the second input goes high, which in turn resets the circuit and returns the FSM to the initial state.

Fig. 2.16. (a) Conventional three-state phase detector architecture (b) State diagram of the three-state phase detector

The characteristic of PFD is ideally linear for the entire range of input phase difference from 2π to -2π as shown in Fig. 2.17(a). However, due to the finite delay of the reset path, the linear range is less than 4π. This nonideal linear PFD characteristic is shown in Fig. 2.17(b). There are gain inversion regions near ±2π.

The effect appears as a negative output for phase difference approaching ±2π. The width of the gain inversion region depends on the reset path delay, which is determined by the propagation delay of logic gates. The PFD nonideal behavior due to nonzero reset path delay is shown in Fig. 2.18. The CLK_ref leads the CLK_div that activates an UP signal. As the input phase difference approaches 2π, the next leading edge CLK_ref arrives before the DFFs are reset due to the nonzero reset path delay. The reset signal RB overrides the new CLK_ref edge and does not activate the UP signal. The subsequent CLK_div edge activates a DN signal, but it is wrong information. During acquisition, the frequency will not monotonically approach

lock-in range because the nonideal PFD gives the wrong information periodically.

The acquisition process slows by how often the wrong information occurs. If the reset path delay equalsπ, i.e. in high frequency operation, the PFD outputs the wrong information half the time and, thus, fails to acquire frequency lock unconditionally.

In this design, a 2-cycle frequency search method cooperating with a new PFD structure can prevent the cycle slipping occurrence.

Fig. 2.17. (a) Ideal linear PFD characteristic (b) Nonideal linear PFD characteristic

Fig. 2.18. PFD nonideal behavior due to nonzero reset path delay

2.3.3 The Impact of Hsync Jitter Injection

Another design issue is the impact of Hsync jitter injection. The PLL reference clock source in the video display system is very different form the other electronic systems. Unlike most PLL reference clock coming from a precise oscillator, the Hsync signal is a mediocre quality clock source in the video display system. The following is the clock jitter measurement data of three commercial graphic cards [25].

The jitter may range from several hundred pico-seconds to more than one nano-second. The injection of such a large jitter into the PLL will cause the stability problem. The output jitter may cause spatial instability in the displayed image.

Furthermore, an overmuch Hsync jitter will probably make the PLL unable to be locked. This malfunction will cause the image to be distorted seriously.

Besides these previously described design issues, the low refresh rate induced jitter, nonzero PFD dead zone, DCO resolution limitation, and working temperature variation are also important considerations of the PLL clock generator for video application circuit design.

Chapter 3

ADPLL Clock Generator Circuit Design

3.1 The Proposed ADPLL Architecture

The proposed cell-based ADPLL clock generator architecture is shown in Fig.

3.1. The ADPLL consists of phase/frequency detector (PFD), control unit (CTRL), digital-controlled oscillator (DCO), phase adjustment circuit (ADJ), and clock counter (DCO_CNT). An RSTB control signal enables the ADPLL circuit. The MULTI signals are used for programming the clock divider. The input reference clock is CLK_IN, which comes from Hsync. The output clock CLK_DCOO and CLK_DIVO are generated high frequency pixel clock and low frequency divided clock respectively.

The digital control unit is the core of this ADPLL clock generator. It issues commands to control all the other functional blocks. The proposed PFD is a modified three-state phase/frequency detector without self-reset path. It compares the phase relation between the input reference clock and the feedback divided clock, and then sends the comparison results, IS_UP and IS_DN, back to the control unit. The control unit will speed up or slow down the DCO according to the comparison results. The proposed DCO circuit is a four-tuning-stage ring oscillator with enable part. The frequency of DCO is decided by the digital control words TUNE1, TUNE2, TUNE3, and TUNE4 from the control unit. The phase adjustment circuit is a fine delay line to deskew channel delay according to the external phase selection signal, ADJUST. The clock counter acts as a frequency divider. It receives the DCO clock and feeds back a