The Impact of Hsync Jitter Injection

Another design issue is the impact of Hsync jitter injection. The PLL reference clock source in the video display system is very different form the other electronic systems. Unlike most PLL reference clock coming from a precise oscillator, the Hsync signal is a mediocre quality clock source in the video display system. The following is the clock jitter measurement data of three commercial graphic cards [25].

The jitter may range from several hundred pico-seconds to more than one nano-second. The injection of such a large jitter into the PLL will cause the stability problem. The output jitter may cause spatial instability in the displayed image.

Furthermore, an overmuch Hsync jitter will probably make the PLL unable to be locked. This malfunction will cause the image to be distorted seriously.

Besides these previously described design issues, the low refresh rate induced jitter, nonzero PFD dead zone, DCO resolution limitation, and working temperature variation are also important considerations of the PLL clock generator for video application circuit design.

Chapter 3

ADPLL Clock Generator Circuit Design

3.1 The Proposed ADPLL Architecture

The proposed cell-based ADPLL clock generator architecture is shown in Fig.

3.1. The ADPLL consists of phase/frequency detector (PFD), control unit (CTRL), digital-controlled oscillator (DCO), phase adjustment circuit (ADJ), and clock counter (DCO_CNT). An RSTB control signal enables the ADPLL circuit. The MULTI signals are used for programming the clock divider. The input reference clock is CLK_IN, which comes from Hsync. The output clock CLK_DCOO and CLK_DIVO are generated high frequency pixel clock and low frequency divided clock respectively.

The digital control unit is the core of this ADPLL clock generator. It issues commands to control all the other functional blocks. The proposed PFD is a modified three-state phase/frequency detector without self-reset path. It compares the phase relation between the input reference clock and the feedback divided clock, and then sends the comparison results, IS_UP and IS_DN, back to the control unit. The control unit will speed up or slow down the DCO according to the comparison results. The proposed DCO circuit is a four-tuning-stage ring oscillator with enable part. The frequency of DCO is decided by the digital control words TUNE1, TUNE2, TUNE3, and TUNE4 from the control unit. The phase adjustment circuit is a fine delay line to deskew channel delay according to the external phase selection signal, ADJUST. The clock counter acts as a frequency divider. It receives the DCO clock and feeds back a

multiplication factor, MULTI. The details of these functional blocks will be presented in the next sections. The simulation waveform of the proposed ADPLL system is shown in Fig. 3.2.

Fig. 3.1. The proposed ADPLL clock generator architecture

Fig. 3.2. The simulation waveform of the proposed APDPLL

3.2 Phase/Frequency Detector

The proposed PFD is a modified three-state PFD without self-reset path as shown in Fig. 3.3. When feedback divided clock CLK_DIV lags input reference clock CLK_IN, the UP signal goes to logic high and DN remains low. Then, the control signal PD_GET goes high to latch the comparison results. Thus the IS_UP state is asserted. Oppositely, when CLK_DIV leads CLK_IN, the IS_DN state is asserted.

Afterward the control signal PD_RB goes low to reset the PFD and then goes high to prepare for receiving the arrival of input signals next time. The timing diagram of the proposed PFD is shown in Fig. 3.4. The generation of the control signals will be presented in section 3.5. By the way, the only information sent to the control unit is the phase difference polarity not magnitude.

Fig. 3.3. The schematic of the proposed PFD

Fig. 3.4. The timing diagram of the proposed PFD

An important performance index of PFD is dead-zone. The so-called dead-zone is a very small region of PFD characteristics where the phase difference is around 0.

The PFD cannot detect the phase relation of input reference and feedback divided clocks correctly within this region. In other words, the PFD is unable to generate correct information when the two input clock phases are very close. The cause of dead-zone comes from the response time of the devices. The dead-zone usually ranges from several to several tens pico-seconds. There have been plenty studies of PFD dead-zone problem published [33-48]. Most of them use dynamic logic techniques to improve the dead-zone. However, it cannot apply to a low refresh rate ADPLL.

The simulation result of the proposed PFD is shown in Fig. 3.5. The phase difference between CLK_IN and CLK_DIV is 1ps. The PFD can output correct information in different simulation conditions. The dead-zone of the proposed PFD is 1ps according to this simulation result.

Fig. 3.5. The simulation result of the proposed PFD

Note: The divided clock lags reference clock by 1ps. The PFD can latch correct information in different simulation conditions: (A)TT/1.0V/40°C (B)SS/0.9V/120°C (C)FF/1.1V/-40°C (D)FNSP/1.0V/40°C (E)SNFP/1.0V/40°C

3.3 Digital-Controlled Oscillator

The proposed DCO is a four-tuning-stage ring oscillator with enable part as shown in Fig. 3.6. The four stages are: (1)successive approximation register (SAR), (2)linear (LIN), (3)first DCO dithering (DIT1), and (4)second DCO dithering (DIT2).

The first three stages are utilized as frequency searching, and the last stage is utilized as phase tracking. These tuning stages are governed by the control unit. The control flow chart will be presented in section 3.5.

Fig. 3.6. The schematic of the proposed DCO

The most basic requirement of the DCO circuit is the delay line range, that is, the DCO operation frequency range has to cover all the display modes. In order to meet all the display modes from VGA to UXGA, the DCO frequency range must cover 25MHz (40ns) to 230MHz (4.34ns) under different operation conditions. Hence the DCO tuning range must be more than 35.66ns (40ns-4.34ns=35.66ns). The proposed DCO frequency range is dominated by the tuning range of the first SAR stage. The schematic of the proposed SAR tuning stage is shown in Fig. 3.7. This stage is used to achieve fast frequency search. It is composed of 12 cascaded binary-weighted delay paths controlled by TUNE1[11:0]. Each delay cell consists of a multiplexer and a different weighted delay path. The control signal decides which path to be selected, thus one of 4096 delay path combinations could be chosen

through the 12-bit control word. The simulation result of each SAR stage tuning range corresponding to the control code TUNE1[11:0] is shown in table. 3.1. The minimum tuning range in fast case is 40.118 ns. It can be seen that the proposed DCO can apply to the all the display modes.

Fig. 3.7. The schematic of the proposed SAR tuning stage

Table. 3.1. The tuning range simulation result of the SAR stage

The linear tuning stage is shown in Fig. 3.9. The purpose of this linear stage is to acquire a more accurate frequency after SAR stage. It consists of 8 delay cells, and

each cell is composed of a buffer and two digitally controlled varactors (DCV) [49,50]. The DCV array is controlled by the 16-bit thermometer code which decoded from TUNE2[3:0]. The simulation result of this linear stage delay time corresponding to the control word is listed in table 3.2. It can be seen that the DCV cell can achieve 6ps high resolution in worst case.

Fig. 3.8. The schematic of the proposed linear tuning stage

Table 3.2. The tuning range simulation result of the linear stage

Next, the DCO dithering stages are employed to minimize the frequency error and tracking error. Each stage is controlled by one single bit to alter the delay time.

The control mechanism will be presented in section 3.5. The tuning range simulation results of the DCO dithering stages is listed in table 3.3. The tuning resolutions of the third and fourth stages are 168ps and 17ps respectively in worst case according to the simulation result. Because there is tradeoff between DCO resolution and tracking ability, a very small tuning step of the fourth stage is not necessary.

Fig. 3.9. The schematic of the proposed DCO dithering stages

Table. 3.3. The tuning range simulation result of the DCO dithering stages

In short, the simulation result of the overall DCO operation range is shown in table 3.4. The maximum DCO frequency is 237MHz (4212ps) in slow case, and the minimum DCO frequency is 23.8MHz (41848ps) in fast case. Thus, the DCO can fully support all the display modes from VGA to UXGA.

Table. 3.4. The simulation result of the overall DCO operation range

3.4 Phase Adjustment Circuit

The purpose of the phase adjustment circuit is to deskew channel delay such that the sampling clock can be fine tuned to the best timing. It is a 16-step adjustable delay line controlled by ADJUST[3:0]. It is composed of 16 delay stages and a thermometer decoder, and each delay stage consists of a NAND and MUX to decide which path to be chosen [51,52]. The adjustment step is 410ps in slow case according to the simulation result listed in table 3.5.

Fig. 3.10. The schematic of the proposed phase adjustment circuit

Table 3.5. The simulation result of the proposed phase adjustment circuit

3.5 Control Unit

The control unit is the core of the ADPLL clock generator. It receives the comparison result of PFD and modifies the DCO control code until the loop is locked.

The detail state and timing diagrams will be presented in this section.

3.5.1 State Diagram of Control Unit

The state diagram of the control unit is shown in Fig. 3.11. The control algorithm will influence the frequency lock time and tracking performance of the loop.

Fig. 3.11. The state diagram of control unit

The first state is successive approximation register (SAR) tuning stage. The default values of the SAR control bits are all zeroes except the first bit, i.e.

TUNE1[11:0]=12’b1000_0000_0000 (refer to Fig. 3.7.). The control code is scanned bit by bit from the most significant bit (MSB) to the least significant bit (LSB). A counter is employed to record the current SAR step. If the PFD returns IS_UP, the

control unit resets the current SAR control bit to logic 0 and sets next bit to logic 1 in order to speed up DCO frequency. In another situation, if the PFD returns IS_DN, the control unit keeps the current SAR control bit as logic 1 and sets the next bit to logic 1 in order to slow down the DCO frequency. By means of the SAR algorithm and binary-weighted DCO design, the fast frequency search can be achieved owing to the variable loop bandwidth. The loop bandwidth is quite high in the beginning and relatively small in the end of SAR state. The frequency search time depends on how many bits is the SAR control code. For instance, it takes n steps for an n-bits SAR control code. It takes 12 steps to finish the SAR frequency search process in the proposed chip.

The second state is linear (LIN) tuning stage. The purpose of this stage is to acquire a more accurate frequency after SAR stage. Thus the tuning resolution must be much higher than the first stage. The default values of the LIN control bits are half zeroes and half ones through a thermometer decoder, that is TUNE2[3:0]=4’b1000 while C[15:0]=16’b0000_0000_1111_1111 (refer to Fig. 3.8.). If the PFD returns IS_UP, the control unit decreases the LIN control code, which asserts less ones, to speed up the DCO frequency, and vice versa. The frequency search time is proportional to the width of control code. It equals 2^n-1 steps for an n-bits LIN control code. As a result, it takes 8 steps to complete the LIN frequency search process in the proposed chip.

The third state is DCO dithering (DIT1) tuning stage. The control unit enters this stage as the PFD comparison result is changed. This means that the DCO frequency is quite close to the target frequency. This stage is intended to minimize the frequency error after the first two stages. Sometimes it is not possible to find a control code that exactly fulfils the multiple relations between input and output clock owing to the DCO resolution limitation. Therefore, the fraction-N PLL architecture is

introduced to enhance the tuning resolution and flexibility [55,56]. However, the multiple relations between input and output clocks are not fixed in different cycles.

The fractional-N architecture is not feasible in the video application. Another solution to enhance the tuning resolution is the DCO dithering method [54]. The concept of DCO dithering is to alter the output clock period during one reference cycle and keep the multiple relation as shown in Fig.3.12. The period of CLK_DCO is controlled by TUNE signal. When TUNE is logic 1, the CLK_DCO is dithering to long period by increasing Δt whereΔt is the original DCO tuning resolution. From this figure, the DCO clock frequency keeps 10 times of the reference clock, and the period of the DCO clock is T₀+Δt/2 on average. It can be seen that the DCO resolution is thus doubled without an extremely high resolution DCO. The resolution enhancement level is determined by the frequency multiplication factor and how many cycles are dithered during one reference cycle. In the proposed design, a fractional and a step counters with binary search algorithm are exploited to decide how many DCO clock must be dithered. The frequency search time of this DCO dithering stage is determined by the width of the step counter. This stage ends up when the dithering step counter equals zero. For a n-bits counter, the binary search process takes n*2 steps. In the proposed design, the step counter is 10-bits, thus takes at most 20 steps to complete the frequency search process. As this DCO dithering stage finishes the frequency error is minimized and the PLL is locked to the desired frequency.

Fig. 3.12. The timing diagram of DCO dithering method

The final state is another DCO dithering (DIT2) stage. The behavior of this stage is similar to the first dithering stage. The PLL starts phase tracking when enters this stage. When the PFD returns IS_DN, more clocks are dithering as long period in order to realign with the reference clock. On the contrary, when the PFD returns IS_UP, fewer clocks are dithering as long period to catch up the reference clock.

3.5.2 Timing Diagram of Control Unit

The timing diagram of control unit is shown in Fig. 3.13. The state machine is in IDEL state during reset. When the reset signal RSTB releases and input reference clock activates, the state machine enters SAR, LIN, and DIT1 frequency search state sequentially. The frequency search states take 40 steps (12+8+20=40) to lock in the desired frequency. Because each frequency search step takes two reference cycles (this 2-cycle frequency compare method will be described thereafter), the frequency search process need totally 80 reference cycles to be finished. The PLL enters DIT2 phase tracking stage and the output signals CLK_DCOO and CLK_DIVO are activated once the frequency is locked. The detailed timing diagram of each state will be presented in the following.

Fig. 3.13. The timing diagram of control unit

The timing diagram of SAR frequency search state is shown in Fig. 3.14. When the first rising edge of reference clock CLK_ref comes, the DCO clock CLK_DCO is activated and the DCO counter dco_cnt starts up counting at timing (A). The dco_cnt keeps up counting until it equals M and then reset to 1 where M stands for the multiplication factor. The CLK_DIV goes high when dco_cnt equals 1 and goes low when dco_cnt equals M/8. Therefore, the duty cycle of divided clock CLK_DIV is 12.5% which is similar to Hsync. A sequence of commands is generated by CLK_DCO after each CLK_ref depending on the state machine. Here, PFD_EN command is activated to enable PFD at timing (B). After that, the second rising edge of CLK_ref arrives and another sequence of commands is generated. This time, a PFD_GET command is issued to latch the PFD comparison result at timing (C), and then a PFD_DIS command is issued to reset the PFD at timing (D) because the PFD has no self-reset path. In this example, a IS_UP information is latched because the divided clock CLK_DIV lags the reference clock CLK_ref. Next, a DCO_DIS command is activated to disable DCO thus stops DCO clock, and a DCO_TUNE command is activated to modify the DCO control code at timing (E). In this example, the divided clock lags the reference clock. The fifth bit of DCO control code TUNE1 is set to logic 0 and the fourth bit is set logic 1 in order to speed up DCO. Finally, the next rising edge of CLK_ref comes and starts another frequency search step at timing (F). This is the operation of 2-cycle frequency compare method.

It is worthy of noticing that this 2-cycle frequency compare method benefits in two important points. First, there is no accumulation error during frequency search process because DCO clock realigns with reference clock at the beginning of each search step. Consequently, the loop can acquire the target frequency correctly without the disturbance of the accumulation error. Second, the cycle slipping phenomenon is eluded in co-ordination with the proposed PFD because the PFD never operates in the

gain inversion region. Therefore, the loop can lock to the target frequency quickly.

Fig. 3.14. The timing diagram of SAR frequency search state

Note: (A) Start frequency search and enable DCO at first reference clock (B) Enable PFD

(C) Latch PFD comparison result (D) Reset PFD

(E) Disable DCO and tune DCO SAR control code (F) Start next frequency search step and enable DCO

The timing diagram of LIN frequency search state is shown in Fig. 3.15. The 2-cycle frequency compare operation is similar to SAR stage except that an extra PFD_JUDGE command is activated after the second rising edge of CLK_ref to detect whether the PFD polarity changes, either from IS_UP to IS_DN or from IS_DN to IS_UP, at timing (C). If the PFD polarity changes, a PFD_CHANGE signal is asserted to denote the end of LIN stage. In this example, the divided clock leads the reference clock. The control code TUNE2 is modified from 4’b1000 to 4’b1001 to slow down the DCO clock.

Fig. 3.15. The timing diagram of LIN frequency search state

Note: (A) Start frequency search and enable DCO at first reference clock (B) Enable PFD

(C) Detect PFD status transition (D) Latch PFD comparison result (E) Reset PFD

(F) Disable DCO and tune DCO LIN control code (G) Start next frequency search step and enable DCO

The timing diagram of DIT1 frequency search state is shown in Fig. 3.16. The operation is a little different from the previous stages. There are two counters used to calculate how many DCO clocks to be dithered in order to minimize the frequency error. One is the fractional counter fra_cnt3 which records how many clocks to be dithered, and its default value is M/2. The DCO dithering control signal is low when DCO counter reset to 1, and the control signal goes high while DCO counter equals fractional counter. The DCO clock is dithering to long period when control signal is

The timing diagram of DIT1 frequency search state is shown in Fig. 3.16. The operation is a little different from the previous stages. There are two counters used to calculate how many DCO clocks to be dithered in order to minimize the frequency error. One is the fractional counter fra_cnt3 which records how many clocks to be dithered, and its default value is M/2. The DCO dithering control signal is low when DCO counter reset to 1, and the control signal goes high while DCO counter equals fractional counter. The DCO clock is dithering to long period when control signal is