Chapter 1 Introduction
1.3 Thesis Organization
This thesis describes a voltage mode pulse transmitter, a pulse receiver, and an on-chip transmission line. In chapter 2, we study the background of the high-speed serial link interface and the AC coupled communication. Some typical structures are also introduced in this chapter. In chapter 3, the on-chip pulse signaling is present. An
Transmitter Receiver
Timing Recovery
Data out Data in
Transmission Line
analysis of on chip pulse signaling and an on-chip differential transmission are discussed. Chapter 4 shows the design of the pulse transmitter and the pulse receiver.
The experimental results and conclusions are addressed in the last two chapters. The results are also compared with some prior works.
Chapter 2
Background Study
System on chip (SOC) is the trend of today’s IC design and the high speed interface [2] [3] between chip modules is an important design issue. In the electrical industry, positive-referenced emitter-coupled logic (PECL), current mode logic (CML), and low voltage differential signaling (LVDS) are the structures commonly used in high speed link interface design. However, a current source is required to produce the IR drop that makes the signal swing. The current source not only consumes the dynamic power but also the static power. In order to save more power, AC coupled method is introduced because it only consumes the dynamic power by coupling pulse mode data. Besides, with the growing of chip size, on-chip interconnect is also getting more attention as on-chip interconnect is becoming a speed, power and reliability bottleneck for the system. In this chapter, we will briefly overview the background of high-speed serial link interface and AC coupled communication. Of course, some typical structures are also introduced in this chapter.
2.1 High Speed Link Interface
High speed links for digital systems are widely used in recent years. In the computer systems, the links usually appear in the processor to memory interfaces and
in the multiprocessor interconnections. In the computer network, the links are used in the long-haul interconnect between far apart systems and in the backplane interconnect within a switch or a router. Fig 2.1 is a generalized structure of a high speed serial link [4]. It consists of a transmitter, a transmission line, and a receiver.
The transmitter side serializes the parallel data and delivers the synchronized data into the transmission line. Timing information is embedded in this serial data, which is sent over a single interconnect. The receiver side receives the serial data and recovers its timing. Then, the serial data returns to the parallel one.
Fig. 2.1 A generalized model of a serial link
As the demand for high-speed data transmission grows, the interface between high speed integrated circuits becomes critical in achieving high performance, low power, and good noise immunity. Fig.2.2 shows the typical structure of a high speed interface. The interface usually appears in the chip-to-chip high speed data communication [5]. Three commonly used interfaces are PECL, CML, and LVDS.
The signal swing provided by the interface depends on the IR drop on the termination resistance, and that decides the power consumption. The signal swing of most designs is in the range of 300mV to 500mV.
Fig. 2.2 High speed interface
Serial to
2.1.1 PECL Interface
PECL [6] is developed by Motorola and originates from ECL but uses a positive power supply. The PECL is suitable for high-speed serial and parallel data links for its relatively small swing. Fig. 2.3 (a) shows the PECL output structure. It consists of a differential pair that drives source followers. The output source follower increases the switching speeds by always having a DC current flowing through it. The termination of PECL output is typically 50Ω that results in a DC current and makes Vop and Von to be (Vdd-Vov). The PECL has low output impedance to provide good driving capability.
Fig.2.3 (b) shows the input structure of PECL. It consists of a differential current switch with high input impedance. The common mode voltage is around (Vdd-IR) to provide enough operating headroom. Besides, decoupling between the power rails is required to reduce the power supply noise.
Fig. 2.3 (a) output structure of PECL (b) input structure of PECL
2.1.2 CML Interface
CML [6] [7] is a simple structure for high speed interface. Fig. 2.4 (a) shows the output structure of the typical CML which consists of a differential pair with 50Ω drain resistors. The signal swing is supplied by switching the current in a common-source differential pair. Assuming the current source is 8mA typically, with the CML output connected a 50Ω pull-up to Vdd, and then the single-ended CML output voltage swing is from Vdd to (Vdd−0.4V). That results in the CML having a differential output swing of 800mVpp and a common mode voltage of (Vdd–0.4V). Fig.
Von
2.4 (b) shows the CML input structure which has 50Ω input impedance for easy termination. The input transistors are source followers that drive a differential-pair amplifier.
Fig. 2.4 (a) output structure of CML (b) input structure of CML
In conclusion, the signal swing provided by the CML output is small and that results in low power consumption. Besides, the termination minimizes the back reflection, thus reducing high-frequency interference. Table 2.1 [6] summarizes the electrical characteristics of a typical CML.
Table 2.1 Electrical characteristics of the CML [6]
Parameter min typ max Unit
Differential Output Voltage 640 800 1000 mVpp
Output Common Mode Voltage Vdd-0.2 V
Single-Ended Input Voltage Range Vdd–0.6 Vdd+0.2 V Differential Input Voltage Swing 400 1200 mVpp
2.1.3 LVDS Interface
LVDS [6] [8] has several advantages that make it widely used in the telecom and network technologies. The low voltage swing leads to low power consumption and makes it attractive in most high-speed interface. Fig. 2.5 (a) shows the output structure of LVDS. The differential output impedance is typically 100Ω. A current
Von
steering transmitter provides Ib (at most 4mA) current flowing through a 100Ω termination resistor. The signal voltage level is low which allows low supply voltage such as 2.5V. The input voltage range of the LVDS can be form 0V to 2.4V and the differential output voltage can be 400mV. These allow the input common mode voltage in the range from 0.2V to 2.2V. Fig. 2.5 (b) shows the LVDS input structure.
It has on-chip 100Ω differential impedance between Vip and Vin. A level-shifter sets the common-mode voltage to a constant value at the input. And a Schmitt trigger with hysteresis range relative to the input threshold provides a wide common-mode range.
The signal is then send into the following differential amplify for receiver usage.
Table 2.2 [6] summarizes the LVDS input and output electrical characteristic.
Fig. 2.5 (a) output structure of LVDS (b) input structure of LVDS Table 2.2 Electrical characteristics of LVDS [6]
Parameter Symbol Cond. min typ max Unit
Output high voltage VOH 1.475 V
Differential Output Impedance 80 120 Ω
Output Current Short
together 12 mA
Output Current Short to
Gnd 40 mA
Differential Input Voltage |Vid| 100 mV Input Common-Mode Current Input
Vos=1.2V 350 uA
Hysteresis Threshold 70 mV
Differential Input Impedance Rin 85 100 115 Ω
2.2 AC Coupled Communication
2.2.1 AC coupled communication
The AC coupled interface [9] [10] [11] uses pulse signal to transmit data. It has the advantage of less power consumption. The AC component actually carries all the information of a digital signal and thus an AC coupled voltage mode driver can be used to improve the power consumption because only the dynamic power is presented.
Coupling capacitor acts like a high-pass filter that passes the AC component of the data to the data bus.
(a)
(b)
Fig. 2.6 (a) AC coupled communication [12] (b) pulse waveform in transmission line GND
300mV VDD
GND VDD
1ns
Fig. 2.6 (a) shows the AC coupled communication [12]. The transmitter (in chip 1) and the receiver (in chip 4) are connected to the data bus through an on-chip coupling capacitor Cc at pad. Both end of the data bus are terminated by the impedance matching resistors Z0 with termination voltage Vterm. Fig 2.6 (b) indicates the waveform of the pulse communication. The input full swing data sequence is coupled to pulse form by the capacitor at the transmitter output. The amplitude of the pulse signal is roughly 300mV at the data rate of 1Gbps. The receiver obtains the pulse mode data through the coupling capacitor and then amplifies the decayed signal to full swing.
2.2.2 Typical pulse transmitter / receiver
Pulse signaling [15] [16] typically uses a voltage-mode transmitter [17] as shown in Fig. 2.8. The transmitter output is connect to a coupling capacitor and then to the transmission line. Return impedance matching at the transmitter output is provided by the termination resistor. The voltage mode transmitter provides a full swing as well as high edge rate output to drive the transmission line. Without DC current consumption, the voltage mode transmitter consumes less power than a current mode transmitter.
Fig. 2.7 voltage mode transmitter
Fig 2.9 (a) shows the pulse receiver proposed by Jongsun Kim in 2005 [12]. The enable function is design for saving power if the circuit is in the off mode. The equivalent circuit with enable on is shown in Fig. 2.9 (b). The cross-couple structure
not only senses the pulse signal but also provides the latch function to transform the pulse signal into NRZ data.
(a)
(b)
Fig. 2.8 (a) pulse receiver (b) equivalent circuit with enable on
Fig 2.10 shows another low swing pulse receiver proposed by Lei Luo in 2006 [14]. The diode connected feedback M1~M4 limits the swing at the out of inverter.
Meanwhile, M5 also M6 provide a weak but constant feedback to stabilize the bias voltage, making it less sensitive to the input pulses. Source couple logic M7~M9 further amplifies the pulse and cross-coupled M11 & M12 serves as a clock free latch to recover NRZ data. In addition, a clamping device M10 limits the swing of long 1’s or 0’s and enable latch operation for short pulse which improves the latch bandwidth.
The structure is able to receive pulse of the swing as small as 120mVpp.
Fig. 2.9 low swing pulse receiver
Chapter 3
On-Chip Pulse Signaling
This chapter introduces the on-chip pulse signaling. It includes the pulse signaling mathematic model and the geometry of the on-chip differential transmission line. On-chip transmission line [18] [19] has a large parasitic resistance. The resistance is frequency dependent due to the skin effect. The large parasitic resistance and parasitic capacitance make the signal decay greatly [20]. Thus, a wide line is required for long distance and high-speed signal transmission. However, the wider line and space between lines require more layout area. That will increase the costs of the SOC. That is why a low cost and large bandwidth transmission line is desired.
Moreover, the characteristic impedance of transmission line is also discussed in this chapter. Theoretically, impedance matching among the transmitter end, the receiver end, and the transmission line is required. That can prevent the signal from reflecting in the transmission line. In this thesis, a single end termination is implemented. The single termination method can guarantee the signal reflects at most once. The designed termination impedance is 75Ω for less attenuation. The width, space, and length of the transmission line are 2.3um, 1.5um, and 5000um respectively. The transmission is implemented with Metal 6 and Metal 5 of TSMC RF013um technology.
3.1 Pulse Signaling Scheme
Fig. 3.1 shows the on-chip pulse signaling scheme. The transmitter and the receiver are coupled to the on-chip transmission line through the coupling capacitor Cctx and Ccrx. Transmitter and receiver ends of the data bus are terminated by the impedance Ztx and Zrx respectively with the terminated voltage Vterm. Furthermore, the transmission line acts like the distributed RLC that decays the transmitted data. The coupling capacitor makes it a high-pass filter that transmits the transient part of the input data. The DC component is blocked. The pulse signaling method is base on the fact that the AC component actually carries all the information of a digital signal. The DC component is treated as redundant. In this way, the pulse data acts as return to zero signaling (RZ). In contrast to non-return to zero (NRZ) signaling, pulse signaling has been used to reduce the power consumption by only dissipating the dynamic power at transient time.
Fig. 3.1 Pulse signaling scheme
In Fig 3.1, full swing data is fed into the transmitter input. The transmitted data in the transmission line is a pulse coupled by the coupling capacitor at the transmitter output. After long distance of transmission, the received pulse is coupled to the
On-Chip Transmission Line
Cascaded Driver Hysteresis Receivers
Full Swing
Coupling
Pulse Coupling
Pulse
Full Swing
hysteresis receiver by the coupling capacitor as well. The receiver end biases the pulse to the DC common mode voltage of the hysteresis receiver. After that, the hysteresis receiver transfers the RZ pulse data to NRZ full swing data.
3.2 On-chip pulse signaling analysis
Fig 3.2 (a) defines the on-chip pulse signaling model and Fig 3.2 (b) is the corresponding transient response of the transmitter. Let Zt be the characteristic impedance of the transmission line, Ztx and Zrx the termination resistances at the transmitter end and receiver end, Cctx and Crtx the coupling capacitors, Cd and Cg the parasitic capacitance at transmitter output and receiver input respectively. The transfer function from transmitter output (A) to near end transmission line (B) is
tx t Equation (3.1) shows the high-pass characteristic and that HAB(s) is dominated by
tx t ctx d
(Z //Z )C C in high frequency. In other words, large coupling capacitor and termination resistance are better for transferring the pulse signal. Moreover, the transfer function from the near end (B) to the far end C) is and the transfer function becomes
.
Equation (3.2) shows the channel bandwidth is roughly 1/RchCch. The parasitic resistance and capacitance of the transmission line limits the channel bandwidth.
Furthermore, the transfer function from the far end (C) to the receiver input (D) is
g
Equation (3.3) shows that the receiver pulse is proportional to the value of coupling capacitor (Ccrx ).
Fig. 3.2 (a) On-chip pulse signaling model (b) Transient response of the transmitter Node A
The step response is important in analyzing the pulse signaling. A step input voltage at node A results in a transient on node C. Transforming a square wave into a short triangular pulse wave on the transmission line. The amplitude (Vp) becomes
p eff c
V = R I tx t cdVA
= (Z //Z )C
dt (3.4) and the voltage value at node B is
eff eff Equation (3.4) shows that the amplitude of the pulse is proportional to three parts: the equivalent value of the termination resistance parallel to the characteristic resistance, coupling capacitance, and the slew rate at the transmitter output. As illustrated in Fig 3.2 (b), the transmitter needs to provide a large amplitude value of pulse signal for the decay in the transmission line. However, after the transition time, the transmitted waveform becomes steady and the coupling pulse decays according to the RC time constant. The pulse width roughly equals to the rise time during the pulse transition plus the RC decay time. If the amplitude is too large, it creates the pulse tail and that leads to the ISI effect. This ISI effect not only limits the communication speed but also increases the jitter at the receiver end. In other words, large coupling capacitance and large termination resistance are good for transferring the pulse signal but that also create the ISI issue. In this thesis, we bring up an equalization method to reduce the ISI effect. The details will be discussed in the chapter 4.
3.3 On-Chip Differential Transmission Line
3.3.1 Mode of Transmission Line
As the wire cross-section dimension becomes smaller and smaller due to the technology scaling down and the wire length increases due to growing in chip size, not only the capacitance but also the resistance of the wire becomes significant.
Besides, the wire inductance becomes important as well for the faster circuit operating speed and relatively lower resistance from the new technology. The current distribution inside the conductor changes as the frequency increases. This change is called the skin effect and that results in variations of resistance and inductance value.
Fig. 3.3 shows the on-chip transmission line. When ωL is comparable to R then the wire should be modeled as a distributed RLC network. The frequency dependent behavior of the transmission line decays the pulse signal in the channel and makes the amplitude too small to receive at the far end.
Fig. 3.3 On-chip transmission line as a distributed RLC transmission line
Fig. 3.4 (a) shows the proposed on-chip differential transmission line which is fabricated by TSMC 0.13µm RF technology. A co-planar transmission line is placed in Metal 6. Metal 5 below is reserved for ground shielding. A micro-strip structure is used in GSGSG placing, ‘S’ for signal and ‘G’ for ground. The ground path is not only for signal return but also for the ground shielding. The transmission line model is analyzed and extracted to build the distributed RLC parameters by PTM [21]. Fig. 3.4 (b) illustrates the cross section of the differential transmission line. The total length (l) of the line is 5mm. The line width (w) is 2.3µm and line-to-line space (s) is 1.5µm.
On-Chip Transmission Line
Characteristic Impedance Z0
Fig. 3.4 (a) Micro-strip structure and the parasitic effect (b) Cross section of the on-chip transmission line
3.3.2 Geometry Analysis of Transmission Line
Table 3.1 shows the data obtained from PTM. The dimension is obtained form the TSMC 013RF technology document. The thickness (t) of Metal 6 is 0.37µm, the height (h) from Metal 5 to Metal 6 is 0.45µm, and the dielectric constant (k) is 3.9.
The total parasitic RLC value divided by the total length of the transmission line obtains the parasitic RLC in unit length. The distributed parasitic parameters are Rul=25.85Ω/mm, Lul=1.74nH/mm, and Cul=306.70 fF/mm.
Table 3.1 Parasitic RLC of the on-chip transmission line
Dimension RLC ( 5mm ) RLC ( /mm )
Ccouple Ccouple Ccoupl Ccouple
S G S
Cc = 1255.44 fF Cg = 139.035 fF Ct = 1533.51 fF
According to the data mentioned above, the characteristic impeadance (Z0) of the transmission line is
0 ul ul The characteristic impedance of the designed differential transmission is 75Ω. Fig. 3.5 shows the relationship between the dimension of the transmission line versus its characteristic impedance. Fig. 3.6 also illustrates the relationship between the dimension of transmission line versus its parasitic Rtotal*Ctotal which is equivalent to the bandwidth of the line. These two figures tell that smaller width as well as spacing results in larger characteristic impedance value. From (3.1), we know that it is good for coupling pulse because the high pass characteristic. However, small width as well as spacing results in large parasitic Rtotal*Ctotal which makes the signal decay greatly.
On the contrary, wider width and spacing of the transmission line results in better frequency performance of the transmission line. But it also requires more layout area which increases the cost of SOC. The design of w=3.2µm and s=1.5µm meets the characteristic impedance of 75Ω. And there are three main reasons for this value.
Firstly, 75Ω of characteristic impedance makes the parasitic Rtotal*Ctotal < 2E-10 (Ω*F) which decay the signal roughly 18dB. Secondly, 75Ω is close to 77Ω which theoretically causes minimum attenuation. Thirdly, the values of the width and spacing reduce the layout area as well as the costs.
Fig. 3.5 Transmission line dimension vs. characteristic impedance
Fig.3.6 Transmission line dimension vs. parasitic Rtotal*Ctotal
40
5.0E-07 1.0E-06 1.5E-06 2.0E-06 2.5E-06 3.0E-06 3.5E-06 4.0E-06 T-Line Spacing (m)
T-Line Dimension (s,w) vs Characteristic Impedance (Z0)
1E-10
5.0E-07 1.0E-06 1.5E-06 2.0E-06 2.5E-06 3.0E-06 3.5E-06 4.0E-06 T-Line Spacing (m)
T-Line Dimension (s,w) vs Rtotal * Ctotal (Ω*F)
Chapter 4
5Gpbs Pulse Transmitter/Receiver Circuit Design
This chapter introduces the pulse transmitter and pulse receiver operating at 5Gbps. At the near end, we increase the termination resistance for better high-pass characteristics. The equalization circuit built in the transmitter also cuts the pulse tail and depresses the ISI effect as discussed in chapter 3.2. At the far end, three functions are required: biasing the received pulse to the common mode voltage of the receiver, amplifying the received pulse amplitude, and transferring the RZ pulse to NRZ data.
These functions are implemented by a self-bias and equalization circuit, an inductive peaking amplifier, and a non-clock latch. The following sections will discuss these circuits and their design methodology.
4.1 Pulse Transmitter Circuit
4.1.1 Voltage Mode Transmitter
In high-speed serial link design, the near end typically uses a current mode driver as discussed in Chapter 2, but the pulse signaling must use a voltage mode driver as
shown in Fig. 4.2 (a). The transmitter output is connect to a coupling capacitor (Cctx) and then to the on-chip transmission line. Return impedance matching at the transmitter output is provided by the termination resistances (Ztx). There are two advantages to use a voltage mode transmitter rather than a current mode one. First, the
shown in Fig. 4.2 (a). The transmitter output is connect to a coupling capacitor (Cctx) and then to the on-chip transmission line. Return impedance matching at the transmitter output is provided by the termination resistances (Ztx). There are two advantages to use a voltage mode transmitter rather than a current mode one. First, the