Chapter 4 5Gbps Pulse Transmitter / Receiver Circuit Design
4.2 Pulse Receiver Circuit
4.2.4 Non-clock Latch with Hysteresis
The non-clock latch transforms the RZ pulse into NRZ data. So that the recovered NRZ data can then be fed to a traditional clock and data recovery circuit to generate the receiver end clock to re-sample the NRZ data. Fig 4.15 illustrates the non-clock latch structure established from four inverters and Fig. 4.16 shows its schematic. Via and Vib are the differential inputs and Voa and Vob are their corresponding differential outputs. Two small size inverters are connected back to back at the differential output to generate the hysteresis range.
Fig. 4.15 Receiver end: Non-clock latch with hysteresis
As demonstrated in Fig. 4.16 and Fig. 4.17, when the input Via goes from logic high (H) to the trigger point (Vtrp-), the corresponding output Voa will goes from logic low (L) to the threshold point (Vth). If we let βp= μpC (W/L)ox pmin , βn=
nCox
μ (W/L)nmin (where µ is the mobility of transistor, Cox is the oxide capacitance, and (W/L) is the aspect ratio of the transistor). Then, the total current flows through the node Voa becomes
Where X is size of the input inverter and Y is the size of the back to back inverter pair.
With the following replacements:
1 p The trigger point can be solved
[ ] .
VTRP-= roots( A1 , A2 , A3 ) (4.8)
Fig. 4.16 Non-clock latch with hysteresis circuit
Take TSMC 013RF technology for example, for X = 3, Y = 1 , V = 1.2(V) , dd
2 p= 1.5166e - 3 (A/V )
β , βn= 1.8198e - 3 (A/V )2 , V = 403.817e - 3 (V) , and tp V = 403.596e - 3(V) , we can obtain the trigger point (tn VTRP-) of 0.5578V. The proper design of X and Y values makes the hysteresis range to filter out the incoming noise and the interference.
Fig. 4.17 Simulation of non-clock latch with hysteresis circuit
Fig. 4.18 Jitter from the receiver Data
Ideal Pulse
Over Peaking
Vp
Vp
Vp
Vp Jitter
Trigger Point Of Latch VTRP+
VTRP
-Voa
Via
VOL
VOH
Inductive peaking amplifier may over peak the pulse signal for some corner cases especially in the SS corner. This is because the resistance of the peaking cell will change and results in different peak ability. Fig 4.18 illustrates the circuit behavior of the pulse receiver. This over peaking behavior will contribute some jitter at the receiver end. However, the hysteresis range of the latch can solve this problem.
As long as the peaking amplitude is smaller than the hysteresis range, the latch can ignore the over peaking.
Chapter 5
Experiment
One prototype chip was designed in TSMC 013RF technology to verify the research ideas presented in previous chapters. The prototype chip contains a voltage mode transmitter, a 5mm long differential transmission line, and a pulse receiver.
Besides, in order to drive the large parasitic capacitance on the output pad, open drain output drivers are used for the receiver differential output. In this way, the 5Gbps high-speed data can be measured on the oscilloscope. The simulated peak-to-peak jitter at the pulse receiver output is 43.7ps. The die size of the chip is 884×644µm2 with the power consumption of 3.4mW at the transmitter end and 3.2mW at the receiver end.
5.1 Simulation Setup
A test chip is implemented in TSMC 013µm RF technology. The building block of the system is shown in Fig. 5.1. We apply a sequence of random data to the input of the voltage mode pulse transmitter. The data are transported in pulse mode through the coupling capacitor (Cctx) to the on-chip transmission line. As illustrated in Fig 5.1, the differential structure of the transmission line is built in Metal 6 and we use
Metal 5 as the shielding ground. In addition, the differential structure of the transmission line also has the shielding grounds in the arrangement of ‘GSGSG’
between signal paths. The differential scheme has higher immunity to reject noise and the shielding ground reduces the environmental interference as well as the crosstalk between signal lines. At far end, the pulse data is coupled to the hysteresis receiver by the coupling capacitors (Ccrx). The receiver then transforms RZ pulses signal to NRZ data.
Fig. 5.1 System Architecture
In order to drive a large parasitic capacitance of an output pad, open drain output drivers are used for receiver differential output as shown in Fig.5.2. The package of the chip is modeled as a pad (C=1pF) connected to a pin (C=1pF) on the printed circuit board through a pounding wire (L=2nH). Thus, the open drain circuit will introduce a current (Ics) from the outside-chip power supply. The current goes through the impedance matching resistor (50Ω) and drives the large parasitic capacitance on
O
5mm on-chip differential line with shielding ground
5Gpbs eye
G S G S G
Cross-section of T-Line
M5(G) M5(G)
the package. One oscilloscope with 100nF bypass capacitor connected to the pin is used to probe the signal at the chip output. Therefore, we can observe the eye diagram on the oscilloscope.
Fig. 5.2 Common source circuit connects to pad for output signal measurement
5.2 Experiment and Results
Fig. 5.3 shows the system simulation results. The transmitter end sends the differential pulse signal with an amplitude of 400mVpp. After a 5mm long on-chip transmission line, the pulse amplitude decays to 50mVpp at the receiver front end. The pre-amplifier stage amplifies the pulse amplitude to 400mVpp and fed it to the hysteresis latch. The latch then turns the RZ pulse signal into the full swing NRZ data.
After the open drain circuit as discussed in section 5.1, the oscilloscope can measure the received data with a swing of 240mVpp. Fig. 5.4 shows the eye diagrams at the receiver output in different process corners. The eye diagram of the receiver shows the peak-to-peak jitter is 43.7ps (0.218UI) in the TT case. The worse case takes place in SS corner and the jitter is 82.7ps (0.413UI).
Vpp= Ics x 50 Common Source (Open Drain)
Connect To PAD Ics
1pF 50Ω
Fig. 5.3 System simulation results
The proposed on-chip pulse signaling is implemented by National Chip Implement Center (CIC) in TSMC 013RF technology. The core area is 584.7µm×411.5µm including a transmitter of 96.1µm×57.8µm, a receiver of 80.1µm×52.1µm, and a 5mm long on-chip transmission line. The total area is 884µm×644µm as shown in Fig 5.5. Table 5.1 lists the chip summary. The power consumption of the transmitter is 3.4mW, and it is 3.2mW for the receiver at the data rate of 5Gbps.
400mVpp
~240mV Full Swing Rx after Pre-Amp
400mVpp
50mVpp Input Data
Tx Pulse
Rx Pulse
400mVpp
~240mV Full Swing Latch
Oscilloscope
Fig. 5.4 Corner simulation results
Table 5.1 Specification Table
Item Specification (unit)
Process TSMC 0.13µm RF
Supply Voltage 1.2V
Data Rate 5Gb/s / channel (at 2.5GHz)
BER <10-12
Coupling Caps Tx (280+140)fF ; Rx (240+5)fF
Link 5mm and 75Ω on chip micro-strip line
Jitter of receiver data (pk-to-pk) 43.7ps (0.218UI) Transmitter End Layout Area 57µm x96µm Receiver End Layout Area 52µm x78µm
Core Layout Area 884µm x644µm
Pulse Driver 3.402mW
Power dissipation Pulse Receiver 3.213mW
Total 6.615mW
TT 43.7ps (0.218UI)
FF 29.6ps (0.148UI)
FS 52.5ps (0.262UI)
SF 49.7ps (0.248UI)
SS 82.7ps (0.413UI)
Fig. 5.5 Layout
Table 5.2 lists the comparison of the pulse signaling and other on-chip communications. Our work uses TSMC 013RF technology to implement an on-chip 5Gbps pulse signaling. The total communication distance is 5mm with a differential transmission line of width in 2.3µm and line-to-line spacing in 1.5µm. The line consumes small area overhead as compares to other on-chip differential lines [22]
[23]. Compared to the twisted differential wire method [24], our work uses a wider width as well as the wider line-to-line space. But the twisted differential wire method has only 40mVpp voltage swing at the far end. However, our work has full swing data at receiver output and that can be used for further receiver end usage. The power consumption of the transmitter in our work is 0.68pJ/bit and the total power is 1.32pJ/bit. Our work is the lowest in power consumption.
5mm On-Chip Differential Transmission Line
Table 5.2 Comparison of high speed data communication
Communication Chip-to-chip On-chip On-chip
Year 2005 [12] 2006 [14] 2005 [22] 2006 [23] 2006 [24] This work Method Signaling Pulse SignalingPulse Differential
T-Line Technology 0.1µm 0.18µm 0.18µm 0.18µm 0.13µm 0.13um
Data rate 1Gbps 3Gbps 4Gbps 5Gbps 3Gbps 5Gbps
T-Line (µm) - - w=4.0
The whole measurement environment is shown in Fig. 5.6. We use a N4901B Serial BERT to generate 5Gbps random data and send that into the chip. The data pass through the pulse transmitter, on chip transmission line, and then into the pulse receiver. The output data of the chip are sent back to the N4901B Serial BERT for the bit error rate (BER) measurement. At the same time, the output data are also sent to an Agilent 86100B for the eye diagram measurement. We expect the output data rate is 5Gbps with 240mV swing and the peak-to-peak jitter of 0.21UI. Besides, three HP E3610A DC Power Supplies are used. One is for the output open drain circuit, and the other two are for the transmitter and the receiver power rails. The power consumption is also measured by a Ktythley 2400 Source Meter.
Fig 5.6 Measurement instruments
Agilent 86100B Wide-Bandwidth
Oscilloscope
HP E3610A DC Power Supply
(Tx / Rx / CS) N4901B Serial BERT 5 Gbps
Input [vip,vin]
Output [vpop,vpon]
BER Measurement
Jitter Measurement
Supply 1.2V,0V
Ktythley 2400 Source Meter Power Measurement
Power Measurement
Chapter 6
Conclusion
In this thesis, we have proposed a 5Gbps on-chip pulse signaling interface.
Different from previous researches of pulse signaling or other on-chip communication, our near end architecture uses a high termination resistor combing the de-emphasis scheme to reduce ISI effect as well as to increase the maximum data rate. At far end, the self-bias circuit, the pre-amplifier, and the non-clock latch compose the receiver circuit. The self-bias circuit generates the common mode voltage for the receiver such that the pulse mode data can be received. The amplifier stage and the non-clock latch increase the amplitude of the pulse signal and then transfer the RZ pulse signal into NRZ data. The latch also has an input hysteresis range that can filter out the incoming noise from imperfect termination and common-mode disturbances such as the ground bounce. The receiver circuit is design in a simple scheme and easy for implementation.
In chapter 3, we have analyzed the pulse signaling as well as the on-chip channel model. We have also designed a 5mm on-chip differential transmission line in our chip. The characteristic impedance of the line is 75Ω to minimize the attenuation.
Furthermore, the geometry of the line is chosen in the width of 2.3µm and the spacing
of 1.5µm. Our on-chip transmission line has small area overhead as compares to other works.
The simulation results show that the receiver has a peak-to-peak jitter of 40.7ps from 1.2V supply. The power consumption of the transmitter is 0.68pJ/bit and total power is 1.32pJ/bit. This on-chip pulse signaling is fabricated in TSMC 0.13µm RF technology. The total chip occupies 884µm×644µm of area including a transmitter of 57µm×96µm, a receiver of 52µm×78µm and an on-chip transmission line. The chip will be sent back and measured in October, 2007.
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