Thesis Outline

In this thesis, experimental process and electrical parameters extraction are shown in chapter 2. In chapter 3, the electrical characterization of the Si/Ge T-gate TFTs are compared

with the conventional TFT. In chapter 4, the conclusions of this thesis and the future work are given.

Chapter 2

Experimental Process and Electrical Parameters Extraction

2.1 Fabrication of the thin-film transistors (TFTs)

The schematic cross sections of the Si/Ge T-Gate TFT is shown in Fig.2.1 and Fig.2.2.

And the schematic cross section of conventional device is shown in Fig.2.3. The fabrication procedures of these devices are described as following (Fig.2.4):

2.1.1 Fabrication of the Si/Ge T-Gate TFTs

I. Substrate:

The 6-in single crystalline silicon wafers with (100) orientation were used as the starting materials. After an RCA initial cleaning procedure, 550 nm thick thermal oxide was grown in steam oxygen ambient at 980°C.

II. Poly-Si thin film active region formation:

Undoped amorphous silicon layers of thickness about 50/100nm were deposited by low pressure chemical vapor deposition (LPCVD) on buried oxide by hydrolysis of silane (SiH4) at 550°C. Then, the amorphous silicon films were recrystallized by solid phase crystallization (SPC) method at 600°C for 24 hrs in an N2 ambient. These recrystallized poly silicon films were then patterned into active region islands by transformer couple plasma (TCP) etching using the mixture of Cl2 and HBr.

III. Gate dielectric and gate electrode formation:

After defining the active region, the 50nm thick gate TEOS oxide was deposited by low pressure chemical vapor deposition (LPCVD). Then, the germanium layer and the a-Si layer

were deposited as a gate, as shown Table 2.1. Table 2.2 shows the conditions for control devices.

Then, the wafers were ion implanted by phosphorous. The energy and the dose of implantation were 60keV and 5E15cm^-2. After the ion implantation, the germanium film and the a-Si layer were patterned and etched by transformer couple plasma (TCP-9400) to be the gate electrode.

IV. Si/Ge T-gate structure formation:

The T-gate was etched by selective wet etch method to form a T-shape structure. Then, Source and drain region were implanted by phosphorus (P) at 15keV /25keV to a dose of 5E15 cm^-2.

V. Passivation layer and contact metal:

Following, 300nm thick TEOS oxide by LPCVD was deposited and the contact hole was defined. TEOS oxide was etched by buffer oxide etchant (BOE) dip. Then, 500nm Aluminum sputtering and defines the metal pad. After etching Aluminum, the device was finished.

The nitride was also used to be a passivation material compare with the TEOS passivation device. In the chapter3, the electrical characteristics of the Si/Ge T-gate TFTs with Si₃N₄ passivation would compare with the TEOS passivation device.

2.1.2 Fabrication of the conventional TFTs

I. Substrate:

The 6-in single crystalline silicon wafers with (100) orientation were used as the starting materials. After an RCA initial cleaning procedure, 550 nm thick thermal oxide was grown in steam oxygen ambient at 980°C.

II. Poly-Si thin film active region formation:

Undoped amorphous silicon layers of thickness about 50/100nm were deposited by low pressure chemical vapor deposition (LPCVD) on buried oxide by hydrolysis of silane (SiH4) at 550°C. Then, the amorphous silicon films were recrystallized by solid phase crystallization (SPC) method at 600°C for 24hrs in an N2 ambient. These recrystallized poly silicon films were then patterned into active region islands by transformer couple plasma (TCP) etching using the mixture of Cl2 and HBr.

III. Gate dielectric and gate electrode formation:

After defining the active region, the 50nm thick gate TEOS oxide was deposited by low pressure chemical vapor deposition (LPCVD). Then, the 200nm a-Si film was deposited immediately on the gate dielectric by LPCVD at 550°C. (Table2)

Then, the wafers were ion implanted by phosphorous. The energy and the dose of implantation were 60 keV and 5E15 cm^-2. After the ion implantation, the a-Si layer were patterned and etched by transformer couple plasma (TCP-9400) to be the gate electrode.

IV. Source/Drain region formation:

Source and drain region were implanted by phosphorus (P) at 15 keV /25 keV to a dose of 5E15 cm^-2.

V. Passivation layer and contact metal:

Following, 300nm thick TEOS oxide by LPCVD was deposited and the contact hole was defined. TEOS oxide was etched by buffer oxide etchant (BOE) dip. Then, a 500 nm Aluminum was sputtered and patterned as for the metal pad. After etching Aluminum, the device was finished.

2.2 Method of device parameter extraction

In this thesis, all the electrical characteristics of proposed poly-Si TFTs were measured by HP 4156B-Precision Semiconductor Parameter Analyzer. Many methods have been proposed to extract the characteristic parameters of poly-Si TFTs. In this section, extractions of various electrical parameters are introduced. These parameters induced the threshold voltage (V_TH) and subthreshold swing (S.S.), maximum On-current (I_on), minimum Off-current (Ioff), and the On/Off current ratio.

2.2.1 Threshold voltage (V

TH

)

In this thesis, the threshold voltage (V_TH) is defined at a fixed drain current

( ^/ )

D DN

I = I × W L

where IDN is a normalized drain current. Here, IDN is 100 nA and the same for all devices. This definition corresponds to approximately the same surface band bending for all devices and avoids the ambiguity associated with an extrapolated threshold which arises in devices where the effective channel mobility depends strongly on the gate bias.

2.2.2 Subthreshold swing (S.S.)

The drain current in the saturation region (V

_D＞V_GS-V_TH) is expressed as the following equation:

¹

( )

²

DS 2 FE ox GS TH

I C W V V

μ L

= − (Eq.1)

Where W is gate width and L is gate length. Cox is the gate oxide capacitance. μEF is the field effect mobility.

It appears that the current abruptly vanishes while VG is reduced to zero from the equation. In reality, there is still some drain conduction below threshold, and this is known as subthreshold conduction. This current is due to the weak inversion in the channel between flat-band and threshold, which leads to a diffusion current from source to drain.

The subthreshold swing (S.S.) is defined as the reciprocal of slope of the ID-VG curve in weak inversion region. It means that a change in the input VG,

S.S. (V) will change the

output current ID by an order of magnitude. It is a typical parameter to describe the control ability of gate toward channel.

2.2.3 On/Off current ratio

A poly-Si TFT with good characteristics should not only provides high On state driving current but also low Off state leakage current. For pixel transistors, the Off state is frequently encountered in normal operation. Therefore, On/Off current ratio is obviously a more appropriate evaluation parameter compared with On state current alone. In addition, the mechanism of leakage current in poly-Si TFT’s quite differs from that in MOSFET’s. In MOSFET’s, it is the single crystalline that consists of the channel film and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. However, in poly-Si TFT’s, the channel film is composed of polycrystalline.

Lots of traps located in grain boundaries play a dominant role in this situation.

Consider large negative gate bias VG is applied, a hole channel forms under the gate.

In principle, little current flows because the junction between the hole channel and the drain is revered-biased. However, due to the large electric field and the existing numerous trap states in the polysilicon film, electron and hole emission from trap states becomes a strongly increasing function of electric field. Here, a trap could be modeled by a potential well. For large electric fields, it is possible for electrons to escape the potential well by quantum mechanical tunneling. The tunneling rate increases strongly with electric field because the barrier thickness decreases. The effect is a rapid increase in leakage current. The tunneling rate depends upon the total electric field, and consequently the leakage current is increased when both drain and gate voltages are high.

In this thesis, the On current is defined as the current when gate voltage equals to 20V

and drain voltage is 10V. The Off current is specified as the minimum current when drain voltage equals to 10V.

2.3 Material analysis

In order to demonstrate that the T- gate structure has been fabricated, and the length of the T-gate undercut region, we use the transmission electron microscope (TEM) and scanning electron microscopy (SEM) to confirm.

Fig.2.1 T he schematic cross section of the Si/Ge T-Gate TFTs with TEOS passivation

Fig.2.2 The schematic cross section of the Si/Ge T-Gate TFTs with Si

3

N

4

passivation

Fig.2.3 The schematic cross section of conventional TFTs

TEOS

(1) 550 nm thick buried oxide and 50/100nm thick a-Si were deposited.

(2) 600°C annealing for 24-hr and active region definition.

(3) 50 nm thick TEOS oxide was deposited.

(4) 50/100nm thick germanium layer and 150/100nm thick a-Si were deposited.

Buried oxide Poly-Si

TEOS Buried oxide

Poly-Si Buried oxide

a-Si

a-Si

Buried oxide Poly-Si

TEOS

Ge

(5) Phosphorous implantation.

(6) Gate definition.

(7) Si/Ge T-Gate structure formation.

a-Si

Buried oxide Poly-Si

TEOS Ge

Implant

a-Si

Buried oxide Poly-Si

TEOS Ge

a-Si

Buried oxide TEOS

Ge

Poly-Si

(8) Source/Drain region formation.

(9) TEOS passivation layer.

(10) Contact hole and metal pad.

Fig. 2.1 Process flows of Si/Ge T-Gate TFTs.

Implant

n ⁺ a-Si

Buried oxide Poly-Si

Ge

n

⁺

n

⁺

TEOS n ⁺

TEOS Poly-Si

n ⁺ Si

Buried oxide n ⁺ Ge

n

⁺

n

⁺

TEOS

TEOS Passivation

TEOS Poly-Si

n

⁺

Si

Buried oxide n

⁺

Ge

n⁺ n⁺

TEOS

Al Al

TEOS Al TEOS

Table 3.1 Split condition for all samples with different thickness of stacked Si/Ge and undercut length.

Device Channel thickness

Gate oxide

Gate (Si/ Ge) Undercut

Si/Ge_50nm T-gate TFT(400nm)

400nm Si/Ge_50nm T-gate TFT(800nm)

150nm / 50nm

800nm

Si/Ge_50nm T-gate TFT(400nm) 400nm

Si/Ge_50nm T-gate TFT(800nm)

50nm

100nm / 100nm

800nm

Si/Ge_100nm T-gate TFT(400nm) 400nm

Si/Ge_100nm T-gate TFT(800nm)

150nm / 50nm

800nm

Si/Ge_100nm T-gate TFT(400nm) 400nm

Si/Ge_100nm T-gate TFT(800nm)

100nm

All 50nm

100nm / 100nm

800nm

Table 3.2 Split conditions for control devices.

Device Channel thickness

Gate oxide

Gate (a-Si film) Undercut

Conventional TFT

50nm 200nm

Conventional TFT

100nm

50nm

200nm

Chapter 3

Electrical Characterization of the Si/Ge T-gate TFTs

At first, the cross-section TEM of T-gate TFTs is shown in Fig.3.1. Thickness of channel film, gate oxide, gate, and undercut length are shown in Fig.3.2. Fig. 3.3 shows the SEM image of the Stacked Si/Ge gate with undercut structure. The T-Gate structure was successfully fabricated, which had shown in the TEM and SEM pictures clearly. In this chapter, the electrical characteristics of the Si/Ge T-gate TFTs and conventional TFTs are discussed carefully. The device parameters including threshold voltage (VTH), subthreshold swing (S.S.), On current (ION), Off current (IOFF), and On/Off current ratio are all extracted. In order to verify the effect of the T-Gate structure on the vertical and lateral electric field near the drain, the electric field in the TFT was simulated by employing the commercial 2-D simulator for semiconductor device.

3.1 Device Simulation

As we know that the undesirable effect, anomalous leakage current, kink effect, and hot-carrier effect, are related to the lateral electric field in the channel. In order to study the electric field effects of the various LTPS TFT structures, the two-dimensional (2D) numerical device simulator TCAD- ISE (Integrated Systems Engineering) was utilized.

The 2D cross-section of TFTs structure obtained from DIOS-ISE process simulation.

The device simulation grids for the structures are generated using MDRAW-ISE. For electrical analysis is then carrier out in DESSIS-ISE on the structures. We consider the drift-diffusion model in our calculation.

Fig.3.4 and Fig.3.5 show the electric field distribution along the channel/gate insulator

interface for VG= -10V and VD= 10V. At the active layer surface under the T-Gate structure, the vertical electric field and lateral electric field are reduced considerably compared with conventional TFT. Especially, the Si/Ge T-Gate TFTs with high thickness of the germanium layer have shown a lower electric field than that of the Si/Ge T-Gate TFTs with 400nm germanium layer thickness.

Fig.3.6 and Fig.3.7 show the electric field distribution along the channel/gate insulator interface for VG= 0V and VD= 15V. It is also found that the Si/Ge T-Gate TFTs with TEOS passivation reduce both horizontal and vertical electric fields.

Fig. 3.8 and Fig.3.9 show the simulated electric field distribution for Si/Ge T-Gate TFTs with Si3N4 passivation. Results show that higher electric field at the drain edge of the high-k passivation TFT compared to the TEOS passivation TFT. The vertical and lateral electric field distribution along the channel/gate insulator interface for VG= 0V and VD= 15V are shown in Fig.3.10 and Fig.3.11.

It is well known that the leakage current increases significantly with the increase of gate voltage and drain voltage due to the field enhanced generation [32][33]. The lateral peak electric field in the depletion region between the p⁺ accumulation layer and the n⁺ drain causes the field emission via trap states, which makes the leakage current increase with drain voltage. Increase of gate voltage increases the vertical electric field around the interface between the gate oxide and the active poly-Si near the drain, which causes the serious increase of leakage current due to the enhanced thermal generation [34].

3.2 Basic Electrical Characteristics of Si/Ge T-Gate TFTs 3.2.1 Transfer Characteristics

The I

D-VG characteristics of an n-channel Si/Ge T-Gate TFTs with different gate length (10μm、8μm、5μm、3μm) are shown in Fig.3.12~Fig.3.15. The leakage current of the Si/Ge T-Gate TFTs is lower by two orders of magnitude than that of conventional devices at

V

G = -10V. It is because that T-Gate TFTs could effectively reduce the electric field near the drain junction. For an LPCVD polysilicon TFT, according to the trap-assisted field-emission model, the leakage current can be expressed as [32]

1 D

where

x is the effective depth of the junction region, Z is the channel width, and N

_e T is the trap density. The time constants

τ

_TCand

τ

_TVrepresent the probability per unit time that a trapped carrier will tunnel through a triangular barrier at the channel/drain junction, which is exponentially dependent on the inverse of the strength of the lateral electric field Ey. Therefore, the leakage current can be reduced by decreasing the electric field at the channel/drain junction region.

The off-state current of the Si/Ge T-Gate TFTs are much lower than that of the conventional TFT. When the germanium layer thickness is increased, the off-state leakage current is reduced at VD = 10V, compared to the conventional TFT, which is due to the vertical electric field and lateral electric field near the drain edge are both reduced. As channel length is reduced, the leakage current is lower with increase of the T-Gate height is obviously.

Fig.3.16~Fig.3.19 show the transfer characteristics of the Si/Ge T-Gate TFTs with high channel thickness (100nm), the leakage current are also reduced significantly with increase of germanium layer thickness and undercut length.

The off-state leakage current was effectively suppressed in the Si/Ge T-Gate TFTs with channel thickness 50nm, especially when the increase of germanium layer thickness and undercut length. However, the on-current for these conditions is decreased due to the increased series resistance caused by the undercut regions. Hence, the Si3N4 with higher dielectric constant was used to improve the on-state characteristic.

The ID-VG characteristics of the Si/Ge T-Gate TFTs with a Si3N4 passivation for different gate length (10μm、8μm、5μm、3μm) are shown in Fig. 3.20~Fig. 3.23. These

TFTs have better subthreshold swing and high Ion than those TFTs with a TEOS passivation.

High dielectric constant materials have been used to increase capacitance Cox which could improve the on-state current. The combination of T-Gate structure and Si3N4 material can suppress the electric field and improve the on-state characteristics.

3.2.2 On/Off Current Ratio

Fig.3.24 show the gate length dependence of On/Off current ratio in Si/Ge T-gate TFTs with TEOS passivation and conventional TFT. The devices with 50/ 100nm thickness of channel film are shown in the figure (a) and (b). The higher series resistance of the undercut regions slightly degrades the on-current of the Si/Ge T-Gate TFTs with thick germanium film.

For this reason, the On/Off current ratio is lower than the thin germanium film devices, as shown in figure (a).

For the channel thickness is increased, shown in Fig.3.24 (b), the influence of series resistance is slightly released when increasing the thickness of germanium layer. In addition, the off-state leakage current of the Si/Ge T-Gate TFTs with thick germanium film is lower than other devices. The Si/Ge T-Gate TFTs with 100nm thickness of germanium layer have increased the On/Off current ratio relative to the Si/Ge T-Gate TFTs with 50nm thickness of germanium film.

The Si/Ge T-Gate TFTs with a Si3N4 passivation was shown in Figure 3.25. The On/Off current ratio trend is similar in the T-Gate devices because of the on-state current is considerably increased and off-state leakage current is almost the same.

All conventional TFTs show a smaller On/ Off current ratio among these devices, which is due to the leakage current can not be effectively suppressed with large electric field near the drain edge.

3.2.3 Off-State Leakage

The temperature dependence of the mobile holes in equilibrium with the trapped charge

is given by [35]

₀

Ea

off kT

I = I e

⁻

(Eq.3)

I

0 = constant independent of temperature, and Ea = drain current activation energy which measures the difference between the valence band edge and the energy of the grain boundary states within kT of the Fermi level. In TFTs, the increase in the electric field strength causes the decrease of the leakage current activation energy [36]. As the drain bias increases, the drain depletion field increases and Ea decreases. This suggest that the high electric field in the drain depletion region has reduced the barrier that carrier must overcome. This leakage current mechanism is thermionic field emission [35].

The Off-state leakage current characteristics are shown in Fig.3.26 and Fig.3.27. The Si/Ge T-Gate TFTs show the leakage current as low as 1pA/μm. It is because the T-Gate structure can effectively suppress the electric field near the drain edge. In the conventional TFT, Ioff abruptly increases with increasing Vd

because of the thermionic field emission

current at drain junction [37].

3.2.4 Output Characteristics

The current increase in the output characteristics at large VDS, usually referred to as

“kink effect,” is explained by impact ionization occurring in the high-field region at the drain end of the channel. Its effect is enhanced by the action of a parasitic bipolar transistor in the back-channel region, whose base current arises from the impact generated holes [38].

Figure 3.28~ Figure 3.30 show the output characteristics of conventional TFTs and Si/Ge T-gate TFTs with W/L=10μm/10μm. The ID-VD performances of the Si/Ge T-gate TFTs were much better than the conventional TFT. For the conventional TFTs, the severe kink

effect at high drain biases is a result of the exaggerated avalanche multiplication near drain junction caused by the high drain field and large amount of traps [39].

Impact ionization has been modeled by the Chynoweth expressions of the ionization rates for electrons (αn) and holes (αp) [40]

α

_n =

a

_nexp^⎛⎜⁻

b

ⁿ

F

^⎞⎟

⎝ ⎠ _{p p}exp

b

^p

a F

α

= ^⎛⎜⎝^{− ⎞}⎟⎠ (Eq.4)

where F^∥ is the component of the electric field along the current-flow direction. The ionization rate is reduced by suppressing lateral electric field. Therefore, at very high source-drain voltages, drain avalanche is unobvious for T-Gate structure.

Figure 3.28 shows the result for (a) germanium layer thickness is 50nm, and (b) germanium layer thickness is 100nm. The device with thickness of germanium layer 100nm exhibits a smaller on-current than that of 50nm germanium layer case. This is because the series resistance is increased under the undercut region. However, floating body effect is reduced in Si/Ge T-gate TFTs with thick thickness of germanium film which caused by suppressed lateral electric field.

The kink effect in SOI MOSFETs is a combination of the channel avalanche multiplication occurred in the high-field region near the drain and the floating body effect at the channel of the device [41]. However, in poly-Si TFTs, there is an additional mechanism that causes the poor saturation characteristics. It is the high grain-boundary trap density in the poly-Si material that exaggerates the effect of the avalanche multiplication [42] [43].

When channel film is increased, the grain-boundary trap density in the channel will cause the sever kink effect at high drain biases, as shown in Figure 3.29. But it is found that the Si/Ge T-gate TFTs exhibits with good current saturation characteristics compared with conventional TFT. In the conventional TFT, the higher lateral electric field will generate more hot carriers which cause seriously floating body effect to occur.

The output characteristics of Si/Ge T-Gate TFTs with a Si3N4 passivation were shown

in the Fig.3.30. The anomalous current was suppressed at VD< 15V and the on-current characteristic are better than those TFT with a TEOS passivation. But the drain avalanche occurs as the drain voltage is increased, which is due to the lateral electric field is larger than the Si/Ge T-Gate TFTs with a TEOS passivation. In order to obtain excellent saturation characteristics in the low temperature poly-Si (LTPS) TFT’s, both the high electric field and high grain-boundary trap density at the channel near the drain must to be reduced effectively.

3.2.5 Hot Carrier Stress

Hot carrier stress was used to test the long-term reliability of LTPS TFT in this work.

Hot carrier instabilities in poly-Si thin film transistors are caused by high electric fields at the drain. These high fields are determined mainly by the abruptness of the lateral n⁺ doping

Hot carrier instabilities in poly-Si thin film transistors are caused by high electric fields at the drain. These high fields are determined mainly by the abruptness of the lateral n⁺ doping

在文檔中 新穎堆疊矽/鍺T型閘極複晶矽薄膜電晶體 (頁 16-0)