Chapter 4 Conclusions and Future Works
4.2 Future Works
The Si/Ge T-Gate structure can be form by elective wet etch method, but the etch time and temperature of liquors are difficult to control. Furthermore, the TEOS oxide deposited by LPCVD has poor quality which would cause additional problems. Thus, we must find the optimum conditions to accurately control the length of undercut and use PECVD for deposit the TEOS oxide.
The T-Gate structure can be applied as a memory device. This idea is shown in Figure 4.1. The oxide/SiNx/oxide stacked layers be formed under the undercut region of T-Gate TFTs. The expression of good data retention and endurance will be expected.
Fig.4.1 The schematic cross section of stacked Si/Ge T-Gate TFT with O/N/O tripping layer.
p type Si-sub Wet Oxide 550nm
n
+Poly-Si gate
n
+Poly-Ge gate
Poly-Si channel
SiO
2n
+n
+Si
3N
4Si
3N
4O
O O
O N N
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