Chapter 1 Introduction…
1.3 Thesis Outline
This dissertation is organized as follow:
In Chapter 2, the device parameters extraction methods and device measurements will be described.
In Chapter 3, we fabricate and investigate a novel self-aligned poly-Si TFTs with asymmetric source/drain implant. In this chapter we use the process of implantation to materialize the offset region beside the drain junction which form the lightly-doped region after RTA anneal. As well know this lightly-doped-drain junction contributes to restrain the electric field in the drain junction. Also, only one side lightly-doped region after well control would show no degradation at on-state performance. In other words, we contribute a very simple way for polycrystalline silicon thin film transistor without additional mask.
In Chapter 4, a new structure of polycrystalline thin film transistor named ploy-Si
TFTs with sidewall floating gate was realized. This novel structure TFTs also needs no additional mask. It is made by a clever self-aligned procedure. This new TFTs device structure shows not only excellent subthreshold characteristics but also better kink effect. Moreover, the sidewall floating gate acts like the floating gate of flash devices, charges would be stored in it and shift the threshold voltage. So a new TFTs flash was accomplished in our work. However, the program/erase time is not short enough since the tunneling oxide is too thick in this work.
In Chapter 5 conclusions as well as some for further study are given.
Chapter 2
Measurements and Device Parameters Extraction
2.1 Measurement
In this thesis, we use N&K analyzer to measure the thickness of poly-Si, amorphous-Si, and TEOS oxide films in the fabrication procedure.
HP 4156 semiconductor parameter analyzer with source grounded and body floating performed the current-voltage characteristics of thin film transistor devices.
2.2Methods of Device Parameter Extraction
Many methods have been proposed to extract the characteristic parameters of poly-Si TFT. In this section, the methods of parameter extraction used in this research are described.
2.2.1 Determination of threshold voltage ( Vth )
The threshold voltage Vth is an important MOSFET parameter required for the channel length-width and series resistance measurements. However, Vth is a voltage that is not uniquely defined. Various definitions exist and the reason for this van be found in the ID-VGS curves. One of the most common threshold voltage measurement technique is the linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of typically 50-100 mV to ensure operation in the linear MOSFET region[59]. But the drain current is not zero below threshold and approaches zero only asymptotically. Hence the ID versus VGS curve is extrapolated to ID = 0, and the threshold voltage is determined from the extrapolated or intercept gate voltage VGSi by
2 Equation ( 2.1 ) is strictly only valid for negligible series resistance. Fortunately
series resistances is usually negligible at the low drain currents where threshold voltage measurements are made. The ID-VGS curve deviates from a straight line at gate voltage below Vth due to subthreshold currents and above Vth due to series resistance and mobility degradation effects. It is common practice to find the point of maximum slope on the ID-VGS curve at that point and extrapolate to ID=0, as illustrated in Fig.2-2.
2.2.2 Determination of subthreshold swing
Sbthreshold swing S.S ( V/decade ) is a typical parameter to describe the control ability of gate toward channel. It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude.
The subthreshold swing should be independent of drain voltage and gate voltage.
However, in reality, the subthreshold swing might increase with drain voltage due to short-channel effects such as charge sharing, avalanche multiplication, and punchthrough-like effect. The subthreshold swing is also related to gate voltage due to undesirable factors such as serial resistance and interface state.
In this experiment, the subthreshold swing is defined as one-third of the gate voltage required decreasing the threshold current by three orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to threshold voltage.
2.2.3 Determination of field effect mobility (μfe)
The field-effect mobility (μfe ) is determined from the transconductance ( gm) at low drain voltage. The transfer characteristics of poly-Si TFTs are similar to those of conventional MOSFETs, so the first order I-V relation in the bulk Si MOSFETs can be applied to poly-Si TFTs, which can be expressed as
2 ]
Cox is the gate oxide capacitance per unit area, W is the channel width,
L is the channel Length, Vth is the threshold voltage.
If VD id much smaller than VG-VTH ( i.e.VD<<VG-VTH ) and VG>VTH, the drain current can be approximated as:
D
The transconductance is given by
t Therefore, the field-effect mobility is
Cox
2.2.4 Determination of on/off current ratio
On/Off current ratio is one of the most important parameters of poly-Si TFTs since a good performance means not only large On current but also small Off ( leakage ) current. The leakage current mechanism in poly-Si TFTs is not like it in MOSFET. In MOSFET, the channel is composed of single crystalline and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. However, in poly-Si TFTs, the channel is composed of poly
crystalline. A large amount of trap densities in grain structures attribute a lot of defect states in energy band gap to enhance the tunneling effect. Therefore, the leakage current due to the tunneling effect is much larger in poly-Si TFTs than in single crystalline devices. When the voltage drops between gate voltage and drain voltage increases, the band gap width decreases and the tunneling effect becomes much more severe. Normally we can find this effect in typical poly-Si TFTs ID-VG characteristics where the magnitude of leakage current will reach a minimum and then increase as the gate voltage decreases/increases for n/p-channel TFTs.
There are a lot of ways to specify the On and Off current. In my thesis, take n-channel poly-Si TFTs for examples, the On current and Off current is defined as the when gate voltage equal to 15V and drain voltage is 0.1V ( linear operation mode ). The Off current is specified as the minimum leakage current in linear operation mode for casual cases.
2.2.5 Extraction of grain boundary trap state density (Nt )
The trap state density, which can be determined by the theory established by Levison et al.[60], id based on Seto’s theory[61].
For a thin-film transistor, the source-drain current IDS can be given as following
8 ) equation with an activated mobility, which depends on the grain-boundary barrier height as introduced by Step. Levison et al. assumed that the channel thickness was constant and equal to the thickness of the polysilicon film (t). This simplifying assumption is permissible only for very thin film ( t<10 nm ). The trap-state density can be obtained by extracting a straight line on the plot of ln(IDS/VGS) versus 1/VGS at low source-drain voltage and high gate voltages.
Proano et al.[62] thought that a better approximation is to calculate the gate induced carrier channel thickness by solving Poisson’s equation for an undoped material and to define the channel thickness as a thickness which 80 percent of the total charge induced by the gate. Doing so, one obtains
which varies inversely with ( VGS-Vfb). This predicts, by substituting Eq. 2.7 into Eq. 2.6 that ln[IDS/(VGS-Vfb)] versus 1/( VGS-Vfb)2 . We used the gate voltage at which minimum leakage current occurs as Vfb. Effective trap-state density Nt can be determined from the square root of the slope.
Slope q
Nt =Cox (2.10)
Chapter 3
Characterization of Polysilicon Thin Film Transistors with Asymmetric Source/Drain Implantation
3.1 Introduction
Polycrystalline thin film transistors technology are promising for AMLCD applications, the anomalous off-state leakage current represent one of important issues [18]. It is well known that field emission via grain boundary traps due to high electric field in the drain depletion region would dominate off-state leakage current[18]. A common method proposed to reduce the severe anomalous leakage current of polycrystalline silicon TFTs is to alleviate the electric field near the drain junction. To achieve this goal, two popular strategies have been proposed, namely, lightly-doped drain (LDD) [37]-[40] and field –induced drain (FID)[44]-[46].
In the LDD structure, the source/drain is formed by two step implantation, as shown in Fig. 3.1.1.[38] The LDD implant is to produce a lightly doped section of the source/drain near the channel. LDD region with lower dosage is self-aligned to the gate electrode. It is useful to improve drain leakage by using LDD structure. However, the degradation of on-current due to increase in parasitic resistance introduced in the LDD region is the penalty that must be paid. The required extra lithography and ion doping steps will increase the fabrication costs and make it more complicated in processing.
The second approach, which was proposed by Keiji Takana et al.[49], employs a undoped offset region besides the gate shown in Fig. 3.1.2. The undoped region can alleviate the drain side electric field effectively. But usually it needs an additional mask to define the offset region. Moreover, the offset region creates a big series
resistance when devices are biased at on state and result in on-state current degradation. This is not what we want for polycrystalline thin film transistors performance.
The third approach, which was originally proposed by Huang et al.[51], employs a field-plate or sub-gate over an undoped offset region in the active channel layer between the drain and the region directly underneath the gate to form a field-induced-drain (FID) region (Fig. 3.1.3). In this approach, the lightly-doped drain implant that was required in the LDD approach can be skipped. The FID structure has been shown to extremely effective in reducing the off-state leakage, while maintaining good on-state current. The excellent performance of FID structure is believed to due to the effects of a reduced drain electric field. However, the structure of field-induced-drain TFTs structure needs an additional mask to define the sub-gate and offset region. Also, more thin films must be deposited and the misaligned problem is concerned. More films means more fabrication costs. Misalignment means the challenge of uniformity maybe not ignore. In this chapter, we fabricated and investigated a new self-align top gate thin film transistor structures which need no more mask and can shows excellent leakage performance. The first structure is polycrystalline thin film transistor with asymmetric source/drain implantation. By the tilt implantation of source/drain method, the offset region beside the drain junction forms the lightly doped drain. As well as the LDD TFTs structures, the light doped drain region suppresses the field effect near the drain junction. Moreover, by well controlled the lightly doped drain region, this structure can act as a conventional structure in the on-state and turn-on current will not be degraded.
3.2 Fabrication of Polysilicon Thin Film Transistors with Asymmetric Source/Drain Implantation
The schematic cross sections of the Assymetric Source/Drain Implantation is shown in Fig. 3.2.1. And the schematic cross section of conventional device is shown in Fig.3.2.2. The fabrication procedures of these devices are described as following (Fig 3.2.3):
Ⅰ. Substrate 100nm p-type single crystalline silicon wafers with (100) orientation were used as the starting materials. After an RCA initial cleaning procedure, 1000 nm thick thermal oxide were grown in steam oxygen ambient at 980°C.
Ⅱ. Poly-Si Thin Film Active Region formation: Undoped amorphous silicon layers of thickness about 50nm or 100nm were deposited by low pressure chemical vapor deposition ( LPCVD ) on buried oxide by pyrolysis of silane ( SiH4) at 550°C.
The amorphous silicon films were recrystallized by solid phase crystallization (SPC) method at 600°C for 24hrs in an N2 ambient. These recrystallized poly silicon films were then patterned into active region islands by transformer couple plasma (TCP) etching using the mixture of Cl2 and HBr.
Ⅲ. Gate dielectric and gate electrode formation: In order to decrease the roughness of interface between gate oxide and poly silicon island, thermal oxidation of silicon is excluded. After defining the active region, the wafers were boiled in H2SO4 +H2O2 to ensure cleanliness of the wafers before deposition. A buffered HF dip was performed to remove the native oxide on the silicon surface. The gate insulator was deposited by low pressure chemical vapor deposition (LPCVD) using TEOS and O2 gases at 695°C. After deposition of the gate insulator, a 300nm poly silicon film was deposited immediately on the gate dielectric by LPCVD at 595°C. This poly
silicon was then patterned and etched by transformer couple plasma (TCP) to be the gate electrode. Then remove the gate oxide on source/drain by HF dip.
Ⅳ. Source/Drain formation: A thin oxide was deposited as a buffer of implantation to keep off damages on gate dielectric as shown in Fig. 3.2.4 After that source and drain region were implanted by Arsenic (As) as the condition shown in Table 3.1.1. The twist angel come with the tilt angle because the implanter machine roll wafers with three dimensions at the same time as shown in Fig. 3.2.5 The twist angle was fit to the tilt angle by exactly measurement. After ion implantation, the samples were annealed by RTA ambient at 700°C for 20sec and removed the thin oxide by HF dip.
Ⅴ. Passivation oxide and contact metal: Following, 100nm TEOS oxide by LPCVD was deposited and the contact hole was defined. TEOS oxide was etched by buffer oxide etchant (BOE) dip. Then, 900nm Aluminum was sputtered and defined the metal pad. Etching Aluminum and sintering at 400°C in N2 ambient for 30 min.
3.3 Results and Discussion
3.3.1 Asymmetric Source/Drain Implantation With Source/Drain Exchange Measurement
In order to confirm the device structure was fabricated completely, we measure the current-voltage characteristics with exchanging source/drain electrode as shown in Fig. 3.3.1. All devices The with W/L = 10µm/3µm are measured at VDS =0.5 V and 5V.HP 4156 was used to measure all the current-voltage ( I-V ) characteristics and exact device parameters. In this part, results are presented in Fig. 3.3.2 and Fig.3.3.3.
In Fig. 3.3.2, we see subthreshold characteristics of tilt 30° sample get a better performance when the high potential was biased at the drain side. The leakage current of drain side measurement would not be exponentially increasing with gate and drain voltage increased. It means that the lightly-doped-drain region is properly formed only at the drain side and the source side junction is heavily doped. So that the electric field acts at the source side and makes leakage current increasing anomalously when bias was added at the source side. In this figure we are informed that when gate bias at -10 volt, source side leakage current would reach almost 0.1 µA . However, drain side leakage current could be suppressed to 50 pA. There is three order leakage improvement we made. In Fig. 3.3.3, All devices with W/L = 10µm/3µm are measured at VG=5, 6 and 7V. HP 4156 was used to measure. In this figure, the ID-VD curves have been shown. When device is measured at the drain side, better kink effect is performed than measured at the source side. In the tilt 30° samples, when VD was added to 5 V, source side current shows that kink effects is going to happen. However, the drain side measurement was not till the drain voltage increasing to 7 V. That means kink effect happened in polycrystalline TFTs which caused by the high field emission and grain boundary traps is effectively depressed by the lightly-doped-drain ( LDD ). And this lightly-doped-drain exists only at the drain side. In Fig. 3.3.4 and Fig. 3.3.5 we show the sample of tilt 45° asymmetric polycrystalline TFTs. These two figures obviously shows the same characteristics as we described in the before two ones. And we compare Fig. 3.3.4 and Fig. 3.3.5 to Fig. 3.3.2 and Fig. 3.3.3, it shows that the more shift region formed at tilt samples the smaller leakage currents we get and the more shift region formed at tilt samples the better kink effect devices perform.
For instance, the leakage current of tilt 45° when VG is -10 V is 2 pA but 50 pA in tilt 30° samples and the kink effect does not happen till VD is 8 V in 45° samples but it happens when VD is 7 V. Also, the size of lighly-doped region affects the
subthreshold characteristics of device.
3.3.2 Subthreshold Characteristics
We compare the device we designed to conventional polycrystalline TFTs . All devices The with W/L = 10µm/3µm are measured at VDS =0.5 V and 5V.HP 4156 was used to measure all the current-voltage ( I-V ) characteristics and extract device parameters. In Fig. 3.3.6 , the transfer curves of conventional polycrystalline TFTs and asymmetric source/drain implantation polycryastalline TFTs are shown.
Anomalous leakage current of conventional TFTs increases exponentially with difference between gate and drain voltage caused by the drain side high electric field and grain boundary defects. However the new structure asymmetric source/drain implantation polycrystalline TFTs does not show this shortcoming. This contribution is made by the lightly-doped-drain ( LDD ) junction which suppresses the drain side high electric field when gate bias is strongly negative. Compare this two devices, we see that when gate bias to -10 V the drain leakage of conventional polycrystalline TFTs is about 0.1 µA but asymmetric ones only about 50 pA. There is almost 3.5 order leakage suppressed we made in this experiment. This is a great improvement for polycrystalline TFTs. At the on-state performance, asymmetric polycrystalline TFTs have no difference with conventional ones. Since the lightly-doped region is only at drain side but not at source side. The series resistance of polycrystalline TFTs channel is much bigger than that of metal-oxide-silicon field effect transistors ( MOSFETs ).
So the series resistance at on state would not be so serious in polycrystalline thin film transistors. This is why the on-state current not degraded with additional lightly-doped region. As a result, we fabricated a novel new polycrystalline TFTs without any additional mask which show excellent leakage current performance and on-state current performance.
3.3.3 Device characteristics
We extract the device characteristics from the transfer curves in Fig.3.3.7 and show them at Table 3.3.2. First, we survey the on/off ratio of asymmetric and conventional TFTs. Obviously, the on/off ratio of asymmetric polycrystalline TFTs can reach 107 and only 106 at conventional ones. This improvement is made by the leakage current suppressed. The asymmetric source/drain implantation polycrystalline TFTs have lower leakage and the same on-state current than conventional TFTs, so the on off ratio would be improved. The threshold voltage of asymmetric TFTs and conventional TFTs have no difference. Threshold voltage means the voltage gate bias needs to make the channel form inversion layer. This is concerned about the gate oxide thickness, channel quality and etc. There is no difference in our new structure and conventional ones except the source/drain implantation. So the threshold voltage would be the same in these two structures. The inductance Gm and mobility also have the same result. Mobility of polycrystalline TFTs is most affected by channel film quality especially the grain size and grain boundary defects. The bigger grain size
We extract the device characteristics from the transfer curves in Fig.3.3.7 and show them at Table 3.3.2. First, we survey the on/off ratio of asymmetric and conventional TFTs. Obviously, the on/off ratio of asymmetric polycrystalline TFTs can reach 107 and only 106 at conventional ones. This improvement is made by the leakage current suppressed. The asymmetric source/drain implantation polycrystalline TFTs have lower leakage and the same on-state current than conventional TFTs, so the on off ratio would be improved. The threshold voltage of asymmetric TFTs and conventional TFTs have no difference. Threshold voltage means the voltage gate bias needs to make the channel form inversion layer. This is concerned about the gate oxide thickness, channel quality and etc. There is no difference in our new structure and conventional ones except the source/drain implantation. So the threshold voltage would be the same in these two structures. The inductance Gm and mobility also have the same result. Mobility of polycrystalline TFTs is most affected by channel film quality especially the grain size and grain boundary defects. The bigger grain size