Chapter 2 Measurements and Device Parameter Extraction
2.2 Methods of Device Parameter Extraction
2.2.5 Extraction of grain boundary trap state density (Nt )
There are a lot of ways to specify the On and Off current. In my thesis, take n-channel poly-Si TFTs for examples, the On current and Off current is defined as the when gate voltage equal to 15V and drain voltage is 0.1V ( linear operation mode ). The Off current is specified as the minimum leakage current in linear operation mode for casual cases.
2.2.5 Extraction of grain boundary trap state density (Nt )
The trap state density, which can be determined by the theory established by Levison et al.[60], id based on Seto’s theory[61].
For a thin-film transistor, the source-drain current IDS can be given as following
8 ) equation with an activated mobility, which depends on the grain-boundary barrier height as introduced by Step. Levison et al. assumed that the channel thickness was constant and equal to the thickness of the polysilicon film (t). This simplifying assumption is permissible only for very thin film ( t<10 nm ). The trap-state density can be obtained by extracting a straight line on the plot of ln(IDS/VGS) versus 1/VGS at low source-drain voltage and high gate voltages.
Proano et al.[62] thought that a better approximation is to calculate the gate induced carrier channel thickness by solving Poisson’s equation for an undoped material and to define the channel thickness as a thickness which 80 percent of the total charge induced by the gate. Doing so, one obtains
which varies inversely with ( VGS-Vfb). This predicts, by substituting Eq. 2.7 into Eq. 2.6 that ln[IDS/(VGS-Vfb)] versus 1/( VGS-Vfb)2 . We used the gate voltage at which minimum leakage current occurs as Vfb. Effective trap-state density Nt can be determined from the square root of the slope.
Slope q
Nt =Cox (2.10)
Chapter 3
Characterization of Polysilicon Thin Film Transistors with Asymmetric Source/Drain Implantation
3.1 Introduction
Polycrystalline thin film transistors technology are promising for AMLCD applications, the anomalous off-state leakage current represent one of important issues [18]. It is well known that field emission via grain boundary traps due to high electric field in the drain depletion region would dominate off-state leakage current[18]. A common method proposed to reduce the severe anomalous leakage current of polycrystalline silicon TFTs is to alleviate the electric field near the drain junction. To achieve this goal, two popular strategies have been proposed, namely, lightly-doped drain (LDD) [37]-[40] and field –induced drain (FID)[44]-[46].
In the LDD structure, the source/drain is formed by two step implantation, as shown in Fig. 3.1.1.[38] The LDD implant is to produce a lightly doped section of the source/drain near the channel. LDD region with lower dosage is self-aligned to the gate electrode. It is useful to improve drain leakage by using LDD structure. However, the degradation of on-current due to increase in parasitic resistance introduced in the LDD region is the penalty that must be paid. The required extra lithography and ion doping steps will increase the fabrication costs and make it more complicated in processing.
The second approach, which was proposed by Keiji Takana et al.[49], employs a undoped offset region besides the gate shown in Fig. 3.1.2. The undoped region can alleviate the drain side electric field effectively. But usually it needs an additional mask to define the offset region. Moreover, the offset region creates a big series
resistance when devices are biased at on state and result in on-state current degradation. This is not what we want for polycrystalline thin film transistors performance.
The third approach, which was originally proposed by Huang et al.[51], employs a field-plate or sub-gate over an undoped offset region in the active channel layer between the drain and the region directly underneath the gate to form a field-induced-drain (FID) region (Fig. 3.1.3). In this approach, the lightly-doped drain implant that was required in the LDD approach can be skipped. The FID structure has been shown to extremely effective in reducing the off-state leakage, while maintaining good on-state current. The excellent performance of FID structure is believed to due to the effects of a reduced drain electric field. However, the structure of field-induced-drain TFTs structure needs an additional mask to define the sub-gate and offset region. Also, more thin films must be deposited and the misaligned problem is concerned. More films means more fabrication costs. Misalignment means the challenge of uniformity maybe not ignore. In this chapter, we fabricated and investigated a new self-align top gate thin film transistor structures which need no more mask and can shows excellent leakage performance. The first structure is polycrystalline thin film transistor with asymmetric source/drain implantation. By the tilt implantation of source/drain method, the offset region beside the drain junction forms the lightly doped drain. As well as the LDD TFTs structures, the light doped drain region suppresses the field effect near the drain junction. Moreover, by well controlled the lightly doped drain region, this structure can act as a conventional structure in the on-state and turn-on current will not be degraded.
3.2 Fabrication of Polysilicon Thin Film Transistors with Asymmetric Source/Drain Implantation
The schematic cross sections of the Assymetric Source/Drain Implantation is shown in Fig. 3.2.1. And the schematic cross section of conventional device is shown in Fig.3.2.2. The fabrication procedures of these devices are described as following (Fig 3.2.3):
Ⅰ. Substrate 100nm p-type single crystalline silicon wafers with (100) orientation were used as the starting materials. After an RCA initial cleaning procedure, 1000 nm thick thermal oxide were grown in steam oxygen ambient at 980°C.
Ⅱ. Poly-Si Thin Film Active Region formation: Undoped amorphous silicon layers of thickness about 50nm or 100nm were deposited by low pressure chemical vapor deposition ( LPCVD ) on buried oxide by pyrolysis of silane ( SiH4) at 550°C.
The amorphous silicon films were recrystallized by solid phase crystallization (SPC) method at 600°C for 24hrs in an N2 ambient. These recrystallized poly silicon films were then patterned into active region islands by transformer couple plasma (TCP) etching using the mixture of Cl2 and HBr.
Ⅲ. Gate dielectric and gate electrode formation: In order to decrease the roughness of interface between gate oxide and poly silicon island, thermal oxidation of silicon is excluded. After defining the active region, the wafers were boiled in H2SO4 +H2O2 to ensure cleanliness of the wafers before deposition. A buffered HF dip was performed to remove the native oxide on the silicon surface. The gate insulator was deposited by low pressure chemical vapor deposition (LPCVD) using TEOS and O2 gases at 695°C. After deposition of the gate insulator, a 300nm poly silicon film was deposited immediately on the gate dielectric by LPCVD at 595°C. This poly
silicon was then patterned and etched by transformer couple plasma (TCP) to be the gate electrode. Then remove the gate oxide on source/drain by HF dip.
Ⅳ. Source/Drain formation: A thin oxide was deposited as a buffer of implantation to keep off damages on gate dielectric as shown in Fig. 3.2.4 After that source and drain region were implanted by Arsenic (As) as the condition shown in Table 3.1.1. The twist angel come with the tilt angle because the implanter machine roll wafers with three dimensions at the same time as shown in Fig. 3.2.5 The twist angle was fit to the tilt angle by exactly measurement. After ion implantation, the samples were annealed by RTA ambient at 700°C for 20sec and removed the thin oxide by HF dip.
Ⅴ. Passivation oxide and contact metal: Following, 100nm TEOS oxide by LPCVD was deposited and the contact hole was defined. TEOS oxide was etched by buffer oxide etchant (BOE) dip. Then, 900nm Aluminum was sputtered and defined the metal pad. Etching Aluminum and sintering at 400°C in N2 ambient for 30 min.
3.3 Results and Discussion
3.3.1 Asymmetric Source/Drain Implantation With Source/Drain Exchange Measurement
In order to confirm the device structure was fabricated completely, we measure the current-voltage characteristics with exchanging source/drain electrode as shown in Fig. 3.3.1. All devices The with W/L = 10µm/3µm are measured at VDS =0.5 V and 5V.HP 4156 was used to measure all the current-voltage ( I-V ) characteristics and exact device parameters. In this part, results are presented in Fig. 3.3.2 and Fig.3.3.3.
In Fig. 3.3.2, we see subthreshold characteristics of tilt 30° sample get a better performance when the high potential was biased at the drain side. The leakage current of drain side measurement would not be exponentially increasing with gate and drain voltage increased. It means that the lightly-doped-drain region is properly formed only at the drain side and the source side junction is heavily doped. So that the electric field acts at the source side and makes leakage current increasing anomalously when bias was added at the source side. In this figure we are informed that when gate bias at -10 volt, source side leakage current would reach almost 0.1 µA . However, drain side leakage current could be suppressed to 50 pA. There is three order leakage improvement we made. In Fig. 3.3.3, All devices with W/L = 10µm/3µm are measured at VG=5, 6 and 7V. HP 4156 was used to measure. In this figure, the ID-VD curves have been shown. When device is measured at the drain side, better kink effect is performed than measured at the source side. In the tilt 30° samples, when VD was added to 5 V, source side current shows that kink effects is going to happen. However, the drain side measurement was not till the drain voltage increasing to 7 V. That means kink effect happened in polycrystalline TFTs which caused by the high field emission and grain boundary traps is effectively depressed by the lightly-doped-drain ( LDD ). And this lightly-doped-drain exists only at the drain side. In Fig. 3.3.4 and Fig. 3.3.5 we show the sample of tilt 45° asymmetric polycrystalline TFTs. These two figures obviously shows the same characteristics as we described in the before two ones. And we compare Fig. 3.3.4 and Fig. 3.3.5 to Fig. 3.3.2 and Fig. 3.3.3, it shows that the more shift region formed at tilt samples the smaller leakage currents we get and the more shift region formed at tilt samples the better kink effect devices perform.
For instance, the leakage current of tilt 45° when VG is -10 V is 2 pA but 50 pA in tilt 30° samples and the kink effect does not happen till VD is 8 V in 45° samples but it happens when VD is 7 V. Also, the size of lighly-doped region affects the
subthreshold characteristics of device.
3.3.2 Subthreshold Characteristics
We compare the device we designed to conventional polycrystalline TFTs . All devices The with W/L = 10µm/3µm are measured at VDS =0.5 V and 5V.HP 4156 was used to measure all the current-voltage ( I-V ) characteristics and extract device parameters. In Fig. 3.3.6 , the transfer curves of conventional polycrystalline TFTs and asymmetric source/drain implantation polycryastalline TFTs are shown.
Anomalous leakage current of conventional TFTs increases exponentially with difference between gate and drain voltage caused by the drain side high electric field and grain boundary defects. However the new structure asymmetric source/drain implantation polycrystalline TFTs does not show this shortcoming. This contribution is made by the lightly-doped-drain ( LDD ) junction which suppresses the drain side high electric field when gate bias is strongly negative. Compare this two devices, we see that when gate bias to -10 V the drain leakage of conventional polycrystalline TFTs is about 0.1 µA but asymmetric ones only about 50 pA. There is almost 3.5 order leakage suppressed we made in this experiment. This is a great improvement for polycrystalline TFTs. At the on-state performance, asymmetric polycrystalline TFTs have no difference with conventional ones. Since the lightly-doped region is only at drain side but not at source side. The series resistance of polycrystalline TFTs channel is much bigger than that of metal-oxide-silicon field effect transistors ( MOSFETs ).
So the series resistance at on state would not be so serious in polycrystalline thin film transistors. This is why the on-state current not degraded with additional lightly-doped region. As a result, we fabricated a novel new polycrystalline TFTs without any additional mask which show excellent leakage current performance and on-state current performance.
3.3.3 Device characteristics
We extract the device characteristics from the transfer curves in Fig.3.3.7 and show them at Table 3.3.2. First, we survey the on/off ratio of asymmetric and conventional TFTs. Obviously, the on/off ratio of asymmetric polycrystalline TFTs can reach 107 and only 106 at conventional ones. This improvement is made by the leakage current suppressed. The asymmetric source/drain implantation polycrystalline TFTs have lower leakage and the same on-state current than conventional TFTs, so the on off ratio would be improved. The threshold voltage of asymmetric TFTs and conventional TFTs have no difference. Threshold voltage means the voltage gate bias needs to make the channel form inversion layer. This is concerned about the gate oxide thickness, channel quality and etc. There is no difference in our new structure and conventional ones except the source/drain implantation. So the threshold voltage would be the same in these two structures. The inductance Gm and mobility also have the same result. Mobility of polycrystalline TFTs is most affected by channel film quality especially the grain size and grain boundary defects. The bigger grain size channel film has the bigger mobility it owns. The less grain boundary traps it has the better mobility it shows too. The channel film in this experiment are all the same.
They are deposited at the same low pressure chemical vapor deposition chamber. This is why they show no difference. At last we check the subthreshold swing. They are also the same in these samples.
3.3.4 Kink Effects
In Fig. 3.3.8, we show the transfer curves of asymmetric TFTs which is tilted 30°
and conventional TFTs. All devices with W/L = 10µm/3µm are measured at VG=5, 6 and 7V. HP 4156 was used to measure. In this figure, asymmetric polycrystalline
TFTs show better kink effect performance than conventional TFTs. In the conventional polycrystalline TFTs, when VD was added to 5 V, drain current shows that kink effects is going to happen. However, the drain current of asymmetric source/drain implantation TFTs are not till the drain voltage increasing to 7 V. That means kink effect happened in polycrystalline TFTs which caused by the high field emission and grain boundary traps is effectively depressed by the lightly-doped-drain ( LDD ). Kink effect is an important issue for device operation. Better kink effect means bigger operation range of polycrystalline TFTs and that is what the new structure asymmetric source/drain implantation polycrystalline TFTs do.
3.3.5 Threshold Voltage roll off
In Fig. 3.3.9, devices with different channel length are measured by HP 41 and extracted the threshold voltage of each device. For both conventional and asymmetric source/drain implantation TFTs, threshold voltage is proportional to channel length.
However, conventional TFTs threshold voltage roll off is a little serious than asymmetric source/drain implantation. The reason for this phenomenon is the impact ionization in conventional TFTs is more serious than asymmetric TFTs. The impact ionization enhance the threshold voltage roll off.
3.4 Hot Carrier Stress
Hot carrier stress was used to test the long-term reliability of LTPS TFT in this work. Fig. 3.4.1 illustrates the threshold voltage variations and the degradation in a single TFT under static hot-carrier stress. △Vth is defined as the TFT being kept at a high electric field in the drain junction. Notably, the dc stress conditions are Vds=30V and Vgs=15V for 1000s. This effect occurs due to the higher electric field at the drain
junction. The high electric field promotes impact ionization, resulting in numerous grain-boundary traps being created in the drain junction. The large drain junction electric field during hot carrier stress resulted in sever degradation on conventional structure. On the other hand, the asymmetric TFT exhibited better hot carrier endurance than conventional one due to the drain junction electric field relief. Fig.
3.4.2 and Fig.3.4.3 show subthrehold swing and mobility degradation between asymmetric and conventional structure. Those two factors show the same result as the threshold voltage degradation. In our structure, we can effectively reduce the electric field near the drain side and obtain the optimal results in the hot carrier stress.
3.5 Summary
In this work, we have fabricated and characterized the new structure polycrystalline thin-film transistors featuring top gate. The GILD-like leakage appearing in conventional thin-film transistors could be suppressed obviously in this device and this is contributed by the lightly-doped-drain region which suppresses the drain side electric field. The on/off ratio of asymmetric TFTs could be improved to 107 which is bigger than conventional device about half order. Except the on/off ratio and leakage performance, other parameters such as subthreshold swing, threshold voltage, carrier mobility and etc have no difference with the conventional ones since the fabrication process has no difference with conventional thin-film transistors. It means that this new polycrystalline thin-film transistors match to the process of conventional TFTs. Those process could improve conventional TFTs such as ammonia plasma treatment, hydrogen plasma treatment, laser recrystallized and metal induced recrystallized (MIC)may be used to improve our new design.
Chapter 4
Characterization of Polysilicon Thin Film Transistors with Sidewall Floating Gate Structure
4.1
IntroductionAnomalous leakage current of polycrystalline silicon TFTs is an important issue for industrial application. In recent years, it has been pointed out that the conduction mechanism and performance of poly-Si TFTs were closely related to the existence of poly-Si grains and the properties of grain boundary[18]. As compared with single crystalline silicon, the polycrystalline silicon is rich in grain boundary defects, and the electrical activity of these charge-trapping centers profoundly affects the TFT characteristics. For instance, the defects in channel generate potential barrier which degrade the on-state current of polycrystalline silicon TFTs as well as the various of threshold voltage, field-effect mobility. Additionally, grain boundary defects also create the path of off-state leakage. Leakage current of poly-Si TFTs increases exponentially with difference between gate and drain voltage, and has been attributed to the field emission of carriers via the traps by high electric-field near the drain junction[18]-[20]. Recently, many ways have been proposed to suppress the anomalous leakage current such as plasma passivation, recrystallized by laser and device structure improvement. In this section, we fabricate and propose an new structure which shows better device performance and has memory characteristics.
Polycrystalline silicon thin-film transistors have been widely used to integrate driver circuits for AMLCD’s [63].The degree of circuit integration will continue to increase as device characteristics improve further, so that entire systems may be
integrated on a glass substrate soon. The entire system will include memories, such as SRAM and EEPROM.Electrical Erasable PROM (EEPROM) devices are very popular for applications such as programmable logic and high density memories. One of the important applications to polycrystalline thin-film transistors is used to fabricate system on panel (SOP). In this chapter, we design and fabricate a simple self-aligned sidewall floating gate polycrystalline TFTs. This new structure of polycrystalline TFTs shows not only program/erase characteristics but also better
integrated on a glass substrate soon. The entire system will include memories, such as SRAM and EEPROM.Electrical Erasable PROM (EEPROM) devices are very popular for applications such as programmable logic and high density memories. One of the important applications to polycrystalline thin-film transistors is used to fabricate system on panel (SOP). In this chapter, we design and fabricate a simple self-aligned sidewall floating gate polycrystalline TFTs. This new structure of polycrystalline TFTs shows not only program/erase characteristics but also better