In this thesis, we concentrate our efforts on metal gate for improving
Poly-Silicon TFTs’ performance.
In chapter 1, a brief overview of Poly-Silicon TFTs technology was given to
describe the various applications and characteristics of Poly-Silicon TFTs. And it also
shows our conception and motivation to use high –κgate dielectric and Ytterbium
metal gate.
In chapter 2, the fabrication process flows of low temperature Poly-Silicon TFTs
with metal gate and high –κ gate dielectric, experimental recipes and device
parameters extraction methods will be described.
In chapter 3, it shows the experimental data and the detail discussions of
characteristics of high dielectric constant TFTs with metal gate includes high drive
current, low threshold voltage, low sub-threshold slope, not bad mobility, and very
good breakdown voltage. And it also shows the comparison between the performance
of our conception and the performance of other TFTs’ design.
Finally, conclusions and future works as well as suggestion for further research
are given in chapter 4.
Chapter 2
The Experimental Steps
2.1 The Fabrication Steps
Fabrication of the TFTs started with the formation of a Poly-Silicon film, by
depositing 100-nm amorphous Silicon on SiO2/Si wafers (using LPCVD at 550 oC),
followed by crystallization at 600oC and 20 hour annealing in N2. Then 500 nm thick
PECVD oxide was deposited for isolation and device active region was formed by
patterning and etching the isolation oxide. The source and drain regions in the active
device region were implanted with phosphorus (35 KeV at 5×1015 cm-2) and activated
at 600oC for 12 hour annealing under N2. Then the 50 nm thick LaAlO3 gate dielectric
was deposited on previously patterned active region by sputtering from a LaAlO3
source with 150 W power and 30 sccm Ar flow rate. A 400oC and 30 min furnace O2
treatment was applied to improve the gate oxide quality. Then gate was formed by
depositing 200 nm Ytterbium using PVD. The TFTs devices were completed by gate
definition with lift-off process, electrode formation and 400oC sintering for 30 min
under N2 ambient without using hydrogenation plasma passivation treatment. The
fabricated device has gate length and width of 4 mµ and 100 mµ , respectively.
2.2 The Structure of fabrication
1. Silicon substrate.
Si
Fig 2.1 Step 1 2. Silicon dioxide growth ( 5000Å ).
Si SiO2(5000Å)
Fig 2.2 Step 2
3. Amorphous Silicon deposition by LPCVD at 550˚C ( 1000 Å ).
Si SiO2(5000Å)
-Si(1000Å)
Fig 2.3 Step 3
4. Poly-Silicon recrystallization by annealing in N2 at 600˚C for 20hr in furance.
Si SiO2(5000Å) Poly(1000Å)
Fig 2.4 Step 4
5. Isolation oxide deposition by PECVD ( 5000 Å )
.
Si SiO2(5000Å) Poly(1000Å) SiO2(5000Å)
Fig 2.5 Step 5
6. Source and Drain region define, patterning, etching ( MASK-1).
Si SiO2(5000Å) Poly(1000Å) MASK-1
Fig 2.6 Step 6
7. Source and Drain implantation with phosphorus ( 35KeV at 5e15 cm-2).
Si SiO2(5000Å) Poly(1000Å)
N+ N+
phosphorus
Fig 2.7 Step 7 8. Activating in N2 at 600˚C for 12hr.
9. Removing Silicon on gate region ( MASK-2 ).
Si SiO2(5000Å) Poly(1000Å)
N+ N+
MASK-2
Fig 2.8 Step 8 9
10. LaAlO3 deposition by PVD in Ar ( 150-W, 30-sccm, 500 Å ).
Si SiO2(5000Å) Poly(1000Å)
N+ LaAlO3(500Å) N+
Fig 2.9 Step 10 11. Contact hole define, patterning, etching ( MASK-3 ).
Si SiO2(5000Å) Poly(1000Å)
N+ LaAlO3(500Å) N+
MASK-3
Fig 2.10 Step 11
12. Photoresist deposition
Si SiO2(5000Å) Poly(1000Å)
N+ LaAlOPR3(500Å) N+
Fig 2.11 Step 12 13. Metal region definition ( lift-off, MASK-4 )
Si SiO2(5000Å) Poly(1000Å)
N+ LaAlO3(500Å) N+
PR PR
MASK-4
Fig 2.12 Step 13
14. PVD-Yb deposition ( 2000 Å )
Si SiO2(5000Å) Poly(1000Å) N+ Yb(2000Å)LaAlO3(500Å) N+
PR PR
Fig 2.13 Step 14
15. Removing PR
Si SiO2(5000Å) Poly(1000Å) N+ Yb(2000Å)LaAlO3(500Å) N+
Fig 2.14 Step 15
Chapter 3
Result & Discussion
3.1 Method Of Device Parameter Extraction
In this thesis, we use Ellipsometer to measure the thickness of Poly-Silicon, amorphous-Si and dielectric films in the fabrication procedure. All the electrical characteristics of proposed Poly-Silicon TFTs were measured by HP 4156 Precision Semiconductor Parameter Analyzer. Many methods have been proposed to extract the characteristic parameters of Poly-Silicon TFTs. In this section, those methods are described.
3.1.1 Determination Of Threshold Voltage
Threshold voltage (Vth) is an important parameter required for the channel length-width and series resistance measurements. However, Vth is not uniquely defined. Various definitions have been proposed and the reason can be found in ID-VGS curves. One of the most common techniques is the linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of 50~100mV to ensure operation in the linear region [17]. The drain current is not zero when VGS below threshold voltage and approaches zero asymptotically. Hence the IDS versus VGS curve can be extrapolated to ID=0, and the Vth is determined from the
extrapolated intercept of gate voltage (VGSi) by Equation (3.1) is strictly only valid for negligible series resistance. Fortunately series resistance is usually negligible at the low drain current when threshold voltage measurements are made. The IDS-VGS curve deviates from a straight line at gate voltage below Vth due to sub-threshold current and above Vth due to series resistance and mobility degradation effects. It is common practice to find the point of maximum slope of the IDS-VGS curve (the same as the max-value point of Field Effect Mobility, from Eq. 3.4)and fit a straight line to extrapolate to ID=0 by means of finding the point of maximum of transconductance (Gm).
In other thesis, someone can use a simpler method to determinate the Vth called constant drain current method. The voltage at a specified threshold drain current is taken as the Vth. This method is adopted in the most studied papers of Poly-Silicon TFTs. It can be given a threshold voltage close to that obtained by the complex linear extrapolation method. Typically, the threshold current is specified at (W/L)×10nA for VDS=0.1V and (W/L)×100nA for VDS=5V, where W and L are channel width and channel length, respectively.
3.1.2 Determination Of Sub-threshold Slope
Sub-threshold slope (S.S.) is a typical parameter to describe the control ability of gate toward channel, which reflects the turn on/off speed of a device. It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude.
The S.S. should be independent of drain voltage and gate voltage. However, in
reality, the S.S. increases with drain voltage due to channel shortening effect such as charge sharing, avalanche multiplication and punchthrough effect. The sub-threshold slope is also related to gate voltage due to undesirable and inevitable factors such as the serial resistance and interface states.
In this thesis, the S.S. is defined as one-third of the gate voltage required to decrease the threshold current by three orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to threshold voltage.
3.1.3 Determination Of Field Effect Mobility
Usually, field effect mobility (µeff) is determined from the maximum value of transconductance (Gm) at low drain bias. The transfer characteristics of Poly-Silicon TFTs are similar to those of conventional MOSFETs, so that the first order of I-V
Therefore, the field-effect mobility is
(max) →0
3.1.4 Determination Of ON/OFF Current Ratio
On/Off current ratio is one of the most important parameters of Poly-Silicon TFTs since a high-performance device exhibits not only a large on-current but also a small off-current (leakage current). The leakage current mechanism in Poly-Silicon TFTs is not like that in MOSFET. In MOSFET, the channel is composed of single crystalline Si and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. However, in Poly-Silicon TFTs, the channel is composed of Poly-Silicon. A large amount of trap state densities in grain structure attribute a lot of defect states in energy band gap to enhance the tunneling effect. Therefore, the leakage current is much larger in Poly-Silicon TFTs than in MOSFET. When the voltage drops between gate voltage and drain voltage increases, the band gap width decreases and the tunneling effect becomes much more severe. Normally we can find this effect in typical Poly-Silicon TFTs’ IDS-VGS characteristics where the magnitude of leakage current will reach a minimum and then increase as the gate voltage decreases/increases for n/p-channel TFTs.
There are a lot of ways to specify the on and off-current. In this chapter, take n-channel Poly-Silicon TFTs for examples, the on-current is defined as the drain current when gate voltage at the maximum value and drain voltage is 0.1V. The off-current is specified as the minimum current when drain voltage equals to 0.1V.
V
3.2 Experimental Data Result & Discussion
The fabricated devices were characterized using HP4156 and HP4284 Precision Semiconductor Parameter Analyzer. We first show the data of NMOS-TFT (Yb / LaAlO3). The Id-Vg characteristics of a representative TFT are shown in Fig. 3.1. The threshold voltage is 0.85 V which is better than the threshold voltage of the device with aluminum gate which we reported before ( 1.2 V, Fig 3.2 ). The threshold voltage decreases because that Ytterbium 2.6 eV) makes the lower φms. Base on the
threshold voltage equation: ms fp
ox density, and is consistent with the good electron field-effect mobility of 31.4 cm2/Vs which is showed in Fig 3.4. This is because the sputtering and subsequent 400oC oxidation also oxidized the poly-silicon surface. Although this is the undesired feature in high κ CMOS to lower down the EOT [28-31], the good high-κ /Ytterbium interface gives the not bad mobility and good sub-threshold slope. The Ion / Ioff ratio of the Ytterbium/LaAlO3 TFT is 1.63×106, even without performing hydrogen passivation.
And then the output characteristics (Id-Vd) of the Ytterbium/LaAlO3 TFT are shown in Fig. 3.5. The large drive current of 22 µA/µm, at 5 V, is attractive for
high-speed display ICs. This good performance is related to the lower threshold voltage and the high gate-capacitance of 3.9×10-7 F/cm2 from C-V measurements (Fig 3.6), which gives a small equivalent-oxide thickness (EOT) of 8.7 nm at a κ value of ~22.5 [28][29] This is the thinnest reported EOT TFTs so far [32-35], And the high drive current is higher than our past reported Al/LaAlO3 (EOT=8.7 nm) thin film transistor, which is showed in Fig 3.7~3.13. It is because the work-function of Al eV) is higher than that of Yb 2.6 eV). So the data affirm our conception. Our design also provides an alternative way to create high drive current, along with existing approaches such as excimer-laser crystallization (ELC) [32][36-38], metal-induced lateral crystallization [39] and electric field enhanced crystallization [40]. It shows that good uniformity is also obtained due to the furnace crystallization, in contrast with the narrow process window and poor uniformity in ELC TFTs [41].
The field dependence of the gate current density is showed in Fig 3.14 shows a gate dielectric breakdown voltage of 31-32 V. This corresponds to an electric field of 6.25 MV/cm that is slightly larger than PECVD TEOS oxide of 5.4 MV/cm[35]. This is high enough to drive a liquid crystal display. This high breakdown field is comparable with or better than that for PECVD TEOS oxide [32-34][42]. This is important for achieving good dielectric reliability [28-31]. It may arise from the plasma-free process used, which does not damage the gate dielectric.
Figure 3.15 shows the charge-trapping characteristics of the Ytterbium/LaAlO3 TFTs under constant-current stress from 0.1 to 10 mA/cm2 (or ~2.9 to 5.8 MV/cm electric field ). The gate voltage shift is only 0.61 V even under 10 mA/cm2 stress, which is much better than the 2.2 V shift in TEOS oxide TFTs under the same stress
condition [43]. Such low charge-trapping indicates the good quality of the gate dielectric and is consistent with high – κLaAlO3 CMOSFETs also fabricated at low temperature [28-29] and good intersurface between metal gate and high – gate dielectric. Hence integrating high- κ gate dielectrics with Ytterbium metal gate into TFT-NMOS should not degrade the TFT device reliability, often dominated by the grain-boundary related hot-carrier degradation[44]
The important device parameters are summarized in Table 1, where the data from devices using PVD LaAlO3 with Al gate, LPCVD SiO2 with poly-silicon gate, PECVD TEOS oxides [33-35] with poly-silicon gate and Al2O3 gate dielectric with Poly-SiGe gate [45]are also shown for comparison. The better device performance of the Ytterbium/LaAlO3 TFTs that compared with LPCVD, PECVD TEOS oxide TFTs (using the same furnace-crystallization process) and relative low – κAl2O3 devices, is due to the lower threshold voltage which results from the higher capacitance density combining with low work-function Ytterbium metal gate (Vth= φms + Qtotal/Cdielectric), and the plasma-free process.
Gate
electrode Ytterbium Aluminum Poly-Si Poly-Si Poly-Si Poly-SiGe
Vth (V) 0.85 1.2 5.6 8.14 Not
The primary parameter comparison of different structure thin film transistor
-2 -1 0 1 2 3 4 5 6
Fig 3.1 The threshold voltage of Yb/LaAlO3 thin film transistor
-2 0 2 4 6
Fig 3.2 The threshold voltage of Al/LaAlO3 thin film transistor
-4 -2 0 2 4 6 8
10
-1110
-910
-710
-510
-3D ra in C ur re nt (A )
Gate Voltage (V)
Unhydrogenated poly-Si TFT W/L=100 µµµµm/4 µµµµm
Vd=0.1 V
subthreshold slope=0.58 V/decade
Fig 3.3 The low subthreshold slope of Yb/LaAlO3 thin film transistor
-4 -2 0 2 4 6 8 0
10 20 30 40 50 60 70
80 Unhydrogenated poly-Si TFT W/L=100
µµµµm/4
µµµµm
Fi el d M ob ili ty (c m
2/V s)
Drain Voltage (V) 3.3V
31.4 cm
2/Vs
Vd=0.1V
Fig 3.4 The mobility of Yb/LaAlO3 thin film transistor
0 1 2 3 4 5 0.0
0.5 1.0 1.5 2.0 2.5 3.0
VG=5 V
VG=3 V
D ra in C ur re nt (m A )
Drain Voltage (V)
VG=1 V Unhydrogenated poly-Si TFT
W/L=100 µµµµm/4 µµµµm
Fig 3.5 The drain current of Yb/LaAlO3 thin film transistor at different voltage
-4 -3 -2 -1 0 1 0.00
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
C ap ac ita nc e ( µµµµ F/ cm
2)
Bias (V)
LaAlO3 with 400oC 30 min O2 treatment
∆∆∆∆Vhys =
< 70 mV
Fig 3.6 The C-V measurements of Yb/LaAlO3 thin film transistor
0 1 2 3 4 5
Fig 3.7 The drain current of Al/LaAlO3 thin film transistor at Vg=1V
0 1 2 3 4 5
Fig 3.8 The drain current of Yb/LaAlO3 thin film transistor at Vg=1V
0 1 2 3 4 5
Fig 3.9 The drain current of Al/LaAlO3 thin film transistor at Vg=3V
0 1 2 3 4 5
Fig 3.10 The drain current of Yb/LaAlO3 thin film transistor at Vg=3V
0 1 2 3 4 5
Fig 3.11 The drain current of Al/LaAlO3 thin film transistor at Vg=5V
0 1 2 3 4 5
Fig 3.12 The drain current of Yb/LaAlO3 thin film transistor at Vg=5V
0 1 2 3 4 5 0.0
0.5 1.0 1.5 2.0 2.5
D ra in C ur re nt (m A )
Drain Voltage (V)
Yb(VG=1V) Al(VG=1V) Yb(VG=3V) Al(VG=3V) Yb(VG=5V) Al(VG=5V)
Fig 3.13
The comparison of drain current at different gate voltage between Yb-gate and Al-gate
0 1 2 3 4 5 6 7 8
10
-810
-710
-610
-510
-410
-310
-210
-110
00 5 10 15 20 25 30 35 40
Electric Field (MV/cm) C ur re nt D en si ty (A /c m
2)
Fig 3.14 The breakdown voltage of Yb/LaAlO3 thin film transistor
0 50 100 150 200 250 300 0.0
0.2 0.4 0.6 0.8 1.0
G at e V ol ta ge s hi ft (V )
Stress Time (sec)
10 mA/cm2 stress 1 mA/cm2 stress 100 µµµµA/cm2 stress
Fig 3.15 The gate voltage shift of Yb/LaAlO3 thin film transistor
4. Conclusion
We have fabricated and characterized high-performance LTPS TFTs-NMOS
which incorporate high- κ LaAlO3 dielectric with low work-function Ytterbium
metal gate that provides good dielectric properties such as a high breakdown field,
low threshold voltage, low leakage current and low charge trapping rate. These
devices exhibit excellent electrical characteristics and high drive current, even without
special process steps. We can expect that we may achieve better performance by using
hydrogenation passivation or excimer laser crystallization process steps to improve
the trap density on interface or get high quality Poly-Silicon film. And we will keep
the same conception on TFTs-PMOS by using higher work-function metal such as the
second highest work-function metal, Iridium. We do not expect to use Pt (The highest
work-function metal) because that it is difficult to be etched in process.. And finally,
we may integrate this high performance device for drive circuit on panel that realizes
SOP ( System On Panel ).
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