Experimental Data Result & Discussion

The fabricated devices were characterized using HP4156 and HP4284 Precision Semiconductor Parameter Analyzer. We first show the data of NMOS-TFT (Yb / LaAlO₃). The I_d-V_g characteristics of a representative TFT are shown in Fig. 3.1. The threshold voltage is 0.85 V which is better than the threshold voltage of the device with aluminum gate which we reported before ( 1.2 V, Fig 3.2 ). The threshold voltage decreases because that Ytterbium 2.6 eV) makes the lower φ_ms. Base on the

threshold voltage equation: _{ms fp}

ox density, and is consistent with the good electron field-effect mobility of 31.4 cm²/Vs which is showed in Fig 3.4. This is because the sputtering and subsequent 400^oC oxidation also oxidized the poly-silicon surface. Although this is the undesired feature in high κ CMOS to lower down the EOT [28-31], the good high-κ /Ytterbium interface gives the not bad mobility and good sub-threshold slope. The Ion / Ioff ratio of the Ytterbium/LaAlO3 TFT is 1.63×10⁶, even without performing hydrogen passivation.

And then the output characteristics (Id-Vd) of the Ytterbium/LaAlO3 TFT are shown in Fig. 3.5. The large drive current of 22 µA/µm, at 5 V, is attractive for

high-speed display ICs. This good performance is related to the lower threshold voltage and the high gate-capacitance of 3.9×10^-7 F/cm² from C-V measurements (Fig 3.6), which gives a small equivalent-oxide thickness (EOT) of 8.7 nm at a κ value of ~22.5 [28][29] This is the thinnest reported EOT TFTs so far [32-35], And the high drive current is higher than our past reported Al/LaAlO3 (EOT=8.7 nm) thin film transistor, which is showed in Fig 3.7~3.13. It is because the work-function of Al eV) is higher than that of Yb 2.6 eV). So the data affirm our conception. Our design also provides an alternative way to create high drive current, along with existing approaches such as excimer-laser crystallization (ELC) [32][36-38], metal-induced lateral crystallization [39] and electric field enhanced crystallization [40]. It shows that good uniformity is also obtained due to the furnace crystallization, in contrast with the narrow process window and poor uniformity in ELC TFTs [41].

The field dependence of the gate current density is showed in Fig 3.14 shows a gate dielectric breakdown voltage of 31-32 V. This corresponds to an electric field of 6.25 MV/cm that is slightly larger than PECVD TEOS oxide of 5.4 MV/cm[35]. This is high enough to drive a liquid crystal display. This high breakdown field is comparable with or better than that for PECVD TEOS oxide [32-34][42]. This is important for achieving good dielectric reliability [28-31]. It may arise from the plasma-free process used, which does not damage the gate dielectric.

Figure 3.15 shows the charge-trapping characteristics of the Ytterbium/LaAlO₃ TFTs under constant-current stress from 0.1 to 10 mA/cm² (or ~2.9 to 5.8 MV/cm electric field ). The gate voltage shift is only 0.61 V even under 10 mA/cm² stress, which is much better than the 2.2 V shift in TEOS oxide TFTs under the same stress

condition [43]. Such low charge-trapping indicates the good quality of the gate dielectric and is consistent with high – κLaAlO3 CMOSFETs also fabricated at low temperature [28-29] and good intersurface between metal gate and high – gate dielectric. Hence integrating high- κ gate dielectrics with Ytterbium metal gate into TFT-NMOS should not degrade the TFT device reliability, often dominated by the grain-boundary related hot-carrier degradation[44]

The important device parameters are summarized in Table 1, where the data from devices using PVD LaAlO₃ with Al gate, LPCVD SiO₂ with poly-silicon gate, PECVD TEOS oxides [33-35] with poly-silicon gate and Al₂O₃ gate dielectric with Poly-SiGe gate [45]are also shown for comparison. The better device performance of the Ytterbium/LaAlO3 TFTs that compared with LPCVD, PECVD TEOS oxide TFTs (using the same furnace-crystallization process) and relative low – κAl2O3 devices, is due to the lower threshold voltage which results from the higher capacitance density combining with low work-function Ytterbium metal gate (Vth= φ_ms + Qtotal/Cdielectric), and the plasma-free process.

Gate

electrode Ytterbium Aluminum Poly-Si Poly-Si Poly-Si Poly-SiGe

Vth (V) 0.85 1.2 5.6 8.14 Not

The primary parameter comparison of different structure thin film transistor

-2 -1 0 1 2 3 4 5 6

Fig 3.1 The threshold voltage of Yb/LaAlO3 thin film transistor

-2 0 2 4 6

Fig 3.2 The threshold voltage of Al/LaAlO3 thin film transistor

-4 -2 0 2 4 6 8

10

^-11

10

^-9

10

^-7

10

^-5

10

^-3

D ra in C ur re nt (A )

Gate Voltage (V)

Unhydrogenated poly-Si TFT W/L=100 µµµµm/4 µµµµm

V_d=0.1 V

subthreshold slope=0.58 V/decade

Fig 3.3 The low subthreshold slope of Yb/LaAlO3 thin film transistor

-4 -2 0 2 4 6 8 0

10 20 30 40 50 60 70

80 Unhydrogenated poly-Si TFT W/L=100

µµµµ

m/4

µµµµ

m

Fi el d M ob ili ty (c m

2

/V s)

Drain Voltage (V) 3.3V

31.4 cm

²

/Vs

Vd=0.1V

Fig 3.4 The mobility of Yb/LaAlO3 thin film transistor

0 1 2 3 4 5 0.0

0.5 1.0 1.5 2.0 2.5 3.0

V_G=5 V

V_G=3 V

D ra in C ur re nt (m A )

Drain Voltage (V)

V_G=1 V Unhydrogenated poly-Si TFT

W/L=100 µµµµm/4 µµµµm

Fig 3.5 The drain current of Yb/LaAlO3 thin film transistor at different voltage

-4 -3 -2 -1 0 1 0.00

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

C ap ac ita nc e ( µµµµ F/ cm

2

)

Bias (V)

LaAlO3 with 400oC 30 min O2 treatment

∆∆∆∆V_hys =

< 70 mV

Fig 3.6 The C-V measurements of Yb/LaAlO3 thin film transistor

0 1 2 3 4 5

Fig 3.7 The drain current of Al/LaAlO3 thin film transistor at Vg=1V

0 1 2 3 4 5

Fig 3.8 The drain current of Yb/LaAlO3 thin film transistor at Vg=1V

0 1 2 3 4 5

Fig 3.9 The drain current of Al/LaAlO3 thin film transistor at Vg=3V

0 1 2 3 4 5

Fig 3.10 The drain current of Yb/LaAlO3 thin film transistor at Vg=3V

0 1 2 3 4 5

Fig 3.11 The drain current of Al/LaAlO3 thin film transistor at Vg=5V

0 1 2 3 4 5

Fig 3.12 The drain current of Yb/LaAlO3 thin film transistor at Vg=5V

0 1 2 3 4 5 0.0

0.5 1.0 1.5 2.0 2.5

D ra in C ur re nt (m A )

Drain Voltage (V)

Yb(VG=1V) Al(VG=1V) Yb(VG=3V) Al(VG=3V) Yb(VG=5V) Al(VG=5V)

Fig 3.13

The comparison of drain current at different gate voltage between Yb-gate and Al-gate

0 1 2 3 4 5 6 7 8

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

0 5 10 15 20 25 30 35 40

Electric Field (MV/cm) C ur re nt D en si ty (A /c m

2

)

Fig 3.14 The breakdown voltage of Yb/LaAlO3 thin film transistor

0 50 100 150 200 250 300 0.0

0.2 0.4 0.6 0.8 1.0

G at e V ol ta ge s hi ft (V )

Stress Time (sec)

10 mA/cm² stress 1 mA/cm² stress 100 µµµµA/cm² stress

Fig 3.15 The gate voltage shift of Yb/LaAlO3 thin film transistor

4. Conclusion

We have fabricated and characterized high-performance LTPS TFTs-NMOS

which incorporate high- κ LaAlO₃ dielectric with low work-function Ytterbium

metal gate that provides good dielectric properties such as a high breakdown field,

low threshold voltage, low leakage current and low charge trapping rate. These

devices exhibit excellent electrical characteristics and high drive current, even without

special process steps. We can expect that we may achieve better performance by using

hydrogenation passivation or excimer laser crystallization process steps to improve

the trap density on interface or get high quality Poly-Silicon film. And we will keep

the same conception on TFTs-PMOS by using higher work-function metal such as the

second highest work-function metal, Iridium. We do not expect to use Pt (The highest

work-function metal) because that it is difficult to be etched in process.. And finally,

we may integrate this high performance device for drive circuit on panel that realizes

SOP ( System On Panel ).

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Vita

Studies Of High Performance Metal Gate Low Temperature Poly-Silicon Thin Film Transistor.

在文檔中 高性能金屬閘極低溫多晶矽薄膜電晶體之研究 (頁 36-0)