Chapter 1 Introduction
1.2 Thesis Overview…
This thesis covers theoretical analysis of the CT ΔΣ modulator and the method of the CT loop filter from its DT function. After discussing the design issues of the CT ΔΣ modulator as well as the solutions, the detailed design procedure of the prototype modulator are presented. The thesis is organized as following:
Chapter 2 reviews some basic concepts about ΔΣ ADCs to help understand the rest of the thesis.
Chapter 3 describes the equivalence between the DT and CT loop filters in terms of impulse-invariant transformation (IIT). Besides, effects of various non-idealities and potential solutions to deal with them are discussed.
Chapter 4 proposes a CT ΔΣ modulator using feedback resistors. The system level design procedure which combines many aspects of the design considerations and detailed circuit level design are discussed.
Chapter 5 presents a CT ΔΣ modulator we propose. We also show the system
level design procedure which combines many aspects of the design considerations and circuit design of this CT ΔΣ modulator.
Chapter 6 covers the issues of test board design as well as the chip evaluation work.
Chapter 7 concludes the thesis and discusses some future work.
In this chapter, we describe some basic background knowledge about ΔΣ ADCs.
The concepts of quantization, oversampling and noise-shaping are introduced and illustrated with examples. The tradeoffs of the various sigma-delta modulator architectures will be discussed.
2.1 Sampling and Quantization
In order to properly interface the analog world which is composed of continuous-time signal (e.g. voice, audio or video) with the digital signal processor which can only process discrete-time signal, analog-to-digital conversion is required.
We describe it into two basic operations: uniform sampling in time and quantization in amplitude.
Under the assumption that the signal information of the continuous input waveform u t is contained in the signal band, i.e.,( ) fs i g £ fB , where f is B defined as the signal bandwidth, the sampling in time is a completely invertible process. This is easily understood when considering a quantization in time as a periodization in frequency [1], which is illustrated in Fig. 2.1. There, the considered input signal is sampled at uniform time intervalsT , the sampling time, or with a S fixed frequency, f , resulting in a periodicity of the original signal S
Fig. 2.1 The sampling spectral
spectrum at multiples of f . From Fig. 2.1 it is obvious that by sample low-pass S filtering, the original base-band spectrum can be reconstructed, provided that the sampling itself does not result in overlap or aliased regions. This is achieved when:
S 2 B N
f ³ f = f (2.1)
which is known as the Nyquist theorem, where fN is the Nyquist frequency. To assure a proper sampling operation, the condition in (2.1) is enforced by an analog filter preceding the sampling operation, called the antialiasing filter (AAF).
a
fS fS
Fig. 2.2 Analog-to-digital conversion
The basic ADC structure is shown in Fig. 2.2. An ADC working with a distortion. Therefore, many ADCs work with sampling rates higher than fN , and one defines: as the oversampling ratio of the ADC.
The process of quantization in amplitude, usually referred to as the quantization, encodes a continuous range of analog values into a set of discrete levels. The quantizer is assumed to be a memoryless nonlinear device completely defined by its static input-output characteristics, i.e., by its y-v transfer curve. An example of such a curve is shown in Fig. 2.3(a), where the number of quantization level is 4 which can be represented by a 2-digit binary code, and the difference of two adjacent quantized values Δ is the same as the difference between input thresholds, also known as least-significant bit size or LSB size, given by VLSB. The difference between the lowest and the highest levels is called the full-scale (FS) of the quantizer, given by 2VRef. The deviation between the sampled input and the quantized output is called the quantization error, or the quantization noise. Fig. 2.3(b) shows the relationship between the quantization noise q and the input y. From this figure, it can be seen that as long as y is between –( VRef + VLSB/2 ) and +( VRef + VLSB/2 ), the error q is between －VLSB/2 and +VLSB/2. The range of y where this condition is satisfied is called the non-overload input range. For an N bit ADC, the
quantization step as well as the LSB size is given by Δ ＝ VLSB ＝FS/(2N-1), which is in the case 2VRef /3.
The ideal quantizer is a deterministic device. The output v and hence the error q are fully determined by the input y. However, under certain circumstances, for example, if the input y stays within the non-overload input range of the quantizer, and changes by sufficiently large amounts from sample to sample so that its position within a quantization interval is essentially random, then it is permissible to assume
v
y
Ref
Ref LSB
y q=v-y
Ref Ref +VLSB/2
-VLSB/2
Fig. 2.3 (a) Transfer curve and (b) error function of a 4-level quantizer
that q is a white noise process with samples uniformly distributed between － VLSB/2 and +VLSB/2. The probability density function (PDF) and power spectral density (PSD) of the quantization noise are shown in Fig. 2.4.
Fig. 2.4 (a) Probability density function of quantization noise (b) power spectral density of quantization noise
The impact of the quantization noise on the ADC’s performance can be found by calculating its maximum signal-to-quantization-noise ratio (SQNR). This parameter is obtained by dividing the power of a sinusoidal input signal by the power of the quantization noise. The power of a sinusoidal signal is given by Amp2/2, where Amp is the amplitude of the signal. The power of the quantization noise is given in (2.3).
To get the SQNR, Amp should be equal to half of the non-overload input range of the quantizer, which is VRef+VLSB/2. performance of the data converter.
[ ] 1 0 l o g1 0 6 . 0 2 1 . 7 6
S Q N R d B = S Q N R = N + (2.5)
2.2 Oversampling
A way to calculate the power of the quantization noise is to integrate the power spectral density over the full bandwidth which we interest:
2 2
Now, the power of the in-band quantization noise is given in (2.7).
2
f , is called oversampling ratio which is one of the most important parameters used to characterize the oversampling data converters. The power of input signal is not modified since it is assumed that it has no frequency content above f . Therefore, the maximum SQNR is given by: B
[ ] 6 . 0 2 1 . 7 6 1 0 l o g
S Q N R d B = N + + O S R (2.8)
It is obvious that if the sampling rate is equal to twice the Nyquist rate (OSR = 2), the SQNR is improved by 3 dB. (2.8) shows that oversampling can improve the SQNR with the OSR at a rate of 3 dB/octave, or 0.5 bit/octave [2].
2.3 Noise Shaping
In the previous section, we show that oversampling can be used to trade speed for resolution of ADC. It is noticed that the quantization noise in previous section has a flat power spectral density over the full bandwidth [- fS / 2 , fS / 2 ] . A more efficient way to use oversampling is to shape the spectral density such that most of the quantization noise power is outside the band of interest. A general noise-shaped sigma-delta modulator and its linear model have been shown in Fig.
2.6.
Fig. 2.6 (a) A general noise-shaping delta-sigma modulator (b) Linear model of the modulator showing injected quantization noise
Treating the linear model shown in Fig. 2.6 as having two independent inputs, u n and ( ) e n , we can derive a signal transfer function ( ) S T F z , and a ( ) noise transfer function N T F z . ( )
( ) ( ) the zeros of the noise transfer function by choosing the function of the loop filter.
We can also using super position to combine two signals, and find out the output as
( ) ( ) ( ) ( ) ( ) noise-shaping strategy [3]. The quantization noise over the frequency band which we interest will be reduced and do not affect the input signal. This would improve the SNR significantly for overall system.
2.3.1 First-Order Delta-Sigma Modulator
x
Quantizer
y
Fig. 2.7 The block diagram of the first-order low-pass delta-sigma modulator
In Fig. 2.7, it is a block diagram of the first-order low-pass delta-sigma modulator. It includes an integrator and a quantizer. The input of the integrator is the input signal minus the output signal of the modulator through the DAC. In this example, since the loop filter is a high-pass filter, the noise function should have a zero at dc (i.e., z = 1). The transfer function of the discrete-time integrator (i.e., have a pole at z = 1) is
( ) 1 H z 1
= z
- (2.12) Its block diagram for such a choice is shown in Fig. 2.8.
Fig. 2.8 First-order delta-sigma modulator
According to (2.9) and (2.10), we can obtain the signal transfer function
Combining the two signal transfer function, we can obtain the output as
1 1
( ) ( ) (1 ) ( )
Y z = z U- z + - z- E z (2.15) We see that the input signal is just a delay through the input to the output, and the quantization noise is through a discrete-time differentiator (i.e., a high-pass filter) to the output. We are interesting in the magnitude of the noise transfer function, Taking the magnitude of both sides, we have the high-pass function
( ) 2 s i n ( ) bandwidth we interest as below
2 ( ) ( ) 2 having maximum amplitude. We can obtain as
2 3
We can see that the first-order noise shaping can give an SNR improvement for 9 dB or 1.5 bits by doubling the OSR. This result should be compared to the 0.5 bits/octave when oversampling with no noise shaping.
2.3.2 Second-Order Delta-Sigma Modulator
Fig. 2.9 The block diagram of the second-order low-pass ΔΣ modulator
The second-order low-pass delta-sigma modulator is shown in Fig. 2.9. and the signal is just a delay to output. The signal transfer function is given by
( ) 1
S T F f = z - (2.23) Combining the two signal transfer function, we can obtain the output as
1 1 2
( ) ( ) (1 ) ( )
Y z = z U- z + - z - E z (2.24)
The same as before, we interest in the magnitude of the noise transfer function interest and using the approximation, we can get the result:
2 ( ) ( ) 2
We can see that the second-order noise shaping can give an SNR improvement for 15 dB or 2.5 bits by doubling the OSR.
Fig. 2.10 shows the noise-shaping curves compared with shape of zero-, first-, second- and third-order. The noise power decreases as the noise-shaping order increases over the band which we interest. But the out-of-band noise power increases for the higher-order modulators.
0 0.1 0.2 0.3 0.4 0.5
Fig. 2.10 Different order noise shaping curves
2.3.3 High-Order Delta-Sigma Modulator
As mentioned before, we extend the delta-sigma modulator to L order, and get the noise transfer function interest and using the approximation, we can get the result:
2 ( ) ( ) 2
2.11 shows the SQNR tradeoff between order and OSR.
4 8 16 32 64 128 256
Fig. 2.11 Empirical SQNR limit for 1-bit modulators of order N
In this chapter, we illustrate the procedure to choose the feedback DAC pulse shapes and design the loop filter function for CT ΔΣ modulator. Besides, various non-idealities will affect the performance, even the stability of the CT ΔΣ modulator.
These non-idealities, including finite OpAmp gain and gain-bandwidth, excess loop delay, element mismatch in the multi-bit feedback DAC and clock jitter, would be analyzed in detail.
3.1 DT to CT Conversion of ΔΣ Modulator
3.1.1 Impulse-Invariant Transformation
The quantizer in a CT ΔΣ modulator is clocked, that is, there is an implicit sampling action inside the modulator. Because sampled circuits are DT circuits, we can make the sampling explicit by placing the sampler immediately prior to the quantizer without changing the behavior of the modulator, as Fig. 3.1 shown. As mentioned above, the two modulators are equivalent if their quantizers have the same inputs at each sampling instant, which means
( ) ( ) |
C t n TS
x n = x t = (3.1)
H(z)
Fig. 3.1 The loop filter representation for (a) DT modulator and (b) CT modulator
This can be satisfied if the open loop impulse responses are the same at sampling instants, which can be written as
{ } { }
In the time domain, this leads to the condition
( ) ( ) ( ) | response equal at the sampling times.
(a)
Fig. 3.2 DAC feedback impulse response (a) NRZ (b) RZ (c) HRZ
3.1.2 Synthesis of CT ΔΣ Feedback DAC
To actually perform the Impulse Invariant Transformation, the continuous-time DAC feedback pulse shape has to be decided first. Different pulse shapes result in different transformations between the DT and CT modulators. We will shortly discuss their practical advantages. There are three commonly used rectangular DAC feedback pulses: non-return-to-zero (NRZ), return-to-zero (RZ) and half-delay-return-to-zero (HRZ) [5]. Their impulse responses are shown in Fig.
3.2. DACs with NRZ shapes provide constant output over a full period; DACs with RZ shapes produce constant valid output only from 0 to T/2 and DACs with HRZ produce a half clock cycle delayed version of RZ. The transfer function of NRZ, RZ and HRZ can be described by the same equation:
e x p ( ) e x p ( )
where α and β are valid feedback starting and ending times respectively, so we have
0 ,
After determining the DAC feedback pulse shape and its transfer function, the impulse invariant transform can be executed following the steps below. At first, we will write H ( )z as a partial fraction expansion. Following, we convert each
partial fraction from z-domain to s-domain. At the last, we recombine the results from step 2 to get H C ( )s [6].
3.2 Non-idealities in ΔΣ Modulator
3.2.1 Non-idealities in CT Integrators
OP Gm
Fig. 3.3 (a) Active-RC (b) Gm-C integrators
The basic circuit blocks of a CT loop filter are the CT integrators. Many kinds of CT integrators are available but the most commonly used are active-RC integrators and Gm-C integrators, as shown in Fig. 3.3.
The advantages of the active-RC integrators over the Gm-C counterparts include higher linearity and larger input signal swing. Because the active-RC integrators are based on the closed loop applications of the operational amplifiers (OpAmps), the OpAmp’s inputs are virtual ground and only experience very small signal swing regardless of the integrator’s input. On the contrary, the transconductor, which performs voltage-to-current (V-I) transformation with a known
0 2 4 6 8 10
Fig. 3.4 The GBW requirement of the OpAmp in the integrator
transconductance, operates under the open-loop condition in the Gm-C integrators, so its inputs have to experience the full swing of the integrator’s input, which degrades the linearity of the integrator. Due to this reason, the input signal of the Gm-C integrator has to be small enough to keep a reasonable linearity. When using active-RC integrators to build a CT ΔΣ modulator, the virtual ground provided by the closed loop OpAmp application will also greatly improve the linearity of the feedback current DAC whose outputs are connected with the inputs of the OpAmp.
However, in a CT ΔΣ modulator based on Gm-C integrators, the feedback DAC’s outputs have to be connected with the output of the integrator and hence experience the full output swing, which degrades the linearity of the DAC.
As shown in Fig. 3.4, we find “the gain-bandwidth requirement of the OpAmp in the integrator of the CT ΔΣ modulator is two times as high as the sampling frequency or similar”. Therefore, the relative bandwidth normalized to
/
Table 3.1 Overview of various advantages and drawbacks of various CT integrator approaches
Gm-C Active-RC MOSFET-C
Frequency Range ☆☆☆☆ ☆☆☆ ☆☆
On the other hand, due to the same open loop working condition, the GBW of the Gm-C integrator is integrator will be lower for a given bandwidth requirement.
A qualitative overview is given in Table 3.1 [6]. The log approach shows advantages, if low voltage capability and power consumption are of high interest while the desired frequency range is limited to a few MHz. If a higher frequency range is additionally demanded in connection with a high linearity, the active-RC integrator is the preferred structure. For linearity requirements limited to about
6 0
T H D = - d B , Gm-C integrators are favorable, if low power is a major interest [6].
According to the above analysis, the active-RC integrator is preferred as the first stage integrator, and following are Gm-C integrators to save power.
3.2.2 Finite OpAmp Gain and Gain-Bandwidth
Operational amplifiers (OpAmps) are the basic blocks of the active-RC integrators. An ideal opamp can be seen as a voltage-controlled voltage source whose voltage gain is infinitely large across the whole frequency domain. However, a real opamp has a finite DC gain and several poles and zeros in its transfer function.
In analysis, we assume an OpAmp be a single pole system and the model is given by: Besides, the unity gain bandwidth of the OpAmp can be express as:
D C A
Fig. 3.5 The active-RC integrator with single pole OpAmp
As shown in Fig. 3.5, the integrator transfer function (ITF) from one input to the output can be expressed as:
( ) 1 for a given feedback DAC waveform in the section 3.1.2, it is assumed that there is no delay time between the sampling instant of the loop filter output and the generation of new output digital codes. However, in the real circuits, due to the finite speed of transistors, this delay known as excess loop delay could not be zero.
The excess loop delay usually consists of the delays introduced by the quantizer (including the dynamic element matching (DEM) logic if necessary), feedback DAC,
(a)
Fig. 3.6 DAC feedback impulse response including Excess Loop Delay (a) NRZ (b) RZ (c) HRZ
and loop filter. Considering the feedback DAC, the impulse response of those three rectangular DAC pulses shown in Fig. 3.2 is changed to be that in Fig. 3.6.
As analyzed in [5], if the falling edge of the DAC pulse exceeds the time instant T , the order of the equivalent DT loop filter of the CT one is higher by S one than under ideal conditions, which makes the CT modulator uncontrolled. The excess loop delay degrades the dynamic range of the modulator by reducing the effectiveness of the noise shaping as well as the maximum stable input signal swing.
If the excess loop delay is too large compared with the clock period, the CT modulator will be unstable.
In order to compensate the excess loop delay, the RZ pulse can be used as the DAC waveform. As shown in Fig.3.6 (b), it can be seen that if the excess loop delay is smaller than half clock period, then the falling edge is still within the range 0 ~ T , and hence the equivalent DT loop filter has the same order of the CT one. S However, in most CT ΔΣ modulators, the NRZ DAC pulse is superior to the RZ (or HRZ) counterpart in terms of the clock jitter sensitivity issue. In addition, because the exact value of the excess loop delay t is unknown while synthesizing the CT d loop filter, the resulting CT modulator still cannot realize the same noise shaping as
In 2
Fig. 3.7 Continuous-Time ΔΣ modulator with zero-order loop compensation
the DT target even using RZ DAC pulse.
While using NRZ DAC pulse, a common solution to the excess loop delay is to introduce a full clock delay in the feedback path to absorb the varying quantizer delay as well as the other delays, as shown in Fig. 3.7. However, due to this full clock delay, the impulse response of the CT loop at the sampling instant T is S zero. To compensate this response sample, an extra feedback branch is added directly to the quantizer input to make the total impulse response equivalent to the DT function [7]. Because the loop formed by the extra feedback branch doesn’t include any integrator, we call it zero-order loop compensation.
3.2.4 Clock Jitter
In the DT ΔΣ modulator, the continuous-time signal is sampled at the modulator input, so the sampling error caused by the clock jitter is directly added to the output without any attenuation. However, the sampling action in the CT ΔΣ modulator happens at the input of the quantizer, so the jitter-induced error is shaped
In the DT ΔΣ modulator, the continuous-time signal is sampled at the modulator input, so the sampling error caused by the clock jitter is directly added to the output without any attenuation. However, the sampling action in the CT ΔΣ modulator happens at the input of the quantizer, so the jitter-induced error is shaped