Chapter 4 A Continuous-Time Delta-Sigma Modulator Using Feedback
4.5 Circuit Level Simulation
The circuit level results are simulated by Hspice. The captured output digital data is windowed by a Hann window and a Fourier transformation is applied using Matlab. The spectra resulting (16384 bins from 0 to FS) from -6 dB 94.6 kHz input signal can be seen in Fig. 4.15. The total power consumption is 13.6 mW. The finial specifications are summarized in Table 4.3. The chip photo is shown in Fig.
4.16. The total area, including pad is 1.14 x 0.945 mm2.
104 105 106 107
-140 -120 -100 -80 -60 -40 -20 0
SNDR (dB)
Frequency (Hz)
Fig. 4.15 The circuit simulation of this work using feedback resistors
Fig. 4.16 Chip photo of this work using feedback resistors
Table 4.3 Summary of circuit level simulation results Specification Simulation Results
Technology TSMC 0.18μm 1P6M
Signal bandwidth 1 MHz
Sampling frequency 100 MHz
SNDR 67.3 dB
SFDR 78 dB
ENOB 11
Power Supply 1.8 V
Power Dissipation 13.6 mW
Chip area (with pad) 1.14 mm x 0.945 mm
In this chapter, the system level and circuit level design of our second chip is presented in detail, which includes the determination of the system level parameters, and the system level simulations with non-idealities. After that, the circuit blocks would be discussed and the modulator is realized with a 0.13 μm CMOS technology and 1.2 V power supply voltage.
5.1 System Level Design
In this second work, the target is to successfully design a CT ΔΣ modulator to reach 63 dB SNDR (signal-to-noise-and-distortion-ratio) within a 2 MHz bandwidth (BW) in a 0.13 μm mixed-signal CMOS process.
For this second work, the clock jitter sensitivity is still the important specification. It will significantly affect the selection of the system level parameters.
Therefore, we still assume that the modulator will be evaluated with a clock signal generated by the instrument and determine the RMS value of the target jitter tolerance is 20 ps. Here, for lower power consumption and clock jitter sensitivity, we choose 13 as our OSR value.
For this design, we determine the number of the quantizer be eight. On the other hand, we also choose 3 as the loop order. The aggressiveness of the noise shaping is also limited by the stability issue. In addition, the real input amplitude cannot reach the peak input value because of the input range of Gm-C which as our second and third integrator. The finite RC time constant accuracy will also reduce the effectiveness of the noise shaping. Based on these requirements, a large amount of simulations were performed by using the MATLAB toolbox to explore the parameter space.
5.2 Architecture of the Loop Filter
5.2.1 Out-of-Band Quantization Gain
Fig. 5.1 Noise transfer function amplitude of a ΔΣ modulator
In Fig. 5.1, we illustrate the design of ΔΣ ADCs with the maximum out-of-band quantization noise gain Qmax. When the out-of-band quantization noise gain is high, we find the in-band noise shaping provide greater attenuation of the quantization
Maximum Out-of-Band Quantization Noise Gain
Base-band Quantization Noise Gain
noise. However, increasing Qmax will cause the ΔΣ system more unstable. According to Lee criterion [13], the Qmax of a ΔΣ modulator with a 1-bit quantizer must be less than 1.5 to maintain stable modulator performance. If a multibit quantizer is used, the quantization noise error is much lower. It is very natural to think that a much higher value of Qmax can be used to improve the signal to noise ratio (SNR) [14].
Fig. 5.2 shows the simulated signal-to-noise ratio (SNR) of different quantization bit third order ΔΣ modulators. When Qmax increases, SNR also increases and the performance gain is almost 20 dB when Qmax is much greater than 1.5. Thus, Qmax plays an important role in the performance of ΔΣ modulators. When advanced CMOS processes, the power supply voltage becomes lower and it also causes the input range of the transconductor lower. This leads to the dynamic range of delta-sigma modulator decrease because we usually define the output swing of the OpAmp in the first integrator or the input range of the transconductor in the second integrator as our full scales (FS) range which is also our maximum dynamic input range. When the value of the FS is decreased as the power supply voltage been lowered, one thing we can do is to make the in-band noise flow lower to maintain the same SNR.
Fig. 5.2 Simulated SNR as a function of Qmax for different quantization bit third order ΔΣ modulators (OSR = 16)
In 2
Fig. 5.3 Continuous-Time ΔΣ modulator architecture with compensation loop
Although increasing out-of-band quantization noise gain we can get some advantage, we also must pay for the cost. The cost is that it causes the system unstable easily. To overcome the problem, a D-flip-flop (DFF) that is in front of the DAC is used to fix the timing of the feedback pulse, as the Fig. 5.3 shown.
5.2.2 Improved Zero-Order Loop Compensation
Fig. 5.3 shows a block diagram of the 4-bit CT ΔΣ modulator including improved zero order loop compensation. With the exception of three integrators, DAC1, DAC2 and DAC3 realize the feedback paths, and together with DAC4 which it is used to realize the direct zero-order path around the semi-uniform quantizer, as will be explained later [15]. The digital input of DAC4 is delayed by a DFF to realize a full clock period delay. Generally, the implementation of the zero-order loop would require a summing amplifier. This leads to higher power consumption.
Moreover, the implementation of the RZ DAC increases design complexity and power consumption. To avoid this problem, we use the differentiation operation
which means the DAC4 is introduced in the direct feedback path. It allows the signal to be fed to the input of the third integrator. As Fig. 5.4 shown, we generate a loop filter function with a half sample delay using the MATLAB Control System Toolbox at first. Then, we make the DAC4 feed to the input of the third integrator and multiply s T together to make the equation equal. Following, we replace the S continuous-time differentiation operation by discrete-time differentiation operation.
Finally, expanding the parameter of DAC3 and DAC4, we get the results
( )
continuous time differentiation is difficult to implement, this is instead carried out in discrete time. In order to make the direct feedback signal available at the correct time, the differentiation operation works at a half clock period delay. By this excess loop delay compensation, we avoid the need for an additional summing amplifier which would increase power consumption.2
Fig. 5.4 Realization of the zero-order loop feedback path
5.2.3 Non-Uniform Quantization
Most of the quantization performed in A/D conversion is uniform quantization, which means the quantization steps are equal. Considering the low input range of the transconductor in the low power supply voltage design, to reduce the overall quantization error power, which is expressed in (5.2).
( ) 2 ( )
Pe ¥ r x e x d x
=
ò
- ¥ (5.2) Its quantization error e ( )x is smaller when the amplitude of x is small, and its e ( )x is larger when the amplitude of x is large. Therefore, the precondition to use a non-uniform quantizer is that the quantizer input distribution concentrates in the small-amplitude range, so that the overall noise power can be reduced by using a non-uniform quantizer. Fortunately, this precondition is satisfied with our low input range of transconductor.Fig. 5.5 The transfer curve of semi-uniform quantization
The name “semi-uniform” means that there are only two different-size quantization steps [16] [17] [18]. In other words, the small quantization step is for
small inputs and the large step for large inputs. In effect, for this 8-level semi-uniform quantizer with normalized full scale range of -1 ~ +1, the center four quantization steps have a step size of D = D , and the outer four quantization steps 1 have a step size of Δ2 = 3Δ1.
Fig. 5.6 The quantization error of semi-uniform quantization
Fig. 5.5 and Fig. 5.6 show the quantization levels and quantization error of an 8-level semi-uniform quantizer, compared with a 16-level uniform quantizer. At the five center steps, the quantization error of both the 8-level semi-uniform and 16-level uniform quantizers are the same, while at the outer steps the semi-uniform quantization error can be three times as large as that of the 16-level uniform quantizer. This implies that if most of the quantizer inputs fall into those small quantization steps, a k-bit semi-uniform quantizer could achieve the same dynamic range as a (k+1)-bit uniform quantizer. This helps us saving a lot of power and chip area for our low voltage input.
5.2.4 Dynamic Element Matching
Dynamic element matching (DEM) algorithms are often used in multi-bit modulators to increase DAC linearity. Because of the element mismatches in the multi-bit DAC, they introduce an output error which consists of the harmonics of input signal as well as an increased noise floor due to the folding of high frequency quantization noise into the baseband [9]. To convert the energy of the harmonic spurs into a pseudo-random noise, an error randomization technique is used. The process can be carried out if the input of DAC is a thermometer coded digital signal, and the DAC is built from unit elements (Here we use current sources). The error randomization conversion is performed by activating K unit elements if the value of input code is K, as Fig 5.7 shown. The error randomization is achieved by choosing these K unit elements circularly each time. For the use of DEM, the DAC error e(n) at time n will not be correlated with the value of its input v(n). Therefore, the signal distortion is replaced by random noise in the DAC output.
Fig. 5.7 Unit element DAC with randomized element selection
In 2 Fig. 5.8 The architecture of CT ΔΣ modulator we propose
In Fig. 5.8, we show the architecture of CT ΔΣ modulator we propose. The loop filter architecture we use is feedback structure with improved zero-order loop compensation, semi-uniform quantization and DEM.
5.3 System Level Simulation
As mentioned before, taking the non-idealities into account, we show the system analysis of DC gain and HD3 in the first active-RC integrator, as illustrated in Fig. 5.9 and Fig. 5.10. In Fig. 5.11 and Fig. 5.12, we show the system analysis of DC gain and HD3 in the second Gm-C integrator. We find the DC gain 60dB and 40dB are sufficient in the first integrator and second integrator, respectively. And the HD3 90dB and 70dB are sufficient in the first integrator and second integrator, respectively. Fig. 5.13 shows the output spectrum in this system level simulation of the modulator, which includes all the non-idealities except the thermal noise. As a comparison, the ideal noise transfer function is also plotted in this figure.
0 20 40 60 80 100
Fig. 5.9 The simulation of DC gain in first active-RC integrator
0 20 40 60 80 100 120 140 160 180 200
Fig. 5.10 The simulation of HD3 in the first active-RC integrator
0 10 20 30 40 50 60 70 80
Fig. 5.11 The simulation of DC gain in the second Gm-C integrator
0 20 40 60 80 100 120 140 160 180 200 -40
-20 0 20 40 60 80
SNDR (dB)
-HD3 (dB)
Fig. 5.12 The simulation of HD3 in the second Gm-C integrator
103 104 105 106 107 108
-180 -160 -140 -120 -100 -80 -60 -40 -20 0
SNDR (dB)
Frequency (Hz)
Fig. 5.13 The system simulation of CT ΔΣ modulator we propose
5.4 Circuit Level Design
5.4.1 Loop Filter
Fig. 5.14 Simplified block diagram of the third-order CT ΔΣ modulator
The third-order loop filter of our second design is implemented with CRFB architecture, as shown in Fig. 5.14. The first stage is an active-RC integrator and the following resonators are realized by Gm-C integrators. The role of the resonators is to shift the poles of the loop filter to optimum non-zero frequencies in order to reduce in-band quantization noise and get more performance. The two gain stages are also transconductors which convert the integrators’ outputs from voltages to currents and then convert back to voltages through a resistors ladder. The voltages on the resistors ladder are sampled by the semi-uniform multi-bit quantizer to generate the modulator digital outputs. The thermometer-coded outputs control the four current steering DACs to generate feedback currents, feeding to the each stage of modulator input.
In this design, the first stage also uses an active-RC integrator for its superior linearity. Gm-C integrators are chosen for the two resonators to save power.
5.4.1 First Stage － Active-RC Integrator
The OpAmp in the active-RC integrator uses a folded-cascode topology.
Compared with the telescopic OpAmp and the two-stage OpAmp, the folded-cascode OpAmp achieve the tradeoff between the power consumption and output swing in our 0.13 μm CMOS design (VDD = 1.2 V). Fig. 5.15 shows the schematic of the folded-cascode OpAmp used in this design. NMOS transistors are used for the input pair to provide a high speed path for the input. In addition, given the same biasing current and size, a NMOS transistor has larger transconductance than a PMOS transistor. Therefore, input referred thermal noise is lower when NMOS transistors are used for the input pair than if PMOS transistors are used. The spice simulation results are shown in Fig. 5.16, including DC gain and phase margin.
The detailed specifications are summarized in Table 5.1.
VSS
Fig. 5.15 Schematic of folded-cascode OpAmp
Fig. 5.16 The spice simulation, including DC gain and phase margin
Table 5.1 Summary of spice simulation results Specification Simulation Results
Technology TSMC 0.13μm 1P8M
Unit Gain Frequency 100 MHz ( Cload = 8p )
Phase Margin 78°
DC Gain 61 dB
Out Range 1.0 Vpp
Power Supply 1.2 V
Power Dissipation 2.45 mW
5.4.3 Following Stage － Gm-C Integrator
VSS VDD
VIP M1 M2 VIN
M3 M4
M5 M6
M7 M8
M9 M10
M11 M12
Vb1
Vcmfb Vb2 Vb3 Vb3
VON VOP
R
C C
Fig. 5.17 Schematic of Gm with source degeneration resistor
A folded-cascode architecture is used with source degeneration resistor, as shown in Fig. 5.17. It achieves the required linearity and it has independent input-output common mode voltages as well. The constant transconductance is shown in Fig. 5.18, it shows the linear range between -0.2V to 0.2V. The spice simulation results are shown in Fig. 5.19, including DC gain and phase margin. The detailed specifications are summarized in Table 5.2.
Fig. 5.18 The simulated transconductance range
Fig. 5.19 The spice simulation, including DC gain and phase margin
Table 5.2 Summary of spice simulation results Specification Simulation Results
Technology TSMC 0.13μm 1P8M
Unit Gain Frequency 33 MHz ( Cload = 3p )
Phase Margin 90°
DC Gain 47 dB
Out Range 1.0 Vpp
Power Supply 1.2 V
Power Dissipation 1.51 mW
5.4.4 Current Steering DAC with Semi-Uniform
Quantization
Fig. 5.20 shows the schematic of the unit current steering DAC cell. The current cell is composed of four transistors which are current source M1, cascode transistor M2 and two switches (M3 and M4). The cascode transistor is used to increase the output impedance of the current source, and at the same time, to prevent the dynamic glitches at the node A from impacting the current in M1. However, adding this cascode transistor reduces the allowable saturation voltage of M1 and hence the noise performance of the current DAC. The gates of the switch transistors are controlled by the complementary digital feedback signals, D and Db.
Fig. 5.20 Schematic of the unit current steering DAC cell
When the 8-bits digital codes are high, the system must minus the value of FS.
For the use of active-RC integrator, the current value of FS is
R e f D A C
I V
= R (5.3)
Quantizer Input D3
D2
D1 D4D5D6 D7 D8
Fig. 5.21 The determination of digital codes in semi-uniform quantization
where VR e f is the voltage value of FS and the R is resistor value of aictive-RC.
For the use of Gm-C integrator, the current value of FS is
R e
D A C f
I = G m ´ V (5.4)
where VR e f is the voltage value of FS and the Gm is the transconductance value of Gm-C. Considering the semi-uniform quantizer, there are two kinds of quantization intervals, that is to say, the feedback current could not be the same when one bit digital code changes. As Fig. 5.21 shown, when one of D3, D4, D5 and D6 changes, the variation of current would be ID A C / 1 6 ; when one of D1, D2, D7 and D8 changes, the variation of current would be 3I D A C / 1 6 .
5.4.5 Current Summation Circuit
Before the quantizer, a current summation circuit (adder) is needed. The speed of this adder is one of the most critical issues in the modulator design. If a passive adder is used, it will be very sensitive to the parasitic input capacitors of the quantizer. If an active voltage adder is used, an extremely fast OpAmp is needed, which will cost large power. In our design, a fast and low power active current adder is used to realize this summation operation [19], as shown in Fig. 5.22.
Fig. 5.22 Schematic of the current summation circuit
In the summation circuit, the loop filter output are transformed from voltage to current with the transconductor (Gm) cell which are shown in left side of Fig. 5.22, and then fed into the resistor ladder at the cascode nodes of the two current sources (M5, M6, M7 and M8). In order to increase the linearity of the Gm cell, the input voltage-current (V-I) conversion is realized with source degeneration resistor, as the
same before. Due the use of source degeneration resistor, a very linear V-I conversion is obtained without difficult matching requirements for the MOS transistors.
5.5 Circuit Level Simulation
The circuit level results are simulated by Hspice. The captured output digital data is windowed by a Hann window and a Fourier transformation is applied using Matlab. The spectra resulting (16384 bins from 0 to FS) from -20 dB 156 kHz input signal can be seen in Fig. 5.23. The total power consumption is 10 mW. The finial specifications are summarized in Table 5.3. The chip photo is shown in Fig. 5.24.
The total area, including pad is 1.1 x 0.9 mm2.
104 105 106 107
-140 -120 -100 -80 -60 -40 -20 0
SNDR (dB)
Frequency (Hz)
Fig. 5.23 The circuit simulation of this work (16384pt, 156 kHz input)
Fig. 5.24 Chip photo of this work
Table 5.3 Summary of circuit level simulation results Specification Simulation Results
Technology TSMC 0.13μm 1P8M
Signal bandwidth 2 MHz
Sampling frequency 62.5 MHz
SNDR 63 dB
SFDR 76 dB
ENOB 10
Power Supply 1.2 V
Power Dissipation 10 mW
Chip area (with pad) 1.1 mm x 0.9 mm
These two works have been fabricated by TSMC 0.18 μm CMOS Mixed-Signal process and TSMC 0.13 μm CMOS Mixed-Signal process. In this chapter, we present the testing environment, including the component circuits on the DUT (device under test) board and the instruments. The measured results are presented in this chapter, too.
6.1 A Continuous-Time Delta-Sigma Modulator Using Feedback Resistors
Integrator 1 Integrator 2 Integrator 3
Dac 1 Dac 2 Dac 3
Tuning Circuit 1 Tuning Circuit 2
Tuning Circuit 3
Digital
&
Output Buffer Clock Generator Bias
Fig. 6.1 Die photo of this work using feedback resistors
Fig. 6.1 shows the die photo of first work using feedback resistors, in which some important blocks are annotated. Several commonly used layout techniques were employed, such as common-centroid layout for all fully differential input pairs, inter-digitation for current sources, guard ring and shielding. Between the analog and digital areas, a deep n-well was inserted to further reduce the noise coupling.
6.1.1 Test Setup
Fig. 6.2 Test environment
Fig. 6.2 presents the configuration of the instruments used to evaluate the performance of the chips. The testing printed circuit board (PCB) contains voltage regulator, single to differential transformer circuit for input signals and clock, tuning resistors, tuning switches, and the DUT, as shown in Fig. 6.3. The differential sinusoidal input signals are produced by the audio precision. The clock generator is used to provide low jitter clock signal for the modulator. The modulator digital outputs are captured by the logic analyzer. The FFT analysis of the output data are performed in MATLAB using a PC connected to the logic analyzer.
Fig. 6.3 Photograph of the first test board
6.1.2 Measurement Results
The chips have been tested with a 798 KHz input signal and 100 MHz sampling rate. Fig. 6.4 shows the relationship between the post-simulation and the measured.
The chips have been tested with a 798 KHz input signal and 100 MHz sampling rate. Fig. 6.4 shows the relationship between the post-simulation and the measured.