Chapter I Introduction
1.3 Thesis organization
A quadrature frequency tripler with fundamental cancellation is presented in Chapter II. Introduction and motivation are described in section 2.1. The design consideration and circuit implementation are explained in section 2.2, followed by the measurement considerations and experimental results in section 2.3 and 2.4 respectively. A summary is given in section 2.5.
The design of the outphasing low-power PA is presented in Chapter III.
Introduction to outphasing technique and the techniques for linearity and efficiency enhancement are provided in section 3.1 and 3.2 respectively. Then, the introduction to PAs and design considerations of class-D PAs are given in section 3.3 and 3.4 respectively. The power combining of outphasing PA is described in section 3.5, followed by the circuit implementation in section 3.6. The chip layout and post-layout simulations are demonstrated in section 3.7. Finally, section 3.8 summarizes the outphasing PA.
The conclusion of this thesis and the future work are given in the Chapter IV.
Chapter II
A Quadrature Frequency Tripler with Fundamental Cancelling
2.1 Introduction and Motivation
Many frequency triplers have been proposed to utilize a nonlinear device, transistors for instance, to acquire the third-order harmonic by driving the transistors into a strongly non-linear region [2-4]. Then a filter is usually implemented in the next stage to eliminate undesired spurs at the output. In general, these circuits usually consume much power and have low conversion efficiency. Alternative method is proposed in [5], which is a time-wave form shaping technique. It enhances the third-order harmonic by pulling the output voltage three times in each fundamental cycle. This approach becomes less efficient in millimeter-wave frequencies limited by the switching operation of transistors. Similar approach was found in [6]. But it results in large power consumption and more complication.
In this work, frequency tripler with a technique of fundamental cancelling was proposed. By applying this technique, the third-order harmonic can be produced under low power consumption. In addition, the proposed technique forms a quadrature phase signal suitable for communication system with I/Q signals, which is good for image rejection.
According to the measured results, this frequency tripler with fundamental cancelling provides 35 dB harmonic rejection ratio (HRR) under 11.5 mW power consumption and conversion gain of -4.2 dB after calibrating poly-phase filter and
buffer loss. The phase noise measured at 1 MHz offset of the 1.5 GHz input signal source and the third-order output are -142.3 dBc/Hz and -123.8 dBc/Hz
Circuit realization is mentioned in Section 3.2. The measurement considerations are mentioned in Section 3.3, and chip implement and measurement results are in Section 3.4 circuit realization. The summary is given in Section 3.5.
2.2 Circuit Realization
As aforementioned, typically the method relies on strong input signals that drive a device into the strongly nonlinear region to obtain the high-order frequency harmonics, of which the desired output signal is selected by filtering. It is confronted with large power consumption and large chip size for band-pass filter (BPF). Fig. 2.1 demonstrates traditional method of frequency tripler. Then the efficient method of frequency tripler was proposed that improved the conversion efficiency shown in Fig.
2.2.
The function of a frequency tripler not only produces the desired third-order harmonic but it also needs to have a high harmonic rejection ratio (HRR). In this work, the fundamental frequency cancelling is introduced that operates under low power consumption and saves BPF at output shown in Fig. 2.3. Accordingly, a tripler with a high HRR is critical to suppress undesired spurs.
Fig. 2.4 shows the block diagram of the frequency tripler with fundamental cancelling. In circuit realization, it consists of a pair of poly-phase filter and a pair of frequency tripler with fundamental cancellation circuit. The poly-phase filter transforms the differential signal into quadrature I/Q signals. Then, the quadrature signals are injected into the core circuit to generate third-order harmonic signals at outputs. The quadrature generator, a pair of three-stage- poly-phase filters [10] are used in this work for function testing only. In circuit integration, the quadrature signals can be provided by a divider.
In this section, the frequency tripler, principle of fundamental cancelling and the evolution of the cancellation circuit will be mentioned.
Fig. 2.1 Traditional method of frequency tripler configuration
Fig. 2.2 Efficient method of frequency tripler
Fig. 2.3 Proposed method of frequency tripler with fundamental cancellation
Fig. 2.4 The block diagram of frequency tripler with fundamental frequency cancellation
2.2.1 Frequency Tripler
The frequency tripler was realized by injection of a second harmonic current [7].
Applying this technique, third-order harmonic can be generated efficiently under low power consumption. Fig. 2.5 shows the frequency tripler for I path and Q path. The bottom transistor pair, M1,2 or M13,14, forms a frequency doubler that provides a second-harmonic current injection into the source-couple differential pair, M3,4 and M15,16, which works like a switching stage of a conventional mixer. Therefore signals with fundamental and third order harmonic frequencies (2fo±fo) are produced at output.
The most critical factors for maximizing 3rd harmonic current at the output are as follows. First, each transistor is biased at where the device could generate maximum gm’, which is the derivative of the transconductance gm. This will maximize the efficiency of frequency conversion. Second, the input phase difference
between top and bottom transistor are ±90 degrees out of phase that provides a maximal output current at 3fo shown in Fig. 2.6. These currents then flow through resistive loadings to produce the output voltages. There is a figure of merit, called harmonic rejection ratio (HRR), which indexes the performance of multiplier circuits.
It is defined as the ratio of the desired harmonic to undesired n-th order harmonic, as demonstrated in Equation (2.1).
harmonic) order
th -n Undesired
harmonic Desired
log(
≡20
HRR
(2.1)In frequency tripler circuit, the desired harmonic is the third-order one, and the undesired harmonic are fundamental and second order harmonics. Other higher order harmonics are small and have neglected effects on the circuit performance.
Fig. 2.5 Frequency tripler for I and Q paths
0.0
Fig. 2.6 Output current at 3fo versus phase difference of upper and bottom difference pairs
2.2.2 Principle of Fundamental Cancelling
Although, the frequency tripler could produced the third-harmonic current efficiently, but it still exists many undesired harmonic signals especially of fundamental frequency. Equation (2.2) demonstrates the output current of frequency tripler. fundamental, second-order and third-order harmonic signals.
) ψ ωt (
C
1cos 3 + 3In order to obtains higher harmonic rejection ratio in multiplier circuit. The filter is one of the most popular methods to suppress undesired spurs at output. It needs higher quality factor of filter that achieves higher harmonic rejection ratio, but it is not easy implemented in chip. Therefore, the fundamental frequency cancelling technique comes out to leave out the output filter.
The principle of fundamental cancelling is generating an inverse current at fundamental frequency then the output current at fundamental frequency could be cancelled. The current of cancellation circuit is expressed in equation (2.3).
...
fundamental, second-order and third-order harmonic currents.According to equation (2.2) and (2.3), the output fundamental current would be cancelled completely while the
θ
1 =π
+ψ
1 andA
2 =A
1. Fig. 2.7 illustrates the concept of the fundamental cancelling.Fig. 2.7 Concept of the fundamental cancelling
2.2.3 Evolution of Cancellation Circuit
Before going into the evolution of cancellation circuit, we should care the phase of the fundamental current of tripler. Because of the bottom differential pair (Fig. 2.5) forms a frequency doubler providing the second-order harmonic current injection into
source couple differential pair. Therefore, the output fundamental current of the frequency tripler is contributing from source couple differential pair. Therefore, a straight forward method is introducing a common source (CS) amplifier, M5 and M6, then the CS amplifier connected to outputs that the input signals are 180-degree out of phase with source couple differential pair as demonstrated in Fig. 2.8. According to simulation result, the output fundamental currents of the tripler generating can be suppressed successfully but performance of the fundamental harmonic rejection ratio is not impressive. Because of parasitic capacitance are different that result in the current i1 and icore are not 180-degree out of phase, therefore, the current iout
would not
be cancelled completely. Fig. 2.9 shows the frequency response of current of i1 , icoreand iout from 1 GHz to 2 GHz at Cartesian coordinate. The current iout is linear combination of current i1 and icore.
In order to enhance the fundamental rejection ratio another common source amplifier, M7 or M8, is introduced in cancellation circuit as shown in Fig. 2.10.
Consequently, the output fundamental current of the cancellation circuit iVT’, iVT’ is linear combination of i1 and i2, can be adjusted by biasing point of transistors M5, M7
and M6, M8 but increased the parasitic capacitance at drain-source junction. The unit current gain buffers (M9 and M10) are introduced to reduce the loading effect on the tripler core due to the parasitic capacitance from the cancellation circuit. Fig. 2.11 illustrates the simulation result of output fundamental current (black), gray is previous simulation without current i2, of cancellation circuit and frequency tripler from 1 GHz to 2 GHz. Moreover, transistors (M5, M7 and M6, M8) are biasing at sub-threshold region, it is advantageous in low power consumption.
Finally, transistors (M11, M12) are introduced in cancellation circuit to provide appropriate biasing current to the unit gain buffer as shown in Fig. 12. The current
magnitude and phase of cancellation circuit at fo are decision by i1 and i2, then its illustrated in (2.4) and (2.5).
2
According to (2.4) and (2.5), the perfect cancellation occurs only at single frequency point. Therefore, the fundamental cancellation method is a narrow band configuration.
M 2 M 1
R 1 R 2
L 1 L 2
M 3 M 4 V DD V DD
+ V o =I
-I - I +
Q - Q + M 6
M 5
I + I
-i Core
i 1
Fig. 2.8 Straight forward method
Fig. 2.9 Simulation result of preliminary improve method
M
2M
1R
1R
2L
1L
2M
3M
4M
5M
7M
10M
9M
6M
8V
DDV
DDi
Corei
VTV
DDV
DD+ V
o=I
-- Q
fo+ I
fo-i
1i
2Fig. 2.10 Improving HRR1 by adding another vector
Fig. 2.11 Simulation result of adding another vector
+
Fig. 2.12 Schematics of proposed frequency tripler with fundamental cancellation for I path
-0.2 -0.1 0.0 0.1 0.2
-2 -1 0 1 2
Im (mA)
Re ( m A)
Iout (fo) Icore (fo) Icancel (fo)
Fig. 2.13 Simulation result of frequency tripler with fundamental frequency cancelling
2.3 Measurement Considerations
Based on the analyses in Section 2.2, an S-band fundamental cancelling circuit was designed and fabricated. Before going into the part of chip implementation, we ought to pay attention to some considerations relating to the final measurement. This step may determine what you can measure (or not) the actual results of your fabricated circuits.
It is difficult to ensure quadrature phase signals because the mismatch of cables and adapters when they connect to the chip usually results in large phase errors and magnitude imbalance. For this reason, one pair of three stages poly-phase filters are merged into the tripler to provide the needed quadrature signals, one for I path the other for Q path. The fundamental input frequency is ranged from 1 GHz to 4 GHz.
Fig. 2-14 shows the schematics of three stages poly-phase filter.
Fig. 2.14 Three stage poly-phase filter
It is very difficult to guarantee the phase and magnitude without mismatch because of the output signal path of the poly-phase filter is more complex to connect
into core circuit. To minimize the phase and magnitude error where the floating metal of fifth layer was introduced under metal of sixth layer that increasing parasitic capacitance (slow wave) as shown in Fig. 2.15. On the other hand, the process variation also should be considered. The capacitors and resistors are put together to minimize the process variation shown in Fig 2.16.
Fig. 2.15 Profile of poly-phase output path
Fig. 2.16 Poly-phase filter layout considerations for process variation
Fig. 2.17 illustrates the post layout simulation results of magnitude and phase frequency response from 1 GHz to 2 GHz input frequency of three stages poly-phase filter, and of magnitude and phase error are shown in Fig 2.18 that less than 0.4 dB and 0.3 degree, respectively. The phase error and magnitude error are defined as (2.6) and (2.7)
path)
Fig. 2.17 Frequency response of magnitude and phase
0.0
Fig. 2.18 Output magnitude and phase error versus input frequency
2.4 Chip Implement and Measurement results
A pair of frequency tripler with fundamental cancelling was realized in this work.
The cancellation circuit was designed to produce out of phase signals with respect to tripler that can be used to cancel output fo current. This tripler features quadrature signals at both the input and output. The filter(s) that eliminated unwanted harmonics at output or off-chip was absent. In addition, a pair of poly-phase filter is also implemented for verifying the function of the frequency tripler.
2.4.1 Chip Implementation
As aforementioned, the output signal path of the poly-phase filter is more complication. In chip implementation, two poly-phase filters of three stages are fabricated in this work in view of layout considerations and I and Q path mismatch.
The frequency tripler with fundamental cancelling is fabricated using 180 nm standard CMOS technology. The total chip area, including one pair of three stages poly-phase filter (for function testing) one for I path and the other for Q path, two S-band frequency triplers with fundamental cancelling, four output buffers (for measurement), is 1400x1100 um2. The core circuit only occupied 350x1100 um2 and total power consumption of tripler in operation is 11.5 mW under 14 dBm input power (after calibrating cable and Hybrid loss), while output buffer consumes 43.1mW, all for 1.8 V supply voltage.
Fig. 2.19 Poly-phase filter for I path
Fig. 2.20 Frequency tripler with fundamental cancellation for I path
Fig. 2.21 Poly-phase filter for Q path
+
Fig. 2.22 Frequency tripler with fundamental cancelling for Q path
2.4.2 Measurement Results
The Microphotograph of fabricated chip is shown in Fig. 2.23, and Fig. 2.24 illustrates measurement setup. An off-chip 180o hybrid coupler provides a differential
signal to pair of three stages poly-phase filter then the core circuit is driven by quadrature I/Q signals. Both I/Q paths, open-drain buffers are used for measurement purposed.
Fig. 2.23 Chip microphotograph
Fig. 2.24 Measurement setup
The HRR1 is one of the most critical performance what we care. Fig. 2.25 shows a snapshot of the measured output spectrum with an input signal of 14 dBm (excluding cable and Hybrid coupler loss) at 1.5 GHz input frequency. The output power of the third-order harmonic is -23.7 dBm after calibration of cable loss.
Measured at the input frequency of 1.5 GHz, the output phase noise at third-order harmonic frequency is -123.8 dBc/Hz at 1MHz offset as shown in Fig.
2.26. The phase noise of the input signal is -142.3 dBc/Hz, yielding to discrepancy of 8.9 dB relate to the ideal multiplication. Fig. 2.27 shows the fundamental harmonic rejection ratio versus input power with a 1.5 GHz input signal. The HRR1 is more than 35 dB while input power is 14 dBm. Fig. 2.28 demonstrates the output power of fundamental and third-order harmonics versus input frequency. The conversion voltage gain versus input frequency is shown in Fig. 2.29, and Fig. 2.30 shows conversion voltage gain versus input power. The poly-phase filter and output buffer loss were calibrated which is 12.8 dB and 11 dB (simulation) respectively.
, ) log( ,
20 3
fo fo
Vi CG≡ × Vo
Fig. 2.25 Output spectra at 1.5 GHz with 19 dBm input power
Fig. 2.26 Output phase noise at 4.5 GHz
-5 5 15 25 35 45
10 11 12 13 14 15 16
Input power (dBm)
HRR1 ( d B)
Fig. 2.27 HRR1 versus input power
-70 -60 -50 -40 -30 -20 -10 0
1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Input Frequency(GHz)
O u tput P o w e r (dB m )
fo 3fo
Fig. 2.28 Fundamental and third-order versus input frequency
-8 -6 -4 -2 0
1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Input Frequency (GHz)
C o n ver si o n G a in (d B )
Fig. 2.29 Conversion voltage gain versus input frequency without poly-phase and buffer loss
Input frequency=1.5 GHz
-45 -41 -37 -33 -29 -25 -21
9 10 11 12 13 14 15 16
Input Power (dBm)
C onve rsi on G a in (d B )
Fig. 2.30 Conversion voltage gain versus input power with poly-phase and buffer loss
Finally, a performance summary is given in the Table 2.1. The proposed frequency tripler with fundamental cancelling provides high HRR1 and moderates conversion gain and lower power comparison. The comparison is given in the Table 2.2.
Table 2.1 Performance summary
Technology CMOS 180nm
Power Supply 1.8 V
1400x1100 um2 (350x1100 um2)
Table 2.2 Comparison with other published
[6] [7] [8] [9] This work
2.5 Summary
A novel frequency tripler with fundamental cancelling circuit is realized using TSMC 180 nm CMOS technology. The proposed frequency tripler has high harmonic rejection ratio under low dynamic power consumption and does not need any filters either at output or off-chip. In addition, the proposed technique feature a quadrature phase signals that suitable for the communication system with I/Q signals for image rejection.
Chapter III
Outphasing Low-Power Amplifier
3.1 Introduction
Efficiency and linearity are the most critical factors for RF front-end power amplifiers (PA). The efficiency had to contend with linearity in typical power amplifier. There are many technology could improve the linearity or efficiency such as Cartesian feedback, pre-distortion, adaptive digital pre-distortion, feed-forward, and outphasing amplifier for linearity enhancement and Doherty amplifier, and bias adaption for efficiency improvement.
The feed-forward method provides excellent linearity and broad-band characteristics. However, the error amplifier is a complicated control circuit [11]-[13].
The instability and bandwidth limitation is advantageous for feedback technique [14]-[16].
Outphasing modulation system is one solution to improve both efficiency and linearity that proposed by H. Chireix [17]. Outphasing PA is made up of a pair of power amplifiers and a combiner to combine signal. Class D power amplifier is used in this work that provides high efficiency (switched-mode power amplifier), and combiner is used transformer at output.
In section 3.2 mentioned the principle of outphasing transmitter, and introduction of Class D PA in Section 3.3. In section 3.4 illustrated circuit realization of class D power amplifiers. The combiner is a key factor of outphasing system. Therefore outphasing power combining technology was illustrated in Section 3.5. The circuit realization and chip layout and post-layout simulation were illustrated in Section 3.6
and Section 3.7, respectively. Finally, a summary is given in Section 3.8.
3.2 Outphasing Transmitter
The concept of LInear amplification with Nonlinear Component (LINC) or outphasing is that an amplitude and phase modulated signal is resolved into two out phased constant envelope signals by signal component separator. Fig. 3.1 shows the structure of the outphasing transmitter.
Fig. 3.1 Outphasing transmitter configuration
3.2.1 The Theory of Outphasing Amplification
The arbitrary input signal Vin
(θ) is separated into two out phased constant
envelope signals V1(φ (t)) and V
2( φ (t)), as illustrated in (3.1) (3.2) and (3.3).
= 2 A ( t ) cos( ω t + θ )
(3.4)where
( ) )
( cos )
(
max 1
B t t =
−A ϕ
In equation (3.4) presents principle of linear amplification. Fig. 3.2 illustrates the separation of two component signals from the source signal.
Fig. 3.2 Separation of two component signals from the source signal
3.3 Power Amplifier Introductions
3.3.1 The parameters of power amplifier definition
There are many parameters that can verify the performance of power amplifier.
The definition of these parameters is shown below:
1. Drain Efficiency: The drain efficiency is defined as
= ×100%,
where the Pout is the output power that delivered to load at the interesting frequency.
And the PDC is the total power consume from power supply. Ideally, the drain efficiency is 100% for switched-mode power amplifiers.
2. Power Added Efficiency (PAE): The power added efficiency is most commonly used to verify the performance of power amplifier. It is defined as
where Pin is input power of power amplifier.
3. Input 1-dB compression point (IP1-dB): An amplifier keeps a constant gain for low input power levels. Nevertheless, at higher input power levels, the amplifier goes into saturation and its gain decreases. The IP1-dB is referred to as the input power level which results in 1 dB gain degradation form its small-signal behavior shown in Fig.
3.3.
4. Adjacent Channel Power Ratio (ACPR): The unwanted signal power at adjacent channel would be generated due to the nonlinear effect of the power amplifier. ACPR is a parameter which characterizes the ratio between signal power at the desired channel and adjacent channel. Higher ACPR means better isolation with
adjacent channel.
Fig. 3.3 P1-dB definition
3.3.2 Principle of Class D power amplifier
The efficiency is the most critical factor for power amplifiers design. Ideally, the drain efficiency achieves 100% for switched-mode power amplifiers, which is the transistor treated as a switch. Thus, transistor’s drain current and voltage never cross at the same time. Fig. 3.4 (a) shows the configuration of voltage-switching class D power amplifier [18]. It consists of an inverter and an L-C series resonator. The L-C tank removes the high-order harmonic frequency signal ensures sinusoidal output.
The transistor Mn and Mp are switched alternately that depend on input voltage swing. The transistor Mn is turned on while the input swing is higher than its threshold voltage. Then the voltage at the drain Vd of transistor Mn and Mp will be pulled down
The transistor Mn and Mp are switched alternately that depend on input voltage swing. The transistor Mn is turned on while the input swing is higher than its threshold voltage. Then the voltage at the drain Vd of transistor Mn and Mp will be pulled down