Summary

A novel frequency tripler with fundamental cancelling circuit is realized using TSMC 180 nm CMOS technology. The proposed frequency tripler has high harmonic rejection ratio under low dynamic power consumption and does not need any filters either at output or off-chip. In addition, the proposed technique feature a quadrature phase signals that suitable for the communication system with I/Q signals for image rejection.

Chapter III

Outphasing Low-Power Amplifier

3.1 Introduction

Efficiency and linearity are the most critical factors for RF front-end power amplifiers (PA). The efficiency had to contend with linearity in typical power amplifier. There are many technology could improve the linearity or efficiency such as Cartesian feedback, pre-distortion, adaptive digital pre-distortion, feed-forward, and outphasing amplifier for linearity enhancement and Doherty amplifier, and bias adaption for efficiency improvement.

The feed-forward method provides excellent linearity and broad-band characteristics. However, the error amplifier is a complicated control circuit [11]-[13].

The instability and bandwidth limitation is advantageous for feedback technique [14]-[16].

Outphasing modulation system is one solution to improve both efficiency and linearity that proposed by H. Chireix [17]. Outphasing PA is made up of a pair of power amplifiers and a combiner to combine signal. Class D power amplifier is used in this work that provides high efficiency (switched-mode power amplifier), and combiner is used transformer at output.

In section 3.2 mentioned the principle of outphasing transmitter, and introduction of Class D PA in Section 3.3. In section 3.4 illustrated circuit realization of class D power amplifiers. The combiner is a key factor of outphasing system. Therefore outphasing power combining technology was illustrated in Section 3.5. The circuit realization and chip layout and post-layout simulation were illustrated in Section 3.6

and Section 3.7, respectively. Finally, a summary is given in Section 3.8.

3.2 Outphasing Transmitter

The concept of LInear amplification with Nonlinear Component (LINC) or outphasing is that an amplitude and phase modulated signal is resolved into two out phased constant envelope signals by signal component separator. Fig. 3.1 shows the structure of the outphasing transmitter.

Fig. 3.1 Outphasing transmitter configuration

3.2.1 The Theory of Outphasing Amplification

The arbitrary input signal Vin

(θ) is separated into two out phased constant

envelope signals V1

(φ (t)) and V

2

( φ (t)), as illustrated in (3.1) (3.2) and (3.3).

= 2 A ( t ) cos( ω t + θ )

(3.4)

where

( ) )

( cos )

(

max 1

B t t =

⁻

A ϕ

In equation (3.4) presents principle of linear amplification. Fig. 3.2 illustrates the separation of two component signals from the source signal.

Fig. 3.2 Separation of two component signals from the source signal

3.3 Power Amplifier Introductions

3.3.1 The parameters of power amplifier definition

There are many parameters that can verify the performance of power amplifier.

The definition of these parameters is shown below:

1. Drain Efficiency: The drain efficiency is defined as

= ×100%,

where the Pout is the output power that delivered to load at the interesting frequency.

And the PDC is the total power consume from power supply. Ideally, the drain efficiency is 100% for switched-mode power amplifiers.

2. Power Added Efficiency (PAE): The power added efficiency is most commonly used to verify the performance of power amplifier. It is defined as

where Pin is input power of power amplifier.

3. Input 1-dB compression point (IP1-dB): An amplifier keeps a constant gain for low input power levels. Nevertheless, at higher input power levels, the amplifier goes into saturation and its gain decreases. The IP1-dB is referred to as the input power level which results in 1 dB gain degradation form its small-signal behavior shown in Fig.

3.3.

4. Adjacent Channel Power Ratio (ACPR): The unwanted signal power at adjacent channel would be generated due to the nonlinear effect of the power amplifier. ACPR is a parameter which characterizes the ratio between signal power at the desired channel and adjacent channel. Higher ACPR means better isolation with

adjacent channel.

Fig. 3.3 P1-dB definition

3.3.2 Principle of Class D power amplifier

The efficiency is the most critical factor for power amplifiers design. Ideally, the drain efficiency achieves 100% for switched-mode power amplifiers, which is the transistor treated as a switch. Thus, transistor’s drain current and voltage never cross at the same time. Fig. 3.4 (a) shows the configuration of voltage-switching class D power amplifier [18]. It consists of an inverter and an L-C series resonator. The L-C tank removes the high-order harmonic frequency signal ensures sinusoidal output.

The transistor Mn and Mp are switched alternately that depend on input voltage swing. The transistor Mn is turned on while the input swing is higher than its threshold voltage. Then the voltage at the drain Vd of transistor Mn and Mp will be pulled down to ground. On the contrary, the input voltage swing of transistor Mn and Mp will be pulled up to VDD. Fig. 3.4 (b) and (c) present the pull up and pull down operation mode. Fig. 3.4(d) shows the ideal waveform for power amplifier at the drain. During T1 period VD

is pulled down to zero, and during T

2 period, the NMOS is cut off and ID

is zero. Because of the characteristic of non-overlap of the current and voltage, the

power dissipation of the switch mode power amplifier is zero.

(a)

(b)

(c)

Time

Time I

_d

PMOS ON

NMOS ON

PMOS ON NMOS

ON

(d)

Fig. 3.4 (a) Configuration of voltage-switching class D power amplifier(b) Pull down operation mode.

(c) Pull up operation mode. (d) Ideal waveform at drain of transistor.

3.3.3 Switched mode low-power amplifier design considerations

There are many parameters ought to take care in low power amplifier circuit design.

1. Input voltage swing: As aforementioned, the input voltage swing must be large enough to fully turn on and off the transistor for a proper switched-mode power amplifier operation. The drain efficiency degrades with insufficient input voltage

swing. Fig. 3.5 shows the relationship between the voltage waveform at the drain and the input voltage swing. The sinusoidal waveform indicates an insufficient input voltage swing, while the square waveform corresponds to a sufficiently large input voltage swing which is able to fully turn on and off the transistor.

Fig. 3.5 Relationship between the voltage waveform at the drain and the input voltage swing

2. Output load impedance: The output load impedance of the power amplifier is a critical factor for the output power. The output power can be calculated by

load out out

R P V

2

2

=

(3.7)

where the Pout,

V

out and Rload are the output power, root mean square output voltage and output load impedance, respectively. The smaller output load impedance leads to a larger output power transfer which is evident in (3.7). Usually, most output load impedance of power amplifier is decided by load-pull, which is the maximum output power can be found on a smith chart. For smaller output power level amplifiers, or said low power amplifiers, the small output load impedance is unnecessary.

3. Drain-source junction parasitic capacitance (Cp): The parasitic capacitance Cp

at drain-source junction would result in switching speed reduction in high frequencies.

Moreover, this Cp causes the energy dissipation due to Cp

V

on2

/2 where V

on

is output

voltage of transistor at the instant of switch closure, and the energy dissipated in the on-resistance of the transistor.

4. Finite turn-on and turn-off time of transistors: Ideally the device switched between the saturation mode with zero on resistance and the pitch off mode with zero drain current. However, in real transistors there would exist non-zero transition times overlapping between the drain current and voltage waveforms as illustrated in Fig. 3.6, especially at high frequencies. This results in efficiency degradation.

Fig. 3.6 Finite turn-on and turn-off time

3.4 Circuit Realization of Class D power amplifier

3.4.1 Self biasing

Fig. 3.7 (a) shows the configuration of class D amplifier with self-biasing resistor.

A large resistor, Rf, which connects across gate and drain is used to ensure a same DC voltage potential of VG and VD while separating their ac behavior. The bias voltage at gate and drain is VDD /2 while the total size of transistor Mn and Mp is 200 µm and 720

µm respectively.

3.4.2 Maximum Drain Efficiency

As mention previously, the small output load impedance is not necessary in low power amplifier circuit design, and the efficiency is the most important parameter that we care about. Therefore, the output load impedance of class D power amplifier is chosen to be 50 ohm for maximum drain efficiency (impedance transformation network is not necessary) at an input voltage swing of 0.3 V. Fig. 3.7 (b) shows the drain efficiency versus the output load impedance. The drain efficiency is more than 60%. Ideal components are used in this simulation except transistors. The transient response of the drain voltage and current of NMOS are shown in Fig. 3.7 (c) and (d).

The overlapping of current and voltage result in efficiency degradation.

(a)

45 50 55 60 65

20 25 30 35 40 45 50 55 60 RL (ohm)

D rai n ef fi ci en cy ( % )

(b)

0.0

Fig. 3.7 (a) Class D amplifier with self-biasing resistor (b) Drain efficiency versus output load impedance (c) Transient response of drain voltage (d) Transient response of drain current

3.5 Outphasing Power Combining Technology

3.5.1 Combiner Types

There are many types of combiners for the outphasing power amplifier, including transformers, hybrid couplers, Wilkinson combiners, Lange couplers, and transmission line combiners. Among all, there are two types of combiners that are commonly employed at the output stage for power combining purpose. One is the lossless and unmatched combiner and the other is lossy and matched combiner.

The lossless and unmatched combiners provide high combining efficiency, unfortunately the linearity are poor. Chireix and Wilkinson combiner with isolation resistor are of this type. On the contrary, the lossy and matched combiners provide high isolation between combining ports, this yield high linearity but with poor combining efficiency, especially for the signal with high peak to average ratio. Table 3-1 summarizes these two types of combiners in terms of isolation, linearity, and efficiency.

Table 3-1 Comparison of lossy and lossless combiner

Isolation Linearity Efficiency

Lossy Good Good Bad

Lossless Bad Bad Good

3.5.2 Time Dependence of Input Impedance

The output of the two PAs can be written as two voltages that connected to the )))

))) ( sin(

)) ( (cos(

)) ( (

2

V e V t j t

V

_in = _m ^{jωt−ψ t} = _m

ψ

−

θ

(3.9) two input ports of combiner shown in Fig. 3.8 (a). Fig. 3.8 (b) illustrates the equivalent circuit and the input impedance Zin1 and Zin2 is drivenas below. The input impedance that the resistive component is equal

2

R

L

. In (3.10), also see the capacitive and inductive reactance, which is a function of the input phase offset angle

ψ , meaning that the capacitive and inductive component is produced by phase

difference between two input signals.

(a)

(b)

Fig. 3.8 (a) Two input ports of combiner (b) The Norton equivalent circuit of the pair of series outphasing voltage sources

It can be derived as

The reactance of Zin1 and Zin2 may lead to efficiency degradation. Chireix combiner was proposed to improve the efficiency by adding parallel compensating components at the cost of linearity degradation. The Chireix combiner and its small-signal equivalent circuit are illustrated in Fig. 3.9 (a) and (b).

(a)

(b)

Fig. 3.9 (a) Chireix combiner (b) Equivalent circuit

The jB is the admittances of the compensating components.

According to Kirchhoff’s low, the current can be expressed as (3.12)

jB

After using Ohm’s low the input admittance could be calculated as (3.13)

1 ) Therefore, the input impedance is inversion of (3.13).

)) )

))

The maximum efficiency would be obtained while the imaginary part of Zin1 and Zin2

equal to zero. The (3.14) expresses the maximum efficiency in our interesting phase what the compensating component value is.

There is a simple simulation where the phase offset is chosen in 0 and 45 degrees.

Both the characteristic impedance and output loads is 50 ohm. While the compensate phase at 0 degree that do not need compensating component and the compensating phase at 45 degrees, according to (3.14) the Lcom and Ccom are 1.613 nH and 630 fF respectively. Using the Chireix combiner would improve the efficiency in outphasing modulation system. Fig. 3.10 shows the efficiency enhancement by adding parallel compensating components but it leads to linearity degradation. Many researcher were analysis this topic in [19-21]. This would be further discussed in Section 3.4.4.

3.5.3 Efficiency and Linearity

1. Efficiency

The instantaneous efficiency of the Chireix combiner was driven by [19] shown in (3.15)

Input phase difference (degree)

C o mb in er E ff ici en c y

0 degree 45 degree (B)

(A)

Fig. 3.10 Compensating phase (A) 0 degree (B) 45 degree

where Pout is the power transfer to the output load, and Pin1 and Pin2 are two available powers at the input of the combiner and y is RL/Zo.

As mentioned in the previous section, with the use of compensating components, the reactive elements can be eliminated, resulting in the maximum transfer efficiency.

The equation (3.15) can be simplified to

2

Equation (3.16) is the best condition for all compensating phase. While the characteristic impedance of λ/4 transmission line is equal 50 ohm. Then the (3.17) can be written as

The optimal efficiency of combiner, shown in Fig, can be calculated for all input phase offset angle θ by equation (3.17). Fig. 3.11 shows the optimal efficiency achieves 80% above while the compensating phase is from 0 degree to 63 degrees.

0 Input phase offset (degrees)

E ff ici en cy ( % )

Fig. 3.11 The optimal efficiency of combiner for all input offset angle

Because of equation (3.16) is a function of Zo and θ. There are two cases for y>1 and y<1.

Case1: y>1

According to (3.16), we recalculated the optimal efficiency for all input offset angle. Then we obtained the optimal efficiency of combiner shown in Fig. 3.12. The optimal efficiency could achieve 100% at the higher input offset angle. But the optimal efficiency is quiet low at the lower input offset angle.

Case1: y<1

0 20 40 60 80 100 120

0 10 20 30 40 50 60 70 80 90 Input phase offset (degrees)

E ff ici en cy ( % )

Fig. 3.12 (a) Zo is 20(b) Zo is 30 (c) Zo is 40

0 20 40 60 80 100 120

0 10 20 30 40 50 60 70 80 90 Input phase offset (degrees)

E ff ici ency ( % )

Fig. 3.13 (a) Zo is 60. (b) Zo is 70.

We recalculated the optimal efficiency for all input offset angle and plot the curve of the optimal efficiency again shown in Fig. 3.13 It is flat and quite high after adding compensating components, but the optimal efficiency is dropped rapidly while the input offset angle is larger 50 degrees.

2. Linearity

There is a trade-off between efficiency and linearity, sine adding compensating components would degrade the linearity of the Chireix combiner [22]. Fig. 3.14 illustrates the effect of the compensating phase on the linearity. Perfect linearity occurred while compensating angle is zero thereafter the distortion is more evident while the compensating angle increases.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.0 0.2 0.4 0.6 0.8 1.0

Normailized Vin (V)

N o rm a iliz e d V o u t (V )

Fig. 3.14 Effect of compensating angle at the linearity of Chireix combining system (a) w/o (b)15 degrees (c) 45 degrees and (d) 75 degrees

3.6 Circuit Realization

The proposed outphasing class D low-power amplifier is shown in Fig. 3.15. The transistor Mn1/Mp1 or Mn2/Mp2 forms a class D power amplifier which amplifies the input signals to the combiner. The transformer is used to combine the signals providing by two path of class D power amplifier. Further discussions about class-D power amplifier and transformer will be presented in section 3.6.1 and 3.6.2.

Fig. 3.15 Schematics of outphasing power amplifier

3.6.1 Combiner comparisons?

The Wilkinson combiner is first used in outphasing technique in this work. Fig.

3.16 (a) and (b) show the efficiency versus input offset angle and probability density function (PDF) of the OFDM modulation system respectively. The drain efficiency is simulated under ideal Wilkinson combiner. In OFDM modulation system, the PDF is most located at 70 degrees, which the efficiency dropped severely. Therefore, it degraded the average efficiency significantly. After calculation, the average efficiency is only 13 percents only for ideal Wilkinson combiner. Then the Chireix combiner is chosen to improve the efficiency by adding compensating components at 70 degrees.

But it results in severe linearity degradation. This is the fundamental trade-off between efficiency and linearity of a power amplifier.

In this work we used the transformer combining two input signals. The maximum efficiency of transformer will be 180 degrees. Fig. 3.17 shows the efficiency of transformer without phase compensation for linearity consideration.

Fig. 3.16 (a) The efficiency of the Wilkinson combiner V.S input offset angle (ideal combiner) (b) The PDF of the OFDM modulation system

0.0

Input phase angle (degrees)

N or m a iliz e d output v olt a ge ( V

0

)

Fig. 3.17 Combiner Efficiency versus input offset angle using transformer

3.6.2 Why class-D power amplifier?

There are many types of switched-mode power amplifier including class D、class E and class F etc. The efficiency of these amplifiers can in principle be excellent. The reasons of choosing class D power amplifier mentioned as below.

The characteristics of the Class E amplifiers are not appropriate to outphasing systems with lossless power combiner. Because of the characteristic of zero-voltage switching is critically dependent on the phase of the output load impedance. Therefore, the class E amplifiers are best suited for lossy combiners [18].

For class-F power amplifier, both efficiency and output power are boosted by using harmonic impedance in the output network. The load of even harmonics frequency (2fo, 4fo…) must be low impedance and odd harmonics (3fo, 5fo…) frequency must be high impedance except fundamental frequency [22]. It is difficult to realize the impedance at each harmonic frequency for fully on chip design,

moreover the more harmonics impedance result in more loss at the output.

The class-D power amplifier does not have zero-voltage switching and harmonics impedance issue of class-E and class-F amplifiers. For those reasons we chosen class D power amplifier.

In this work we care the average efficiency of the outphasing power amplifier more than PA performance.

3.7 Chip Layout and Post-Simulation Results

3.7.1 Chip Layout

Fig. 3.18 shows the chip layout of outphasing power amplifier in TSMC 180nm CMOS technology. The chip area occupies 1400x1000 um² including pads. The bounding wire inductor causes performance degradation. Thus, there are many pads of VDD=1.2 V and ground so that decreasing the effect of pounding wires.

Fig. 3.18 Chip layout

3.7.2 Post-Simulation Results 1. Transformer

The parasitic capacitance exists in metal to substrate shown in Fig. 3.19 resulting in difference of input angle shifts to 74 degree as demonstrated in Fig. 3.20.

Fig. 3.19 Parasitic capacitance of transformer

0.0 0.2 0.4 0.6 0.8 1.0

0 15 30 45 60 75 90

Input phase angle (degrees)

N o rm a il iz e d out put v o lt a g e (V )

Fig. 3.20 EM simulation result

2. Stability

Fig. 3.21 and Fig. 3.22 show the stability circle at DC to 14 GHz of load and source plane.

Fig. 3.21 LSB circle

Fig. 3.22 SSB circle

3. Performance of power amplifier

I. Fixed the input offset angle

Simulated output power versus input power at 1.4 GHz is shown in Fig. 3.23.

The output power is saturated at input power if the input power is larger than -3 dBm.

and the gain of the outphasing power amplifier is 11 dB、9 dB and 12.5 dB for TT、

SS and FF respectively.

Fig. 3.24 shows the simulated drain efficiency of outphasing PA versus input power. Drain efficiency is over 38% above at 1dB compression point. Fig. 3.25 illustrates the simulated PAE versus input power. For TT corner, the PAE is over 29%

above at 1 dB compression point.

-15 -10 -5 0 5 10

-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 Pin (dBm)

Po u t (d B m )

TT SS FF

.

Fig. 3.23 Output power versus input power simulation result

0

Fig. 3.24 Drain Efficiency simulation result

0

Fig. 3.25 PAE simulation result

4. Outphasing response

Simulated output power versus input offset angle at 1.4 GHz is shown in Fig 3.26. The maximum power transfer at 80 degrees input offset angle, and the drain efficiency versus input offset angle is given in Fig. 3.27.

-10

Input phase offset (degrees)

P out ( dB m )

TT SS FF

Fig. 3.26 Output power versus input phase difference simulation result

0

Input phase offset (degrees)

D rai n E ffi ci en cy ( %

Fig. 3.27 Drain efficiency versus input phase difference simulation result

5. Frequency response

Fig 3.28 demonstrates the gain of power amplifier versus input frequency. The phase difference of two input signal is 83 degrees and input power is -5 dBm.

0 2 4 6 8 10 12 14

1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Input Frequency (GHz)

Ga in ( d B )

Fig. 3.28 Frequency response

6. Average efficiency

In wireless communication system, we care the average efficiency more than efficiency of power amplifier itself. Therefore, the average efficiency can be calculated base on the probability density function of OFDM modulation signal. Fig.

3.29 illustrates the OFDM phase distribution and corresponding efficiency. In this work the average efficiency is 33.16% under 14 mW dynamic power consumption.

3.7.3 Performance summary

Finally, a performance summary is given in the Table 3.2. The proposed

outphasing class D low-power amplifier achieves system efficiency to 33.16 % under 14 mW dynamic power consumption.

0 10 20 30 40 50 60 70 80 90

OFDM Phase Distribution and Corresponding Efficiency

Distrbution Efficiency Average Efficiency = 33.16%

0 10 20 30 40 50 60 70 80 90 Phase

Fig. 3.29 Average efficiency of OFDM modulation system Table 3.2 Performance summary

Performance This work

System Efficiency (ideal combiner) (%) 13 →50

System Efficiency (%) 33.16 %

DC power (mW) 14

Power Gain (dB) 11

Pout (dBm) 7

3.8 Summary

Outphasing is one of the most popular techniques that improve the efficiency and linearity. It does not need other circuit aid. In this work, the circuit only consumes 14 mW under 1.2V supply voltage in TSMC 180 nm standard CMOS process. It can be used in wireless data communication for biomedical applications. The power combine technique is most critical factor of outphasing power amplifiers. Therefore, the type of combiners and power amplifiers may be chose with modulation signals appropriately.

Chapter IV

Conclusions and Future Work

4.1 Conclusion

In this thesis, two low-power transmitter circuits are implemented and design one is frequency tripler with fundamental cancelling the other is outphasing power amplifier. Both of them are fabricated using 180 nm standard CMOS technology.

The frequency tripler with fundamental cancelling was verified to has 35 dB

HRR

1 which is impressive for frequency multiplier circuit design. The power consumption is another merit compared to other published works. Therefore, this frequency tripler features quadrature signal generation, which is very useful in modern RF transceivers associated with quadrature modulation.

The frequency tripler with fundamental cancelling was verified to has 35 dB

HRR

1 which is impressive for frequency multiplier circuit design. The power consumption is another merit compared to other published works. Therefore, this frequency tripler features quadrature signal generation, which is very useful in modern RF transceivers associated with quadrature modulation.

在文檔中 應用於射頻發送端之低功率電路 (頁 43-0)