3.1 Introduction
The proposed jitter compensation scheme requires a timing measurement circuit to per-form the jitter-to-digital conversion so that the sampling error introduced by the clock jitter can be compensated in the digital domain. The JDC in Figure 2.2 contains a time-to-digital converter (TDC) that digitizes the timing (or phase) difference between two clocks of identical frequency. As shown in Figure 3.1, a TDC is used to compare the rising edges of two clocks V1 and V2. For a 16-bit 80 MS/s ADC system, the TDC must perform the conversion every clock cycle and have a resolution better than 1 ps.
In order to quantized the timing information into the digital code, several time-to-digital conversion circuits had been demonstrated previously in literature. An up-to-date survey can be found in [30]. Most of them require certain types of precision circuits, such as delay elements with precise delay [31, 32], oscillators with precise frequency [33], or time-to-voltage converters with precise conversion function [34, 35]. In this chapter, we will discuss various types of TDC and their limitations.
3.2 Counter-Based TDC
The most direct method for measuring a time interval is to use a counter. As shown in Figure 3.2, the counter is triggered at the raising edge of V1 signal and stopped at the
37
td V1
V 2
Figure 3.1: Timing difference measured by a TDC.
raising edge of V2signal. Therefore, the timing interval to be measured is proportional to the resulting count,
td ≈ N × Tc (3.1)
where Tc is the clock period of the counter and N is the resulting count which is 6 in Figure 3.2.
The resolution of such TDC is limited by the period of the counter clock. Like the quantization noise in an ADC, the root-mean-squared value (rms) of the quantization step for the counter based TDC can be derived as [36]
∆tq,rms= πTc
8 (3.2)
The accuracy of counter based measurements can be improved by taking a series of measurements of the same interval td, and averaging the results [37]. Therefore, this technique is often used for frequency measurement since several periods can be measured and a better resolution can be obtained by average. For example, if M successive periods are measured for a periodic signal with frequency of fs, i.e. td = M × (1/fs) ≈ N × Tc. Thus, the frequency under measured is
fs = M
N × Tc (3.3)
3.3. TIME-TO-AMPLITUDE METHOD 39
V 2 td
Tc V 1
Trigger Stop
Figure 3.2: A counter-based TDC timing diagram of conversion.
This technique is unsuitable for measuring aperiodic signals with short time intervals in the order of picoseconds, such as the clock jitter.
3.3 Time-to-Amplitude Method
Another commonly used method is based on time-to-amplitude conversion [38, 39, 40].
As shown in Figure 3.3, a capacitor is first charged or discharged by a fixed current for the time interval to be measured, then an ADC is used to digitize the voltage on the capacitor.
The capacitor voltage is reset to zero between measurements. The voltage on the capacitor after it stops charging is
Vc= Ic
C × td (3.4)
For a short td, a high resolution ADC is required to digitize the voltage on the capacitor and is difficult to implement. To simplify the design, a dual-slope ADC is often used together with the time-to-amplitude method. The dual-slope technique first charged a capacitor with fixed current, Ic, for the time interval to be measured then a smaller current,
ADC
Figure 3.3: A time-to-amplitude TDC timing diagram of conversion.
Id, is used to discharge the capacitor to zero. As shown in Figure 3.4, the relation between the time interval to be measured, td, and the time interval for discharging the capacitor to zero, tm, is
td = Id
Ic × tm (3.5)
If Ic = 100Id, tm is equal to 100 × td. Thus, we can measure tm instead of td to obtain a better resolution. However, if tdis small, the switching noise such as clock feed through and charge injection will dominant the resolution.
3.4 Tapped Delay Line TDC
In a tapped delay line TDC as shown in Figure 3.5a, V1signal is passing through a delay line and each delay buffer produces a delay equal to τ1. The output of each delay buffer is connected to the data input of a flip-flop. All the flip-flops are triggered at the raising edge of V2 signal and the TDC’s output m is generated by summing the digital outputs from all flip-flops. Like a flash ADC, the adder can be replaced by an edge detector to perform the thermometer code to binary code conversion. As shown in Figure 3.5b, the timing interval to be measures is
td ≈ m × τ1 (3.6)
3.4. TAPPED DELAY LINE TDC 41
t d
V c
t tm
Figure 3.4: A dual-slope TDC timing diagram of conversion.
and m is equal to 4 in Figure 3.5b. To ensure that τ1is known accurately, the delay chain is often controlled by a delay-locked loop (DLL) [31, 41, 42] or a phase-locked loop (PLL) [33, 43].
The resolution of the tapped delay line TDC is determined by the delay of the delay element τ1, which is limited to a gate delay. To provide a finer resolution, a vernier tapped delay line technique is used [31, 43, 44]. In the vernier tapped delay line technique, one tapped delay line drives the flip-flop clock inputs, while the other tapped delay line drives the flip-flop data inputs as shown in Figure 3.6a. The clock tap delay is slightly longer (or shorter) than the data tap delay. The vernier-based TDC is equivalent to a delay line TDC shown in Figure 3.6b, the effective tap delay is then the difference between the clock and data tap delays, i.e.
td ≈ m ×(τ1− τ2) (3.7)
Therefore, resolutions better than a gate delay can be achieved.
The resolution is sensitive to the gate delays, thus timing calibration of the delay chain is necessary [44, 45, 46, 47]. Even with appropriate calibration, this method still suffered from the noise induced by the delay line itself, and the error is accumulated along the delay line.
Q1 Q
Figure 3.5: (a) TDC utilizing a tapped line. (b) Timing diagram of a tapped delay-line TDC.
3.4. TAPPED DELAY LINE TDC 43
Figure 3.6: (a) A vernier delay-line TDC. (b) An equivalent circuit model of a vernier delay-line TDC containing a single delay line, and ∆τ = τ1− τ2.
3.5 Stochastic TDC
The TDC used in our design is based on the stochastic TDC architecture [28, 48]. It does not use any precision circuit, and can be easily realized in a standard CMOS VLSI technology.
To understand the stochastic TDC in an easy way, Figure 3.7 shows the relationship between a stochastic TDC and a delay-line TDC. Each delay cell in the delay-line is replaced by a timing offset tosn. The timing offset originates from the mismatch of the flip-flop itself. Thus, a stochastic TDC conducts the time-to-digital conversion by exploring the statistics of a group of flip-flops or timing comparators (TCMPs). Like a flash ADC, it can easily complete the conversion in one clock cycle. It can provide the conversion for every clock cycle continuously. Furthermore, it can improve the conversion resolution simply by adding more TCMPs. Figure 3.8 shows a TCMP example [28]. It compares the rising edges of two clocks, V1 and V2. Ideally, its output is a digital 1 if the timing difference td > 0. If td < 0, the output is a digital 0. However, a practical TCMP exhibits an offset, tos. The offset is mainly caused by devices mismatches and interconnect mismatches. The TCMP now yields an output of digital 1 only if td > tos; otherwise, the output is a digital 0.
Figure 3.9 shows the architecture of a stochastic TDC. It contains L TCMPs. Each TCMP detects the polarity of (td − tos) and has its own tosoffset. For every clock cycle, the TDC’s output, m, is generated by summing the digital outputs from all TCMPs. Thus, mis the number of TCMPs with a digital 1 output. Figure 3.10 illustrates the probability density function (pdf) of tosof a TCMP and the TDC transfer function. From the central limit theorem, the pdf of tosis approximately a normal distribution, G(tos), which is
G(tos)= 1 σ√
2πe−t2os/(2σ2) (3.8) where σ is the standard deviation of tos. The averaged td-to-m TDC transfer function can be obtained by integrating over this pdf, i.e.,
m= L × Ztd
−∞
G(tos)dtos (3.9)
3.5. STOCHASTIC TDC 45
Figure 3.7: Relationship between a delay line TDC and a stochastic TDC. (a) Alternative representation of delay line TDC. (b) A stochastic TDC by utilizing the offset.
V2
Figure 3.8: Timing comparator (TCMP).
In practice, m can only be an integer between 0 and L. This TDC has its input range proportional to σ. Its resolution is a function of L.
A TDC converts an input tdinto a digital code m. The input range of a TDC is divided into different segments. Each segment is mapped to a different m code. Figure 3.11 shows an example of time-to-digital conversion for L = 6. The tos1 to tos6are the timing offset of the six TCMPs respectively. Note that tosnis not necessary the timing offset of the n-th TCMP in Figure 3.9. If m= 2 at the k-th sampling, i.e., Dt[k] = 2, there are two TCMPs with a digital 1 output. The clock jitter at the k-th sample is ∆t[k] and tos2 < ∆t[k] < tos3. Thus, as long as the timing offset of all the TCMPs are known, the TDC can be used to measure the timing difference between two signals. However, similar to an ADC, a TDC also introduces quantization noise, ∆tq[k] as shown in Figure 3.12. For example, as long as tos2 < td < tos3, the output of the TDC is always m= 2. The power of the quantization error when m= 2 is
∆t2q,2= ∆t2s,2
12 (3.10)
and ∆ts,2is the step size for m= 2. Thus, the quantization error for a giving TDC can be derived as
3.5. STOCHASTIC TDC 47
V1 V2
1
TCMP TCMP TCMP
2 L
m
Figure 3.9: Stochastic time-to-digital converter (TDC).
tos
td
−1 σ +1 σ +2 σ
−2 σ 0
−1 σ +1 σ +2 σ
−2 σ 0
0.5L m L
Figure 3.10: TDC Transfer function and tosprobability density function (pdf).