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Clock Jitter Measurement and Compensation
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Student : Chi-Wei Fan
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A Dissertation
Submitted to Department of Electronics Engineering
and Institute of Electronics
College of Electrical and Computer Engineering
National Chiao-Tung University
in partial Fulfillment of the Requirements
for the Degree of
Doctor of Philosophy
in
Electronics Engineering
March 2010
Hsin-Chu, Taiwan, Republic of China
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Clock Jitter Measurement and Compensation
for Analog-to-Digital Converters
Student : Chi-Wei Fan
Advisor : Jieh-Tsorng Wu
Department of Electronics Engineering
and Institute of Electronics
National Chiao-Tung University
Abstract
In a modern communication receiver, the received continuous-time analog signal is quantized into a discrete-time digital sequence by an analog-to-digital converter (ADC) so that the complex signal processing can be performed in the digital domain. The ADC requires a periodic clock as a timing reference for input sampling. If the sampling clock exhibits jitter, the ADC suffers from sampling errors and its signal-to-noise ratio (SNR) performance is degraded. For a low-speed low-resolution ADC, the sampling error due to clock jitter is not crucial. As the progress of advanced communication system, the opera-tion speed and the resoluopera-tion of the ADC are also increased. An accurate sampling clock is essential for a high-speed high-resolution ADC.
Clock jitter can be measured and digitized by a time-to-digital converter (TDC). With appropriate calibration technique, the output code of the TDC can be translated in to the corresponding jitter information. This jitter information is then used to compensate the
analog-to-digital converters.
A 7-bit 80-MS/s TDC was fabricated using a 65 nm CMOS technology. The clock jitter of an ADC is measured by the TDC. We also demonstrate a new digital calibration technique for the TDC. The calibration can be performed in the background without in-terrupting the normal ADC and TDC operation. The proposed technique is immune to device and interconnection mismatches, and is not sensitive to the waveforms of the input clocks either. The resolution of the 7-bit TDC is 0.27 ps. The TDC occupies a die area of 0.1mm2while consuming 20 mW from a 1.2 V supply.
The TDC is applied to a 16-bit ADC for the clock jitter measurement and compen-sation. Two different system scenarios are covered: 1) an ADC with a clean external clock and 2) an ADC with an external clock as the main jitter source. For the first sce-nario, the SNR of the 16-bit ADC is improved from 71.2 dB to 77.3 dB for an optimized delay-locked loop (DLL) and 60.8 dB to 74.4 dB for an ill-conditioned DLL by the jitter correction at a sine wave input frequency of 29 MHz. For the second scenario, the pro-posed jitter correction technique achieves an equivalent sampling jitter root-mean-squared value (rms) of 4 ps when the jitter rms of the original sampling clock is 8.2 ps.
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»ñø;. ºÓ»ÜèÜOÜ` vContents
Z` i
English Abstract iii
* v
List of Tables xi
List of Figures xiii
1 Introduction 1 1.1 Motivation . . . 1 1.2 Organization . . . 6 2 Jitter Compensation 9 2.1 Introduction . . . 9 2.2 SNR of an ADC . . . 9
2.3 Proposed Jitter Compensation Configuration . . . 12
2.4 Jitter Compensation Filter . . . 14
2.5 Non-Ideal Effects in Jitter Compensation . . . 17
2.5.1 Quantization Error and Sampling Error . . . 18
2.5.2 Finite Precision of the Filter Coefficients hc . . . 19
2.6 Simplified Jitter Compensation Filter . . . 22
2.7 A 16-bit 80 MS/s ADC Design Example . . . 29
2.8 Summary . . . 30
3.2 Counter-Based TDC . . . 37
3.3 Time-to-Amplitude Method . . . 39
3.4 Tapped Delay Line TDC . . . 40
3.5 Stochastic TDC . . . 44
3.6 Summary . . . 53
4 Jitter Compensation with Clean External Clock 55 4.1 Introduction . . . 55
4.2 Jitter Compensation with Clean External Clock . . . 56
4.3 TDC Background Calibration Principle . . . 59
4.4 Signal Reconstruction Filter . . . 62
4.5 Jitter Calibration Processor . . . 66
4.6 A 16-bit 80MS/s ADC Design Example . . . 72
4.7 Circuit Implementations . . . 74
4.7.1 Stochastic Time-to-Digital Converter . . . 75
4.7.2 Variable Delay Line . . . 76
4.7.3 Delay-Locked Loop . . . 77
4.8 Experimental Results . . . 80
4.9 Summary . . . 86
5 Jitter Compensation with Jittering External Clock 87 5.1 Introduction . . . 87
5.2 Jitter Compensation with Jittering External Clock . . . 88
5.3 A 16-bit 80MS/s ADC Design Example . . . 94
5.4 Circuit Implementations . . . 96
5.5 Experiment Results . . . 97
5.6 Implementation Issues . . . 102
5.7 Summary . . . 103
6 Conclusions and Future Works 105 6.1 Conclusions . . . 105 6.2 Recommendations for Future Investigation . . . 106
Appendix A 107
Bibliography 109
F 115
Publication List 116
List of Tables
2.1 Sign-magnitude expression of hs[n] . . . 29
List of Figures
1.1 Block diagram of an analog front-end. . . 1
1.2 Sampling-time uncertainty (aperture jitter). . . 2
1.3 Signal-to-noise ratio due to aperture jitter. . . 4
1.4 Jitter compensation scheme proposed by Tourabaly and Osseiran. . . 5
2.1 Continuous-to-Discrete Conversion of an ADC. . . 10
2.2 Jitter compensation block diagram. . . 12
2.3 A graphic illustration of jitter compensation principle. . . 14
2.4 A jitter compensation filter with 2M+ 1 taps. . . 15
2.5 hc[n, ˆ[k]] and qh[n, ˆ] plots example when ˆ=0.001 and the filter coeffi-cients are represented by binary fraction of 18-bit wide. . . 20
2.6 SNR results of jitter compensation of different Bh. Circles are simulations with irrational hc[n, ˆ[k]]= sinc(n − ˆ[k]) . . . 21
2.7 A graphic illustration of simplified jitter compensation principle. . . 22
2.8 A simplified jitter compensation filter with 2M+ 1 taps. . . 23
2.9 Pe,r normalized to the quantization noise Pq Plots. . . 26
2.10 The ADC output power spectrum before and after the jitter compensation for M = 7. . . 32
2.11 The ADC output power spectrum before and after the jitter compensation for M = 7. . . 33
2.12 SNR results of jitter compensation for M = 7. Circles are from simula-tions. Lines are from calculasimula-tions. fi = ωi/(2π) is the input frequency, and fs = 1/Ts is the sampling rate. . . 34
3.1 Timing difference measured by a TDC. . . 38
3.2 A counter-based TDC timing diagram of conversion. . . 39
3.3 A time-to-amplitude TDC timing diagram of conversion. . . 40
3.4 A dual-slope TDC timing diagram of conversion. . . 41
3.5 TDC utilizing a tapped delay-line. . . 42
3.6 A vernier delay-line TDC. . . 43
3.7 Relationship between a delay line TDC and a stochastic TDC. . . 45
3.8 Timing comparator (TCMP). . . 46
3.9 Stochastic time-to-digital converter (TDC). . . 47
3.10 TDC Transfer function and tosprobability density function (pdf). . . 47
3.11 An example of time-to-digital conversion for L = 6. . . 48
3.12 Quantization error of a TDC. . . 49
3.13 Binary search process for timing offset extraction. . . 50
3.14 Histogram of timing comparator offset, tos, from 1000 Monte Carlo sim-ulations. . . 51
3.15 ∆tq,rmsperformance for TDC with different L at various ∆trmsinput level. 52 4.1 A jitter compensation scheme with clean external clock. . . 56
4.2 A simplified jitter compensation filter with 2M+ 1 taps. . . 57
4.3 Code-density test. . . 58
4.4 Jitter compensation at the k-th sampling and Dt[k]= m. . . 60
4.5 TDC background calibration principle. . . 60
4.6 Signal reconstruction. . . 62
4.7 A signal reconstruction filter with 2N+ 1 taps. . . 63
4.8 An ideal low-pass filter. . . 64
4.9 Block diagram of jitter calibration processor, JCP1. . . 66
4.10 Conversion gain of the JDC using JCP1 for different M and different input frequencies. . . 69
4.11 Conversion gain of the JDC using JCP1 for M=7, M=8 and M=31. . . . 70
4.12 Cyclic multiply-and-accumulate architecture to realize the SRF. . . 71
4.13 Calibration for different TDC output codes, Dt[k]. . . . 72
4.14 SNR of the ADC system of Figure 4.1 at various input frequencies. . . 73
4.15 Jitter compensation experiment setup. . . 74
4.16 Stochastic TDC block diagram. . . 75
4.17 Timing comparator (TCMP) schematic. . . 76
4.18 The probability density function (pdf) of TCMP tos. . . 77
4.19 An 8-bit digitally-controlled delay cell. . . 78
4.20 Block diagram of the digital delay-locked loop. . . 79
4.21 Discrete-time model of the digital delay-locked loop. . . 79
4.22 Jitter amplification of the DLL. . . 80
4.23 Chip micrograph. . . 81
4.24 Photo of the jitter correction setup with the ADC evaluation board. . . 81
4.25 Measured TDC transfer function and INL. . . 82
4.26 Measured ADC output power spectrum before and after the jitter correction. 83 4.27 Measured ADC SNR versus input frequency. . . 84
4.28 Measured sine wave jitter of the CLKiclock. . . 85
4.29 Measured ADC output power spectrum before and after the jitter correc-tion when the CLKijitter is a sine wave. . . 85
5.1 A jitter compensation scheme with jittering external clock. . . 88
5.2 Relations between the CLK and CLKd clocks. . . 89
5.3 Block diagram of jitter calibration processor, JCP2. . . 90
5.4 Signal reconstruction in JE1 and JE2. . . 91
5.5 Conversion gain of the JDC using JCP2. . . 92
5.6 Simulated ADC output spectrum with jitter compensation for different value of b. . . . 95
5.7 Simulated SNRs of the ADC system of Figure 5.1. . . 96
5.8 Jitter compensation experiment setup. . . 97
5.9 Photo of the jitter correction setup with the ADC evaluation board. . . 98
5.10 Measured TDC transfer function. . . 99
Chapter 1
Introduction
1.1
Motivation
In a modern communication receiver, an analog-to-digital converter (ADC) first samples the received continuous-time analog signal and then quantizes the sampled data into a discrete-time digital sequence, so that the complex signal processing can be performed in the digital domain. As shown in Figure 1.1, an input signal first passes through an analog signal processing block, the block is usually a low-pass filter or a band-pass filter to limit the bandwidth of the input signal. Then a programmable-gain amplifier (PGA) is placed in front of the ADC, adapting the loss of transmission to relax the dynamic range requirement of the ADC. The gain of the PGA is digitally controlled by an automatic gain control (AGC) loop. The ADC quantizes the amplified analog signal into a digital sequence. Finally, the required signal processing can be performed by the digital signal
Analog
Signal Processing PGA
AGC
V
i ADC DSP Do
Figure 1.1: Block diagram of an analog front-end.
t ∆ ∆v fs kTs i V (t) V t i V [k]
Figure 1.2: Sampling-time uncertainty (aperture jitter).
processing (DSP) block to generate the output signal.
There are many ways to qualify an ADC’s performance such as spurious-free dy-namic range (SFDR) and signal-to-noise ratio (SNR). The SFDR is usually dominated by the non-linearity of the input to output transfer curve and is solved by many cali-bration techniques. These techniques include linearizing the transfer curve of the mul-tiplying digital-to-analog converter (MDAC) in pipelined ADCs [1, 2, 3, 4, 5, 6, 7, 8], trimming the input-referred offsets of the comparators in flash ADCs or two-step ADCs [9, 10, 11, 12, 13]. To further improve the conversion linearity, there are schemes which also calibrate the non-linearity of the amplifier [2, 5, 6, 8].
The contributions to SNR of these techniques are restricted since the SNR is usually dominated by the environment noise and the quality of the sampling clock. The former is usually solved by enlarge the signal swing to increase the signal power, or use larger sampling capacitors to decrease the thermal noise. The latter problem is usually ignored with the assumption that a pure sinusoid signal source is available and the noise introduced by the clock buffers is neglectable. The most commonly used method for a clock reference is a crystal oscillator followed by a narrow-band high order band-pass filter. However, as the conversion rate of the ADC is increased, a phase-locked-loop (PLL) based clock generator is inevitable which results in a noisier clock source.
A periodic clock is required to provide a reference for the sampling time. If the sam-pling clock jitters, samsam-pling error occurs during the samsam-pling process [14, 15]. Excess clock jitter can degrade the SNR performance of an ADC. Figure 1.2 shows the effect of
1.1. MOTIVATION 3
clock jitter. The Vi(t) signal is sampled by the ADC every Ts, where Ts = 1/fs and fsis the sampling rate of the ADC system. Therefore, the k-th sampling time is kTs ideally. If the sampling clock jitters, the signal is sampled at t = kTs + ∆t instead of t = kTs. Thus the sampled data is ∆V deviated from an ideal sample, which degrades the SNR performance.
If the clock jitter dominates the SNR of an ADC, the SNR can be approximated as [14]
SNR= 1
ω2i ×(∆trms)2
(1.1)
where ∆trms is the rms of ∆t. If the quantization error dominates the SNR of an B-bit ADC, the SNR can be approximated as [16]
SNR= 1
(2/3)2−2B (1.2)
Figure 1.3 shows the SNR for an ADC limited by aperture jitter for various jitter values (the sloped solid lines) and the quantization noise limited performance at various reso-lutions (the horizontal dashed lines). For an ADC with 120 MS/s sampling rate, if the analog input is a 60 MHz sine wave and the clock jitter is random, the root-mean-squared value (rms) of the clock jitter must be less than 0.5 ps to ensure a 12-bit resolution. If the rms value of the clock jitter deteriorates to 2 ps, the resolution of the ADC degrades to 10-bit. As the conversion rate or the resolution of the ADC increase, the jitter requirement also increased.
Clocks generated from PLL can hardly achieve this stringent jitter requirement [17]. Low-jitter clocks, mostly based on crystal oscillators, are inflexible and expensive. There are many researches of low noise PLL design. Such as optimizes the loop bandwidth of a PLL to compromise the noise of different frequency response [18], or lower the sensitivity to supply noise for a PLL [19] or for a voltage-controlled oscillator (VCO) [20, 21, 22, 23]. There are also investigations strive to overcome the difficulties of low noise VCOs designs since the VCO usually dominates the jitter performance of a PLL [24, 25, 26]. Although these methods reduce the jitter of a PLL dramatically, it is still hard to meet the specification for a high speed high resolution ADC.
Figure 1.3: Signal-to-noise ratio due to aperture jitter.
The importance of having a low jitter clock source for an ADC is well-known. While most of the researches try to generate a low jitter clock source, it is possible to compensate the sampling error of an ADC thus relax the clock jitter requirement. To the best of the author’s knowledge, there is only one other published work that tries to compensate the sampling error caused by clock jitter [27]. As shown in Figure 1.4, the scheme of Tourabaly and Osseiran modulates the analog input before the sampler so that the correct input signal is sampled at incorrect sampling time.
Although the simulation result in [27] shows that a first order approximation of jitter correction is sufficient in respect to produce an SNR improvement of about 15dB, this scheme is hard to implement for several reasons.
1. This scheme requires high-precision analog circuits which are difficult to imple-ment. These circuits include analog multiplier, analog adder, and differentiator. 2. The use of differentiators makes it sensitive to high-frequency noises.
1.1. MOTIVATION 5 d dt Differentiator Absolute Value Extractor
∆
t(t) Low Pass Filterclk V (t) d dt
∆
t(t) d dt d dt Phase Demodulator∆
t (t)3∆
t (t) 1 2 2 1 6 V [k]c s kT +∆
t(kT )s i V (t) SamplerFigure 1.4: Jitter compensation scheme proposed by Tourabaly and Osseiran.
(a) Phase mismatch: There are mismatches of the phase delay between the phase demodulator, the jitter compensation circuit and the sampler. Any difference of the phase delay between them degrades the performance dramatically. (b) Gain error: The gain of the phase demodulator and the gain of the mixer in the
jitter compensation must equal to one to extract the jitter correctly.
For these reasons, only simulation results are given in [27], no experimental result is provided. Moreover, the simulation results show that the improvement on SNR is only 0.0015 dB if the phase delay and the attenuation caused by the differentiator and the mixer are not calibrated.
the clock jitter requirement. Clock jitter is measured and digitized by a stochastic time-to-digital converter (TDC) [28]. This jitter information is then used to compensate the ADC’s sampling error in the digital domain, improving the ADC’s SNR performance. We also propose techniques for TDC calibration. The calibration can be performed in the background without interrupting the normal ADC operation. Theoretical analyses, system simulations and silicon proved measurement results are provided to verify the proposed jitter compensation and TDC calibration techniques. A 16-bit 80 MS/s ADC system is discussed as a design example.
1.2
Organization
The organization of the thesis is described as follows:
Chapter 2 discusses the effect of sampling jitter on a signal. The sampling uncertainty caused by clock jitter makes the sampled signals deviate from their nominal values and the SNR performance is degraded. To improve the SNR when the clock is noisy, a novel jitter compensation technique is proposed. Theoretical analyses and system simulations are provided to verify the technique.
In order to measure the clock jitter, a TDC is required to digitize the timing difference between two clocks of identical frequency. Various TDCs are introduced in Chapter 3, such as the counter-based TDC, the time-to-amplitude TDC, the tapped delay line TDC and the stochastic TDC. The advantages of each kind of TDC and their limitations are also discussed.
Chapter 4 describes a jitter compensation scenario in which the external clock is clean. To estimate the clock jitter accurately, a background calibration technique for TDC is proposed to against the process, supply voltage, and temperature (PVT) variations. The proposed TDC background calibration is based on signal reconstruction. Theoretical anal-yses and simulation results are also provided. A 7-bit 80 MS/s TDC is fabricated in 65-nm CMOS technology to verify the jitter compensation and TDC background calibration con-figuration.
Chapter 5 describes an alternative ADC system in which the external clock is the main jitter source. This scheme can achieve high SNR performance even when a clean clock
1.2. ORGANIZATION 7
source is not available, thus mitigates the jitter requirement for the input clock. The jitter compensation can break the SNR limitation predicted by Equation (1.1).
Chapter 2
Jitter Compensation
2.1
Introduction
A Nyquist-rate analog-to-digital converter (ADC) periodically samples its continuous-time analog input, and converts it into a discrete-continuous-time digital data stream. The ADC requires a periodic clock as a timing reference for input sampling. If the sampling clock exhibits jitter, the ADC suffers from sampling errors, and its signal-to-noise ratio (SNR) performance is degraded [14, 15].
It is possible to relax the clock jitter requirement by introducing jitter compensation in the analog-to-digital signal path. The scheme of Tourabaly and Osseiran [27] modulates the analog input before the sampler so that the correct input signal is sampled. As men-tioned in Chapter 1 this scheme requires high-precision analog circuits, which are difficult to implement. The use of differentiators also makes it sensitive to high-frequency noises. In this chapter, we introduced a digital signal processing technique to relax the clock jitter requirement. Both intuitive interpretations and theoretical analyses will be given.
2.2
SNR of an ADC
As described in Chapter 1, the SNR performance of an ADC is usually dominated by the environment noise and the quality of the sampling clock. The SNR of an ADC can be measured by applying the following sine wave input:
i
V (t)
i
V [k]
f
s
ADC
D [k]
i
Figure 2.1: Continuous-to-Discrete Conversion of an ADC.
Vi(t)= Ai×sin(ωit+ φi) (2.1) where Aiis the amplitude of the input sine wave signal, ωiis the input frequency, and φi is the phase. The Vi(t) signal is sampled at a sampling rate of fs as shown in Figure 2.1, i.e., Ts is the sampling interval and Ts = 1/fs. Thus, the k-th nominal sampled voltage is
Vi[k] = Vi(kTs)= Ai×sin(kωiTs+ φi) (2.2) However, if the sampling clock jitters, the ADC suffers from sampling errors and Equa-tion (2.2) becomes
Vi[k]= Vi(kTs+ ∆t[k]) = Ai×sin(Ωi(k+ [k]) + φi) (2.3) where Ωi = ωiTs is the normalized input frequency, ∆t[k] is k-th jitter of the sampling clock and [k]= ∆t[k]/Ts is the normalized clock jitter. The corresponding output from the ADC at the k-th sampling can be expressed as
Di[k]= Vi(kTs)+ q[k] + Ve[k] (2.4) The Di[k] signal consists of the following: 1) the desired input Vi(kTs); 2) the quantiza-tion noise q[k]; and 3) the sampling error Ve[k] caused by the clock jitter. The SNR of the Di[k] signal is defined as
2.2. SNR OF AN ADC 11
SNR ≡ Ps Pq + Pe
(2.5)
where Ps = (1/2)A2i is the power of the Vi(t) input signal, Pq is the signal power of the q[k] sequence, and Pe is the signal power of the Ve[k] sequence. Here we have ignored the thermal noise power and other environment noise for simplicity. The effect of these noises can be included in Equation (2.5) easily as
SNR ≡ Ps
Pq + Pe+ Pt
(2.6) where Ptis the summation of thermal noise power and other environment noise.
Considering an ideal B-bit ADC with an input range of ±1, it has a uniform quantiza-tion step size of sq = 2/2B. The quantization noise power of an ideal quantization process can be approximated by [16] Pq ≡(q[k])2 = 1 12 × s 2 q = 1 12× 2 2B 2 (2.7) The quantization noise q[k] is assumed to be random and uniformly spreads between ±1/2B.
If the clock jitter is small enough compared to Ts, the k-th sampling error Ve[k] can be approximated by [14] Ve[k] ≈ dVi(t) dt t=kTs × ∆t[k]= Aiωicos(Ωik+ φi) × ∆t[k] (2.8)
where ∆t[k] = [k]Ts is the clock jitter. Therefore, the sampling error power can be expressed as Pe ≡(Ve[k])2 = 1 2A 2 iω 2 i ×(∆trms)2 = 1 2A 2 iΩ 2 i × 2 rms (2.9)
where ∆trms is the root-mean-squared value (rms) of ∆t[k], and rms is the rms of [k]. The clock jitter is assumed to be random and has a mean of zero. Assume that the input is a full-range sine wave expressed as Equation (2.1) with Ai = 1. From Equation (2.5), Equation (2.7), and Equation (2.9), the SNR becomes
i D Dc i V Ts Converter Analog−to−Digital Converter Jitter−to−Digital [k] [k] (t) ADC JCF JDC k
ε
( [k] ) Clockε
[k] Jitter Filter CompensationFigure 2.2: Jitter compensation block diagram.
SNRi = 1 (2/3)2−2B+ ω2 i(∆trms)2 = 1 (2/3)2−2B + Ω2 i 2 rms (2.10)
Equation (2.10) is the maximum SNR performance of an ideal ADC without jitter compensation, which is also the SNR limitation of an ADC theoretically. In this thesis, we introduce a novel jitter compensation technique. The proposed jitter compensation scheme can improve the ADC SNR and break the performance limitation predicted by Equation (2.10).
2.3
Proposed Jitter Compensation Configuration
The basic principle of the proposed jitter compensation is illustrated in Figure 2.2. An ADC samples and quantizes the analog signal Vi(t) and generates the corresponding dig-ital sequence Di[k]. A clock dictates the instants at which Vi(t) is sampled. The k-th sampling time is (k+ [k])Ts where Ts is the nominal sampling interval, and [k] is the clock jitter normalized to Ts. The clock jitter at the k-th sample is ∆t[k] = [k]Ts. A jitter-to-digital converter (JDC) measures the [k] jitter and produces a jitter estimation
ˆ[k] in digital form. The relationship between [k] and ˆ[k] is defined as
2.3. PROPOSED JITTER COMPENSATION CONFIGURATION 13
where e[k] is the JDC measurement error. A jitter compensation filter (JCF) uses the ˆ[k] data to correct the sampling error in Di[k]. The corrected output from the JCF is Dc[k]. The jitter error is compensated in the digital domain, thus no high-precision analog circuit is required and all the problems in [27] can be eliminated.
The theory of jitter compensation is discussed as follows. A band-limited signal Vi(t) can be expressed in inverse Fourier transform as
Vi(t) = 1 2π
Z+ωB
−ωB
V(jω)ejωtdω (2.12)
where V (jω) is the Fourier transform of Vi(t), and ωB is its bandwidth. Neglecting the quantization noise, the Di[k] signal in Figure 2.2 is simply the Vi(t) input sampled at t= (k + [k])Ts. It can be expressed as Di[k]= 1 2π Z+ωB −ωB V(jω)ejω(kTs+[k]Ts)dω (2.13)
Assume that only the k-th sample Di[k] contains a sampling error. Then, the sampling error is caused by a jitter [k] at the k-th sampling. To correct this sampling error, the required JCF is a filter with a frequency-domain transfer function of e−jω[k]Ts. Therefore,
the corrected output from JCF is
Dc[k]= 1 2π Z+ωB −ωB h V(jω) × e−jω[k]Ts i ejω(kTs+[k]Ts)dω = 1 2π Z+ωB −ωB V(jω)ejωkTsdω = Vi(kTs) (2.14)
which is a correct sample at t= kTs.
Figure 2.3 gives an intuitive interpretation of this jitter compensation scheme. Assume that a sampling error occurs at the k-th sampling instant. The Vi(t) is sampled at t = (k+ [k])Ts instead of t = kTs. The magnitude at point A’ is quantized as Di[k]. Thus, the ADC perceives a different ˆVi(t) input instead of Vi(t). The signal ˆVi(t) has a value of Di[k] at t = kTs, denoted as point B. The filter of Equation (2.15) interpolates the value of ˆVi(t) at t = (k − [k])Ts, denoted as point B’, which is a correct estimation of Vi(t) at t= kTs, denoted as point A.
Ts k Ts Ts Vi Vi Ts (k −ε[k]) ( k + ε[k]) Ts A’ A B B’ Magnitude (k+1) (k−1) (t) (t) t
Figure 2.3: A graphic illustration of jitter compensation principle.
2.4
Jitter Compensation Filter
Since the JCF is a filter with a frequency-domain transfer function of e−jω[k]Ts, the
discrete-time impulse response of the linear-phase filter can be obtained by using inverse Fourier transform, i.e., hc[n, [k]]= 1 2π Z+π −π e−jΩ[k]ejΩndΩ = sin (π(n − [k])) π(n − [k]) = sinc(n − [k]) (2.15)
where Ω= ωTsis the normalized frequency.
Figure 2.4 shows a finite-impulse-response (FIR) filter with 2M+ 1 taps that approx-imates the JCF of Equation (2.15). Applying the measured ˆ[k] data from the JDC and assuming ˆ[k] 1, the filter’s output can be expressed as
Dc[k]= k+M X n=k−M Di[n] × hc[k − n, ˆ[k]] ≈ Di[k]+ M X n=1 1 2π Z+ωB −ωB V(jω)ejωkTs2j sin(nωTs) (−1)n× n ˆ[k]dω (2.16)
2.4. JITTER COMPENSATION FILTER 15 D i D i 1 z D i 1 z D i D i 1 z D i 1 z D c [k] [k+M] D i [k+M−1] [k+1] [k] [k−1] [k−M+1] [k−M] h [−M+1,k] h [−1,k] h [M,k] h [−M,k] h [0,k] h [1,k] h [M−1,k] c c c c c c c Figure 2.4: A jitter compensation filter with 2 M + 1 taps.
Exchanging the order of integration and summation, Equation (2.16) becomes Dc[k] ≈ Di[k]+ jˆ[k] π Z+ωB −ωB V(jω)ejωkTsF c(M, ωTs)dω (2.17) where Fc(M, ωTs) = M X n=1 sin(nωTs) (−1)n× n (2.18)
Let Ω = ωTs, if M approaches infinity, Equation (2.18) becomes (Appendix A details the derivation)
lim
M→∞Fc(M, Ω)= − Ω
2 (2.19)
Furthermore, if there is no JDC measurement error so that ˆ[k] = [k], Equation (2.17) becomes Dc[k] = Vi(kTs). This proves that the JCF can compensate the sampling errors and recover the original Vi(kTs).
As an example, consider a sine wave input Vi(t) expressed as
Vi(t)= Ai×sin(ωit+ φi) (2.20) where Aiis the amplitude, ωiis the input frequency, and φiis the phase. The correspond-ing output from the ADC is
Di[k]= Aisin(Ωi(k+ [k]) + φi)= Vi(kTs)+ q[k] + Ve[k] (2.21) From Equation (2.16), the resulting Dc[k] from the JCF can be expressed as
Dc[k] ≈ Di[k]+ ˆ[k]Fc(M, Ωi) × 2Aicos(kΩi+ φi) (2.22) The residual sampling error after the jitter compensation, defined as Ve[k] ≡ Dc[k] − Vi(kTs), can be approximated by
Ve[k] ≈ [Ωi+ 2Fc(M, Ωi)] [k] × Aicos(kΩi+ φi) + 2Fc(M, Ωi)e[k] × Aicos(kΩi+ φi)
2.5. NON-IDEAL EFFECTS IN JITTER COMPENSATION 17
The averaged power of Ve[k] is
Pe = A2i 2 [Ωi+ 2Fc(M, Ωi)] 22 rms+ 2A 2 i[Fc(M, Ωi)]2e,rms2 (2.24) where rmsis the rms of the clock jitter, [k], and e,rmsis the rms of the JDC measurement error, e[k]. If Ai = 1 and the quantization noises are included, the SNR of the signal Dc[k] can be calculated using Equation (2.5), Equation (2.7), and Equation (2.24). From Equation (2.19), if M is so large that Fc(M, Ωi) ≈ −Ωi/2, the SNR becomes
SNRc,∞ = 1 (2/3)2−2B+ Ω2 i 2 e,rms (2.25) Comparing Equation (2.25) with Equation (2.10), clock jitter rms rmsin Equation (2.10) is replaced by the jitter measurement error rms e,rms in Equation (2.25). Thus, the jitter compensation can break the SNR limitation caused by clock jitter if the measured jitter error is smaller than the clock jitter.
2.5
Non-Ideal E
ffects in Jitter Compensation
The SNR after jitter compensation can be predicted using Equation (2.5), Equation (2.7), and Equation (2.24). There are several assumptions when deriving Equation (2.24). These assumptions include:
1. The quantization errors are ignored when sampling Di[k − M] to Di[k − 1] and Di[k+ 1] to Di[k+ M]. However, as the number of the filter taps increases, the quantization noise power also increases.
2. When calculating Dc[k], the sampling errors caused by clock jitter when sampling the neighboring samples are also assumed ignorable.
3. The filter coefficients of Equation (2.15) are irrational numbers. The effect of the finite precision is inevitable when implementing the jitter compensation technique in a system-on-chip (SOC).
2.5.1
Quantization Error and Sampling Error
The quantization errors and the sampling errors of Di[k − M] to Di[k − 1] samples and Di[k+ 1] to Di[k+ M] samples are ignored when Equation (2.16) is used to calculate the compensated ADC output Dc[k]. If these errors are taking into consideration, the result of the jitter compensation can be expressed as
Dc[k] = k+M X n=k−M Di[n] × hc[k − n, ˆ[k]] = k+M X n=k−M Vi(nTs)+ q[n] + Ve[n] × hc[k − n, ˆ[k]] (2.26)
where q[n] is the quantization error of Di[n] and Ve[n] is the sampling error of Di[n] caused by the clock jitter.
As discussed in Section 2.4, Dc[k] is a correct sample of Vi(t) at kTsif there is no JDC measurement error and M is large enough. However, the summation in Equation (2.26) not only compensates the sampling error Ve[k] but also accumulates the quantization er-rors and the sampling erer-rors of Di[k − M] to Di[k − 1] and Di[k+ 1] to Di[k+ M]. The accumulation of these errors may degrade the performance of the jitter compensation.
The error in Dc[k] contributed by sampling Di[k − M] to Di[k − 1] and Di[k+ 1] to Di[k+ M] is defined as Vn[k]= k−1 X n=k−M (q[n]+ Ve[n]) × hc[k − n, ˆ[k]] + k+M X n=k+1 (q[n]+ Ve[n]) × hc[k − n, ˆ[k]] ≈ k−1 X n=k−M (q[n]+ Ve[n]) × (−1)n+1ˆ[k] n + k+M X n=k+1 (q[n]+ Ve[n]) × (−1)n+1ˆ[k] n (2.27)
2.5. NON-IDEAL EFFECTS IN JITTER COMPENSATION 19
Pn ≡(Vn[k])2≈ 2ζ (2) × ˆ2rms×(Pq + Pe) (2.28) where Pq and Peis defined as Equation (2.7) and Equation (2.9) respectively, and
ζ(2) = ∞ X n=1 1 n2 = π2 6 (2.29)
is a well-known Riemann zeta function [29]. Therefore, Equation (2.28) becomes
Pn = 1 3π
2× ˆ2
rms×(Pq + Pe) (2.30)
Comparing Equation (2.30) with Equation (2.7), Pn is usually much smaller than Pq or Pe in practical because that the error power is multiplied by ˆrms2 . Thus, the effect of the quantization errors and the sampling errors of Di[k − M] to Di[k − 1] and Di[k+ 1] to Di[k+ M] are indeed negligible even when the number of filter taps approach to infinity when calculating Dc[k].
2.5.2
Finite Precision of the Filter Coe
fficients h
cIn order to represent the irrational coefficients into digital form, quantization processes are required to convert irrational numbers into digital codes. Similar to an ADC, the con-version also introduces quantization error. Take this effect into account when evaluating Dc[k], the result of JCF can be expressed as
Dc[k]= k+M X n=k−M Di[n] ×hc[k − n, [k]]+ qh[n, [k]] (2.31)
where qh[n, [k]] is the error induced by quantizing the filter coefficients hc[k − n, [k]]. The error of Dc[k] induced by the finite precision of the filter coefficients is defined as Vh,qand Vh,q[k] = k+M X n=k−M Di[n] × qh[n, [k]] (2.32) As long as the Di[n] sequence are independent of [k] sequence, the power of the Vh,q[k] sequence can be expressed as
Figure 2.5: hc[n, ˆ[k]] and qh[n, ˆ] plots example when ˆ=0.001 and the filter coefficients are represented by binary fraction of 18-bit wide.
Ph,q = (Di[n])2× k+M
X n=k−M
q2h[n, [k]] (2.33)
Similar to the quantization error power of an ADC expressed as Equation (2.7), the binary fraction expression for hc[k − n, [k]] of Bh-bit wide results in a quantization error which can be expressed as k+M X n=k−M qh2[n, [k]] ≈ 2M × 1 122 −2Bh (2.34)
Figure 2.5 shows an example of hc[n, [k]] and qh[n, [k]] plots with Bh=18 and ˆ[k]=0.001. For an ideal B-bit ADC with full-swing sine wave input, Ph,q must smaller than Pq to preserve the resolution, i.e.,
2.5. NON-IDEAL EFFECTS IN JITTER COMPENSATION 21
Figure 2.6: SNR results of jitter compensation of different Bh. Circles are simulations with irrational hc[n, ˆ[k]]= sinc(n − ˆ[k]) .
A2 2 ×2M × 1 122 −2Bh ≤ 1 12 2A 2B 2 (2.35) Thus, Bh ≥ B −1+ 1 2log2(M ) (2.36)
For example, if B=16 and M=16, Bh=17 can be chosen according to Equation (2.36). Figure 2.6 shows the simulated SNR performance of a 16-bit ADC when using Bh = 15, Bh = 16 and Bh = 17 to approximate the irrational tap coefficients hc[n, [k]]. Assume that rms = 0.0003 and the resolution of the JDC is 0.0001. The circles are simulations without quantizing the tap coefficients, i.e., the irrational hc[n, ˆ[k]] = sinc(n − ˆ[k]) are used in the simulations. As predicts by Equation (2.36), the SNR performance after jitter compensation when Bh = 17 are nearly the same with the SNR performance when
Ts k Ts Ts Vi Ts Ts Vi ε k − ( ε[k]) ( k + ε[k]) B Magnitude (k+1) (k−1) B’ (t) D [k]u (t) u t A A’
Figure 2.7: A graphic illustration of simplified jitter compensation principle.
Bh >17.
Note that Equation (2.36) is overestimated for large M. As M increases, hc[M, [k]]= sinc(M − [k]) will convergence to zero eventually, so does qh[M, [k]].
2.6
Simplified Jitter Compensation Filter
In Figure 2.4, the tap coefficients, hc[n, [k]], are recalculated every clock cycle due to the different ˆ[k] at different k. The hardware cost of this time-variant JCF is very high. It is also difficult for this JCF to achieve high-speed operation. A simplified JCF is proposed to reduce the difficulty when implementing the JCF.
As shown in Figure 2.7, if a sampling error occurs at the k-th sampling instant, the Vi(t) is sampled at t= (k + [k])Tsinstead of t = kTs. The magnitude at point A’ is quan-tized as Di[k]. Thus, the ADC perceives a different ˆVi(t) input instead of Vi(t). The signal
ˆ
Vi(t) has a value of Di[k] at t = kTs, denoted as point B. The filter of Equation (2.15) interpolates the value of ˆVi(t) at t = (k − [k])Ts, denoted as point B’, which is a correct estimation of Vi(t) at t= kTs. If [k] 1, the curve between point B to point B’ is nearly a straight line. Thus, if the clock jitter is u and using Equation (2.16) to compensate the sampling error, the magnitude required to be compensated is defined as Du[k] and
2.6. SIMPLIFIED JITTER COMPENSATION FILTER 23 D i D i 1 z 1 z D i D i 1 z D i 1 z [k+M] D i D i [k] D c [k] D i [k] [k] D u [k+M−1] [k+1] [k−1] [k−M+1] [k−M]
ε
[k] h [−M] h [−M+1] h [−1] h [1] h [M] h [M−1]ε
s s s s s s u Figure 2.8: A simplified jitter compensation filter with 2 M + 1 taps.Du[k]= Dc[k] − Di[k] = k−1 X n=k−M Di[n] × hc[k − n, ˆ[k]]+ k+M X n=k+1 Di[n] × hc[k − n, ˆ[k]] (2.37)
and the slope of the straight line between point B to point B’ is
Ds[k]= Du[k]
u
(2.38) Therefore, the magnitude required to be compensated is simply this slope at the k-th sample, multiplied by the k-th sampling jitter, ˆ[k]. As a consequence, Equation (2.16) can be approximated by Dc[k] ≈ Di[k]+ ˆ[k] × Du[k] u = Di[k]+ ˆ[k] u × ( k−1 X n=k−M Di[n] × hc[k − n, u] + k+M X n=k+1 Di[n] × hc[k − n, u] ) (2.39)
We can define a simplified JCF with the filter coefficients as
hs[n]= hc[n, u]= sinc(n − u) (2.40) Thus, Du[k] becomes Du[k]= k−1 X n=k−M Di[n] × hs[k − n] + k+M X n=k+1 Di[n] × hs[k − n] (2.41)
and the output of the simplified JCF is
Dc[k] ≈ Di[k]+ ˆ[k]
u
× Du[k] (2.42)
In the above equations, uis a predefined jitter constant. The value of uis not crucial. It can be chosen so that uapproximates to the standard deviation of [k].
2.6. SIMPLIFIED JITTER COMPENSATION FILTER 25
Figure 2.8 shows the resulting JCF. In this implementation, once a specific u is cho-sen, the hs[n] tap coefficients are fixed. The Du[k] signal of Equation (2.41) is calculated using a time-invariant FIR filter with the fixed hs[n] tap coefficients. The sampling error is estimated by multiplying Du[k] with the ˆ[k]/uratio. In Figure 2.8, ˆ[k] is only used at one place. Note that the division is not needed here because the results of the TDC calibration are in the form of divided by ualready. The TDC background calibration will be introduced in Chapter 4 and Chapter 5.
As derived in Section 2.4, for an ideal JCF without JDC measurement error, the output of the JCF becomes Dc[k] = Vi(kTs) which is a correct sample without sampling error. Therefore, the sampling error can be derived from Equation (2.16)
Ve[k] = Dc[k] − Di[k]= k−1 X n=k−M Di[n] × hc[k − n, [k]] + k+M X n=k+1 Di[n] × hc[k − n, [k]] (2.43)
From Equation (2.41) and Equation (2.42), the sampling error calculated by the sim-plified JCF can be expressed as
Ve,s[k]= k−1 X n=k−M Di[n] × hs[k − n] × [k] u[k] + k+M X n=k+1 Di[n] × hs[k − n] × [k] u[k] (2.44)
In order to decide the value of u, we defined Eswhich is the difference between hs[n] and hc[n],
Eh[n, [k]] ≡ hc[k − n, [k]] − hs[k − n] × [k] u[k]
(2.45) The residual sampling error caused by the simplified JCF, defined as Ve,r[k] ≡ Ve[k] − Ve,s[k], can be derived from Equation (2.43) and Equation (2.44),
Ve,r[k]= k−1 X n=k−M Di[n] × Eh[n, [k]]+ k+M X n=k+1 Di[n] × Eh[n, [k]] (2.46)
(a)
(b)
Figure 2.9: Pe,r normalized to the quantization noise Pq Plots. (a) rms= 3 × 10−4and (b) rms = 15 × 10−4.
2.6. SIMPLIFIED JITTER COMPENSATION FILTER 27
As an example, consider a sine wave input Vi(t) expressed as
Vi(t)= Ai×sin(ωit+ φi) (2.47)
Using Equation (2.46) and Eh[n, [k]] ≈ Eh[−n, [k]], we have
Ve,r[k]= Aisin(ωikTs+ φi) × (M X n=1 2 cos(nωiTs) × Eh[n, [k]] ) (2.48)
Thus, the error power of the Ve,r[k] sequence is
Pe,r ≡ (Ve,r[k])2= 2A2i × (M X n=1 cos(nωiTs) × Eh[n, [k]] )2 (2.49)
In order to calculate the power of the Ve,r[k] sequence, the distribution of the clock jitter [k] must be considered. Assume that the clock jitter [k] is normal-distributed with zero mean and the standard deviation is rms. Figure 2.9 shows the Pe,r normalized to the quantization noise Pqof a 16-bit ADC. The value of Euis not crucial. For Eu <32×10−14, the Pe,r is smaller than the quantization noise even when the clock jitter rms= 15 × 10−4. rms = 15 × 10−4 is equivalent to ∆tms = 18.75 ps at 80 MHz sampling rate, which is an extremely large value of jitter.
The simplified JCF can be interpreted in a more intuitively way. The Taylor series of the input signal expanded at t= x can be expressed as
Vin(t)= V (x) + V0(x) 1! (t − x)+ V00(x) 2! (t − x) 2+ V 000 (x) 3! (t − x) 3+ . . . (2.50)
At the k-th sample, the nominal smaling time is t = kTs. The jitter at the k-th sample is ∆t[k] = [k] × Ts. Therefore, the Taylor series expansion of the input signal at t = kTs+ [k] × Ts can be obtained by substituting x= (kTs+ ∆t[k]) in Equation (2.50), i.e.,
Vin(t) = V (kTs+ ∆t[k]) + V0(kTs+ ∆t[k]) 1! t − kTs+ ∆t[k] + V00(kTs+ ∆t[k]) 2! t − kTs+ ∆t[k] 2 + V000(kTs+ ∆t[k]) 3! t − kTs+ ∆t[k] 3 + . . . (2.51)
The correct sample ,Vin(kTs), can be obtained by substituting t= kTsinto Equation (2.51),
Vin(kTs)= V (kTs+ ∆t[k]) + V0(kTs+ ∆t[k]) 1! − ∆t[k] + V00(kTs+ ∆t[k]) 2! − ∆t[k] 2 + V000(kTs+ ∆t[k]) 3! − ∆t[k] 3 + . . . = Vc[k] (2.52)
With the information of clock jitter∆t[k], the input signal Vin(t) and its n-th derivative at t = kTs + ∆t[k], the correct sample can be obtained at incorrect sampling time by Equation (2.51). Comparing Equation (2.42) with Equation (2.52), the simplified JCF is the first order Taylor series approximation of jitter correction. and −Du[k]/u is the first order derivative of Vin(t) at t= kTs+ ∆t[k].
As derived from Section 2.5.2, a 17-bit wide binary fraction expression for hc[k − n, [k]] is required for a 16-bit ADC system. Therefore, 2M multipliers with 17-bit × 16-bit is required in a JCF, which results in an area-hunger digital circuit. However, the multipliers can be replaced with a few adders for the simplified JCF since the coefficients are time-invariant. Table 2.1 shows the binary sign-magnitude expression of the filter coefficients, hs[n], for a JCF with 15 filter taps. u = 0.0002 is chosen and 20 bit is used to approximate the irrational number. The number of the adders is proportional to the number of bits with a digital output 1 in the binary expression of the filter coefficients. For example, hs[1] = 0.00000000000011010001, only 4 adders are required to calculate Di[k − 1] × hs[1]. Thus, The area of the simplified JCF is decreased dramatically.
2.7. A 16-BIT 80 MS/S ADC DESIGN EXAMPLE 29
Table 2.1: Sign-magnitude expression of hs[n] hs[n]
Decimal Fraction Binary Fraction
n Sign Magnitude -7 -0.000028570610 1 0.00000000000000011101 -6 0.000033332220 0 0.00000000000000100010 -5 -0.000039998397 1 0.00000000000000101001 -4 0.000049997497 0 0.00000000000000110100 -3 -0.000066662218 1 0.00000000000001000101 -2 0.000099989994 0 0.00000000000001101000 -1 -0.000199959995 1 0.00000000000011010001 1 0.000200039995 0 0.00000000000011010001 2 -0.000100009994 1 0.00000000000001101000 3 0.0000666711073 0 0.00000000000001000101 4 -0.000050002497 1 0.00000000000000110100 5 0.000040001597 0 0.00000000000000101001 6 -0.000033334442 1 0.00000000000000100010 7 0.000028572243 0 0.00000000000000011101
2.7
A 16-bit 80 MS/s ADC Design Example
A 16-bit ADC system operating at a sampling rate of 80 MS/s was simulated by using a C program to verify the proposed jitter compensation techniques. Its sampling period is Ts = 12.5 ns. Assume that the rms of the clock jitter is ∆trms = rmsTs = 3.75 ps, i.e., rms = 3 × 10−4. From Equation (2.5), Equation (2.7), and Equation (2.24), to ensure better than 80 dB SNR for an input frequency up to 32 MHz, i.e., Ωi < (4/5)π, one can choose e,rmsTs < 1.25/
√
12 ps and M = 7. The e,rms indicates the required resolution and accuracy for the JDC. To simplify the simulations, the JDC is an ideal one with a uniform quantization step size of 1.25 ps, so that e,rmsTs = 1.25/
√
12 ps. The number of taps for the JCF is 2M+ 1 = 15. The bandwidth limitation is due to the proposed JDC calibration, which will be discussed in Chapter 4 and Chapter 5.
Figure 2.10 shows the simulated ADC output spectrum before and after the jitter com-pensation for the system in Figure 2.2 and M = 7 is chosen. The JCF is the one shown in Figure 2.8, i.e., a simplified JCF is adopted in simulations. The input is a sine wave signal with frequency of 26 MHz. As the figure reveals, the noise floor is decreased by about
20 dB after the jitter compensation. In other words, the jitter compensation can improve the SNR by 20 dB.
Figure 2.11 shows the simulated ADC output spectrum before and after the jitter com-pensation when the input is a wide-band signal. In this simulation, the input is composed of four sine wave signals with different frequencies and phases. The jitter compensation for this multi-tone test can improve the ADC SNR from 65.46 dB to 83.55 dB.
Figure 2.12 shows the SNR performance from simulations of the system in Figure 2.2 for different input frequencies. The circle symbols in Figure 2.12 are simulation results. Also shown as the solid line in the figure are the calculated SNR of a JCF with M = 7 using Equation (2.5), Equation (2.7), and Equation (2.24). Perfect match between the simulated results and the calculated results can be observed in the figure. The dashed line shown in Figure 2.12 is the SNR of an ideal JCF calculated using Equation (2.25). This dashed line is the limitation of the jitter compensation for a given JDC’s resolution, which is assumed to be 1.25 ps in simulation. At fi/fs = 0.4, i.e., Ωi = (4/5)π, the JCF can improve the SNR by 20 dB at input frequency close to 0.4fs. As a reference, the uncompensated SNR in Figure 2.12 is calculated using Equation (2.10).
As the number of taps of the JCF increased, the SNR after jitter compensation will approach to the ideal performance gradually as predict by Equation (2.25). Figure 2.13 shows the SNR performance when M = 31 is chosen. The circle symbols in Figure 2.13 are simulation results. The solid line is the calculated SNR of a JCF with M = 31 using Equation (2.5), Equation (2.7), and Equation (2.24). Perfect match between the simulated results and the calculated results still can be observed in the figure. The compensated SNR for a JCF with M = 31 is almost the same with the SNR calculated using Equation (2.25).
2.8
Summary
A digital jitter compensation for ADCs is presented in this chapter. If the jitter of the sampling clock is measured, the jitter compensation technique can correct the sampling error caused by the clock jitter, thus allowing the use of a cheaper clock source. Most of the compensation overhead is the digital circuitry; therefore both the circuit area and the power consumption are scaled along with the technology scaling. Since the jitter
2.8. SUMMARY 31
compensation is performed in the digital domain and no feedback signal is required for the ADC, the jitter compensation circuit and the ADC can be connected in parallel. No modification is required for the ADC.
The SNR improvement of the proposed jitter compensation technique is determined by the resolution of the JDC, the number of taps for the JCF and the rms of input clock jitter. Theoretical analyses and System simulations are both provided to verify the proposed jitter compensation technique in this chapter.
Figure 2.10: The ADC output power spectrum before and after the jitter compensation for M = 7.
2.8. SUMMARY 33
Figure 2.11: The ADC output power spectrum before and after the jitter compensation for M = 7.
Figure 2.12: SNR results of jitter compensation for M = 7. Circles are from simulations. Lines are from calculations. fi = ωi/(2π) is the input frequency, and fs = 1/Ts is the sampling rate.
2.8. SUMMARY 35
Figure 2.13: SNR results of jitter compensation for M = 31. Circles are from simulations. Lines are from calculations
Chapter 3
Time-to-Digital Converter
3.1
Introduction
The proposed jitter compensation scheme requires a timing measurement circuit to per-form the jitter-to-digital conversion so that the sampling error introduced by the clock jitter can be compensated in the digital domain. The JDC in Figure 2.2 contains a time-to-digital converter (TDC) that digitizes the timing (or phase) difference between two clocks of identical frequency. As shown in Figure 3.1, a TDC is used to compare the rising edges of two clocks V1 and V2. For a 16-bit 80 MS/s ADC system, the TDC must perform the
conversion every clock cycle and have a resolution better than 1 ps.
In order to quantized the timing information into the digital code, several time-to-digital conversion circuits had been demonstrated previously in literature. An up-to-date survey can be found in [30]. Most of them require certain types of precision circuits, such as delay elements with precise delay [31, 32], oscillators with precise frequency [33], or time-to-voltage converters with precise conversion function [34, 35]. In this chapter, we will discuss various types of TDC and their limitations.
3.2
Counter-Based TDC
The most direct method for measuring a time interval is to use a counter. As shown in Figure 3.2, the counter is triggered at the raising edge of V1 signal and stopped at the
td 1
V
V 2
Figure 3.1: Timing difference measured by a TDC.
raising edge of V2signal. Therefore, the timing interval to be measured is proportional to
the resulting count,
td ≈ N × Tc (3.1)
where Tc is the clock period of the counter and N is the resulting count which is 6 in Figure 3.2.
The resolution of such TDC is limited by the period of the counter clock. Like the quantization noise in an ADC, the root-mean-squared value (rms) of the quantization step for the counter based TDC can be derived as [36]
∆tq,rms= πTc
8 (3.2)
The accuracy of counter based measurements can be improved by taking a series of measurements of the same interval td, and averaging the results [37]. Therefore, this technique is often used for frequency measurement since several periods can be measured and a better resolution can be obtained by average. For example, if M successive periods are measured for a periodic signal with frequency of fs, i.e. td = M × (1/fs) ≈ N × Tc. Thus, the frequency under measured is
fs = M N × Tc
3.3. TIME-TO-AMPLITUDE METHOD 39
V 2
td
Tc
1
V
Trigger
Stop
Figure 3.2: A counter-based TDC timing diagram of conversion.
This technique is unsuitable for measuring aperiodic signals with short time intervals in the order of picoseconds, such as the clock jitter.
3.3
Time-to-Amplitude Method
Another commonly used method is based on time-to-amplitude conversion [38, 39, 40]. As shown in Figure 3.3, a capacitor is first charged or discharged by a fixed current for the time interval to be measured, then an ADC is used to digitize the voltage on the capacitor. The capacitor voltage is reset to zero between measurements. The voltage on the capacitor after it stops charging is
Vc= Ic
C × td (3.4)
For a short td, a high resolution ADC is required to digitize the voltage on the capacitor and is difficult to implement. To simplify the design, a dual-slope ADC is often used together with the time-to-amplitude method. The dual-slope technique first charged a capacitor with fixed current, Ic, for the time interval to be measured then a smaller current,
ADC t d Digital Output I c t d Vc Reset C
A/D Conversion Time Resert
VDD
Figure 3.3: A time-to-amplitude TDC timing diagram of conversion.
Id, is used to discharge the capacitor to zero. As shown in Figure 3.4, the relation between the time interval to be measured, td, and the time interval for discharging the capacitor to zero, tm, is
td = Id Ic
× tm (3.5)
If Ic = 100Id, tm is equal to 100 × td. Thus, we can measure tm instead of td to obtain a better resolution. However, if tdis small, the switching noise such as clock feed through and charge injection will dominant the resolution.
3.4
Tapped Delay Line TDC
In a tapped delay line TDC as shown in Figure 3.5a, V1signal is passing through a delay
line and each delay buffer produces a delay equal to τ1. The output of each delay buffer
is connected to the data input of a flip-flop. All the flip-flops are triggered at the raising edge of V2 signal and the TDC’s output m is generated by summing the digital outputs
from all flip-flops. Like a flash ADC, the adder can be replaced by an edge detector to perform the thermometer code to binary code conversion. As shown in Figure 3.5b, the timing interval to be measures is
3.4. TAPPED DELAY LINE TDC 41
t
d
c
V
t
tm
Figure 3.4: A dual-slope TDC timing diagram of conversion.
and m is equal to 4 in Figure 3.5b. To ensure that τ1is known accurately, the delay chain is
often controlled by a delay-locked loop (DLL) [31, 41, 42] or a phase-locked loop (PLL) [33, 43].
The resolution of the tapped delay line TDC is determined by the delay of the delay element τ1, which is limited to a gate delay. To provide a finer resolution, a vernier tapped
delay line technique is used [31, 43, 44]. In the vernier tapped delay line technique, one tapped delay line drives the flip-flop clock inputs, while the other tapped delay line drives the flip-flop data inputs as shown in Figure 3.6a. The clock tap delay is slightly longer (or shorter) than the data tap delay. The vernier-based TDC is equivalent to a delay line TDC shown in Figure 3.6b, the effective tap delay is then the difference between the clock and data tap delays, i.e.
td ≈ m ×(τ1− τ2) (3.7)
Therefore, resolutions better than a gate delay can be achieved.
The resolution is sensitive to the gate delays, thus timing calibration of the delay chain is necessary [44, 45, 46, 47]. Even with appropriate calibration, this method still suffered from the noise induced by the delay line itself, and the error is accumulated along the delay line.
Q 1 Q2 Q3 Flip−Flop D Q Q L−1 QL V 1 V 2 τ1 τ1 τ1 m Flip−Flop D Q Flip−Flop Flip−Flop D Q D Q (a) V 1 td V 2 3 4 5 1 2 L Q = 1 Q = 1 Q = 1 Q = 1 Q = 0 Q = 0 m=4
τ
1 1 1 1 1 0 0 (b)Figure 3.5: (a) TDC utilizing a tapped line. (b) Timing diagram of a tapped delay-line TDC.
3.4. TAPPED DELAY LINE TDC 43 Q 1 Q2 Q3 Flip−Flop D Q Q L−1 QL V 1 V 2 τ1 τ1 τ1 τ2 τ2 τ2 m Flip−Flop D Q Flip−Flop Flip−Flop D Q D Q (a) Q 1 Q2 Q3 Flip−Flop D Q Q L−1 QL V 1 V 2 τ1 τ2 ∆τ = m Flip−Flop D Q Flip−Flop Flip−Flop D Q D Q ∆τ ∆τ ∆τ (b)
Figure 3.6: (a) A vernier delay-line TDC. (b) An equivalent circuit model of a vernier delay-line TDC containing a single delay line, and ∆τ = τ1− τ2.
3.5
Stochastic TDC
The TDC used in our design is based on the stochastic TDC architecture [28, 48]. It does not use any precision circuit, and can be easily realized in a standard CMOS VLSI technology.
To understand the stochastic TDC in an easy way, Figure 3.7 shows the relationship between a stochastic TDC and a delay-line TDC. Each delay cell in the delay-line is replaced by a timing offset tosn. The timing offset originates from the mismatch of the flip-flop itself. Thus, a stochastic TDC conducts the time-to-digital conversion by exploring the statistics of a group of flip-flops or timing comparators (TCMPs). Like a flash ADC, it can easily complete the conversion in one clock cycle. It can provide the conversion for every clock cycle continuously. Furthermore, it can improve the conversion resolution simply by adding more TCMPs. Figure 3.8 shows a TCMP example [28]. It compares the rising edges of two clocks, V1 and V2. Ideally, its output is a digital 1 if the timing
difference td > 0. If td < 0, the output is a digital 0. However, a practical TCMP exhibits an offset, tos. The offset is mainly caused by devices mismatches and interconnect mismatches. The TCMP now yields an output of digital 1 only if td > tos; otherwise, the output is a digital 0.
Figure 3.9 shows the architecture of a stochastic TDC. It contains L TCMPs. Each TCMP detects the polarity of (td − tos) and has its own tosoffset. For every clock cycle, the TDC’s output, m, is generated by summing the digital outputs from all TCMPs. Thus, mis the number of TCMPs with a digital 1 output. Figure 3.10 illustrates the probability density function (pdf) of tosof a TCMP and the TDC transfer function. From the central limit theorem, the pdf of tosis approximately a normal distribution, G(tos), which is
G(tos)= 1 σ√2πe
−t2os/(2σ2) (3.8)
where σ is the standard deviation of tos. The averaged td-to-m TDC transfer function can be obtained by integrating over this pdf, i.e.,
m= L × Ztd
−∞
3.5. STOCHASTIC TDC 45 Q 1 Q2 Q3 QL−1 QL V 2 τ1 2 3τ1 Lτ1 V 1 τ1 m Flip−Flop D Q Flip−Flop Flip−Flop D Q D Q Flip−Flop D Q (a) Q 1 Q2 Q3 QL−1 QL V 2 osL t V 1 m Flip−Flop D Q Flip−Flop Flip−Flop D Q D Q Flip−Flop D Q tos1 tos2 tos3
(b)
Figure 3.7: Relationship between a delay line TDC and a stochastic TDC. (a) Alternative representation of delay line TDC. (b) A stochastic TDC by utilizing the offset.
![Figure 2.5: h c [n, ˆ[k]] and q h [n, ˆ] plots example when ˆ =0.001 and the filter coefficients are represented by binary fraction of 18-bit wide.](https://thumb-ap.123doks.com/thumbv2/9libinfo/8472276.183584/39.893.129.767.184.690/figure-plots-example-filter-coefficients-represented-binary-fraction.webp)
![Figure 2.6: SNR results of jitter compensation of di fferent B h . Circles are simulations with irrational h c [n, ˆ[k]] = sinc(n − ˆ[k]) .](https://thumb-ap.123doks.com/thumbv2/9libinfo/8472276.183584/40.893.122.772.185.928/figure-results-jitter-compensation-fferent-circles-simulations-irrational.webp)
![Figure 2.8 shows the resulting JCF. In this implementation, once a specific u is cho- cho-sen, the h s [n] tap coe fficients are fixed](https://thumb-ap.123doks.com/thumbv2/9libinfo/8472276.183584/44.893.130.770.504.845/figure-shows-resulting-jcf-implementation-specific-fficients-fixed.webp)
