Conclusions and Future Works
6.2 Recommendations for Future Investigation
This section presents several suggestions for future investigations in jitter compensation for an ADC.
• The background TDC calibration techniques proposed in this thesis need long cali-bration time to converge. TDC calicali-bration with fewer samples is necessary to make this technique more feasible in industry application.
• The measured SNR performance of the implemented jitter compensation technique in Chapter 4 is better than the performance of the jitter compensation technique in Chapter 5. It stems from the jitter accumulation when calculating the absolute jitter from cycle-to-cycle jitter, thus the jitter induced by the delay line is also accumu-lated. Minimize the delay provided by the internal delay line can mitigate this jitter accumulation effect, thus further improving the SNR performance.
• As mention above that the jitter compensation scheme with clean external clock can achieve better SNR performance since there is no jitter accumulation phenomenon.
Therefore, this technique is especially suitable for time-interleaved ADCs with mul-tiphase clock generator for several reasons.
– Time-interleaved ADC is used to multiply the sampling rate, increasing the analog input bandwidth. As the input bandwidth increased, the jitter require-ment is also increased.
– The multiphase clocks are usually generated by a PLL or a DLL. The use of PLL or DLL will induce additional clock jitter inevitable even when the reference clock is clean.
– If the reference clock is clean, the absolute jitter can be measured directly.
Jitter compensation technique in Chapter 4 can be used to obtain a better SNR improvement. There is no jitter accumulation effect mentioned in Chapter 5 if absolute jitter is measured.
Appendix A
In this appendix, we derive the equation
M→∞lim Fc(M, Ω)= −Ω
Considering the Maclaurin Series expansion for − ln(l+ x)
−ln(1+ x) = −x + x2
Comparing (A.2) and (A.3), we can find
M→∞lim
r = 2 + 2 cos(Ω) φ= tan−1 sin Ω
1+ cos Ω = Ω 2
(A.6)
Therefore, (A.4) can be rewriten as
M→∞lim
M
X
n=1
Fc(M, Ω)= −φ = −Ω
2 (A.7)
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F
Chi-Wei Fan was born in Hsin-Chu, Taiwan, R.O.C.. He received the B.S degree in electrical engineering from the National Central University, Chung Li, Taiwan, in 2000. From 2001 to 2010, he worked toward the Ph.D. degree in electronics engineer-ing with the National Chiao-Tung University, Hsinchu. His research interests in mixed-signal, high speed and high resolution integrated circuits design in data communication.
In 2010, he joined the MediaTek where he was engaged in the design of analog and mixed-signal ICs.
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115
• Journal Paper:
– C.-W. Fanand J.-T. Wu, “Jitter Measurement and Compensation for Analog-to-Digital Converters,” IEEE Transactions on Instrumentation and Measure-ment, vol. 58, no. 11, pp. 3874–3884, November 2009.
• Conference Paper:
– C.-W. Fanand J.-T. Wu, “ADC Clock Jitter Measurement and Correction Us-ing a Stochastic TDC,” accepted by 2010 IEEE Asia Pacific Conference on Circuits and Systems Program Committee.
– W.-H. Tseng, C.-W. Fan and J.-T. Wu, “A 12-Bit 1.25-GS/s DAC in 90nm CMOS with > 70dB SFDR up to 500MHz,” submitted to 2011 IEEE Interna-tional Solid-State Circuits Conference.