77
CHAPTER 3
MOV AX,BX
Destination Source FIGURE 3–1 The MOV
instruction showing the source, destination, and direction of data flow.
1The exceptions are the CMP and TEST instructions, which never change the destination. These instructions are described in later chapters.
3–1 DATA-ADDRESSING MODES
Because the MOV instruction is a very common and flexible instruction, it provides a basis for the explanation of the data-addressing modes. Figure 3–1 illustrates the MOV instruction and defines the direction of data flow. The source is to the right and the destination is to the left, next to the opcode MOV. (An opcode, or operation code, tells the microprocessor which operation to perform.) This direction of flow, which is applied to all instructions, is awkward at first. We nat-urally assume that things move from left to right, whereas here they move from right to left.
Notice that a comma always separates the destination from the source in an instruction. Also, note that memory-to-memory transfers are not allowed by any instruction except for the MOVS instruction.
In Figure 3–1, the MOV AX, BX instruction transfers the word contents of the source reg-ister (BX) into the destination regreg-ister (AX). The source never changes, but the destination always changes.1It is crucial to remember that a MOV instruction always copies the source data into the destination. The MOV never actually picks up the data and moves it. Also, note the flag register remains unaffected by most data transfer instructions. The source and destination are often called operands.
Figure 3–2 shows all possible variations of the data-addressing modes using the MOV instruction. This illustration helps to show how each data-addressing mode is formulated with the MOV instruction and also serves as a reference on data-addressing modes. Note that these are the same data-addressing modes found with all versions of the Intel microprocessor, except for the scaled-index-addressing mode, which is found only in the 80386 through the Core2. The RIP relative addressing mode is not illustrated and is only available on the Pentium 4 and the Core2 when operated in the 64-bit mode. The data-addressing modes are as follows:
Register Register addressing transfers a copy of a byte or word from the source addressing register or contents of a memory location to the destination register or
memory location. (Example: The MOV CX, DX instruction copies the word-sized contents of register DX into register CX.) In the 80386 and above, a doubleword can be transferred from the source register or memory location to the destination register or memory location.
(Example: The MOV ECX, EDX instruction copies the doubleword-sized contents of register EDX into register ECX.) In the Pentium 4 operated in the 64-bit mode, any 64-bit register is also allowed. An example is the MOV RDX, RCX instruction that transfers a copy of the quadword contents of register RCX into register RDX.
Immediate Immediate addressing transfers the source, an immediate byte, word, addressing doubleword, or quadword of data, into the destination register or
memory location. (Example: The MOV AL, 22H instruction copies a byte-sized 22H into register AL.) In the 80386 and above, a
doubleword of immediate data can be transferred into a register or
79 10000H + 1000H + 0300H + 0200H Memory
address 10304H
Base relative-plus-index MOV ARRAY[BX+SI],DX
DS× 10H + EBX + 2 × ESI
Notes: EBX = 00000300H, ESI = 00000200H, ARRAY = 1000H, and DS = 1000H MOV [EBX+2 × ESI],AX
memory location. (Example: The MOV EBX, 12345678H instruction copies a doubleword-sized l2345678H into the 32-bit-wide EBX register.) In 64-bit operation of the Pentium 4 or Core2, only a MOV immediate instruction allows access to any location in the memory using a 64-bit linear address.
Direct Direct addressing moves a byte or word between a memory location addressing and a register. The instruction set does not support a
memory-to-memory transfer, except with the MOVS instruction. (Example: The MOV CX, LIST instruction copies the word-sized contents of memory location LIST into register CX.) In the 80386 and above, a doubleword-sized memory location can also be addressed. (Example:
The MOV ESI, LIST instruction copies a 32-bit number, stored in four consecutive bytes of memory, from location LIST into register ESI.) The direct memory instructions in the 64-bit mode use a full 64-bit linear address.
Register indirect Register indirect addressing transfers a byte or word between a addressing register and a memory location addressed by an index or base register.
The index and base registers are BP, BX, DI, and S1. (Example: The MOV AX, [BX] instruction copies the word-sized data from the data segment offset address indexed by BX into register AX.) In the 80386 and above, a byte, word, or doubleword is transferred between a register and a memory location addressed by any register: EAX, EBX, ECX, EDX, EBP, EDI, or ESI. (Example: The MOV AL, [ECX]
instruction loads AL from the data segment offset address selected by the contents of ECX.) In 64-bit mode, the indirect address remains 32 bits in size, which means this form of addressing at present only allows access to 4G bytes of address space if the program operates in the 32-bit compatible mode. In the full 64-32-bit mode, any address is accessed using either a 64-bit address or the address contained in a register.
Base-plus-index Base-plus-index addressing transfers a byte or word between a addressing register and the memory location addressed by a base register (BP or
BX) plus an index register (DI or SI). (Example: The MOV [ ], CL instruction copies the byte-sized contents of register CL into the data segment memory location addressed by BX plus DI.) In the 80386 and above, any two registers (EAX, EBX, ECX, EDX, EBP, EDI, or ESI) may be combined to generate the memory address.
(Example: The MOV [ ], CL instruction copies the byte-sized contents of register CL into the data segment memory location addressed by EAX plus EBX.)
Register relative Register relative addressing moves a byte or word between a register addressing and the memory location addressed by an index or base register plus a
displacement. (Example: MOV AX,[ ] or MOV AX,ARRAY[BX].
The first instruction loads AX from the data segment address formed by BX plus 4. The second instruction loads AX from the data segment memory location in ARRAY plus the contents of BX.) The 80386 and above use any 32-bit register except ESP to address memory. (Example:
MOV AX,[ ] or MOV AX,ARRAY[EBX]. The first instruction loads AX from the data segment address formed by ECX plus 4. The second instruction loads AX from the data segment memory location ARRAY plus the contents of EBX.)
ECX + 4
BX + 4 EAX + EBX
BX + DI
Base relative-plus- Base relative-plus-index addressing transfers a byte or word between a index addressing register and the memory location addressed by a base and an index
register plus a displacement. (Example: MOV AX, ARRAY[ ] or MOV AX, [ ]. These instructions load AX from a data segment memory location. The first instruction uses an address formed by adding ARRAY, BX, and DI and the second by adding BX, DI, and 4.) In the 80386 and above, MOV EAX, ARRAY[ ] loads EAX from the data segment memory location accessed by the sum of ARRAY, EBX, and ECX.
Scaled-index Scaled-index addressing is available only in the 80386 through the addressing Pentium 4 microprocessor. The second register of a pair of registers is
modified by the scale factor of to generate the operand memory address. (Example: A MOV EDX, [ ] instruction loads EDX from the data segment memory location addressed by EAX plus four times EBX.) Scaling allows access to word ( ), doubleword ( ), or quadword ( ) memory array data. Note that a scaling factor of also exists, but it is normally implied and does not appear explicitly in the instruction. The MOV AL, [ ] is an example in which the scaling factor is a one. Alternately, the instruction can be rewritten as MOV AL, [ ]. Another example is a MOV AL, [ ] instruction, which uses only one scaled register to address memory.
RIP relative This addressing mode is only available to the 64-bit extensions on the addressing Pentium 4 or Core2. This mode allows access to any location in the
memory system by adding a 32-bit displacement to the 64-bit contents of the 64-bit instruction pointer. For example, if
and a 32-bit displacement is 300H, the location accessed is 1000000300H.
The displacement is signed so data located within from the instruction is accessible by this addressing mode.