Addition
Addition (ADD) appears in many forms in the microprocessor. This section details the use of the ADD instruction for 8-, 16-, and 32-bit binary addition. A second form of addition, called add-with-carry, is introduced with the ADC instruction. Finally, the increment instruction (INC) is presented. Increment is a special type of addition that adds 1 to a number. In Section 5–3, other forms of addition are examined, such as BCD and ASCII. Also described is the XADD instruction, found in the 80486 through the Pentium 4.
Table 5–1 illustrates the addressing modes available to the ADD instruction. (These addressing modes include almost all those mentioned in Chapter 3.) However, because there are more than 32,000 variations of the ADD instruction in the instruction set, it is impossible to list them all in this table. The only types of addition not allowed are memory-to-memory and seg-ment register. The segseg-ment registers can only be moved, pushed, or popped. Note that, as with all other instructions, the 32-bit registers are available only with the 80386 through the Core2. In the 64-bit mode of the Pentium 4 and Core2, the 64-bit registers are also used for addition.
TABLE 5–1 Example addition instructions.
Assembly Language Operation
ADD AL,BL AL = AL + BL
ADD CX,DI CX = CX + DI
ADD EBP,EAX EBP = EBP + EAX
ADD CL,44H CL = CL + 44H
ADD BX,245FH BX = BX + 245FH ADD EDX,12345H EDX = EDX + 12345H
ADD [BX],AL AL adds to the byte contents of the data segment memory location addressed by BX with the sum stored in the same memory location ADD CL,[BP] The byte contents of the stack segment memory location addressed
by BP add to CL with the sum stored in CL
ADD AL,[EBX] The byte contents of the data segment memory location addressed by EBX add to AL with the sum stored in AL
ADD BX,[SI+2] The word contents of the data segment memory location addressed by SI + 2 add to BX with the sum stored in BX
ADD CL,TEMP The byte contents of data segment memory location TEMP add to CL with the sum stored in CL
ADD BX,TEMP[DI] The word contents of the data segment memory location addressed by TEMP + DI add to BX with the sum stored in BX
ADD [BX+D],DL DL adds to the byte contents of the data segment memory location addressed by BX + DI with the sum stored in the same memory location ADD BYTE PTR [DI],3 A 3 adds to the byte contents of the data segment memory location
addressed by DI with the sum stored in the same location
ADD BX,[EAX+2*ECX] The word contents of the data segment memory location addressed by EAX plus 2 times ECX add to BX with the sum stored in BX
ADD RAX,RBX RBX adds to RAX with the sum stored in RAX (64-bit mode)
ADD EDX,[RAX+RCX] The doubleword in EDX is added to the doubleword addressed by the sum of RAX and RCX and the sum is stored in EDX (64-bit mode)
Register Addition. Example 5–1 shows a simple sequence of instructions that uses register addition to add the contents of several registers. In this example, the contents of AX, BX, CX, and DX are added to form a 16-bit result stored in the AX register.
EXAMPLE 5–1
0000 03 C3 ADD AX,BX 0002 03 C1 ADD AX,CX 0004 03 C2 ADD AX,DX
Whenever arithmetic and logic instructions execute, the contents of the flag register change.
Note that the contents of the interrupt, trap, and other flags do not change due to arithmetic and logic instructions. Only the flags located in the rightmost 8 bits of the flag register and the overflow flag change. These rightmost flags denote the result of the arithmetic or a logic operation. Any ADD instruction modifies the contents of the sign, zero, carry, auxiliary carry, parity, and overflow flags. The flag bits never change for most of the data transfer instructions presented in Chapter 4.
Immediate Addition. Immediate addition is employed whenever constant or known data are added. An 8-bit immediate addition appears in Example 5-2. In this example, DL is first loaded with 12H by using an immediate move instruction. Next, 33H is added to the 12H in DL by an immediate addition instruction. After the addition, the sum (45H) moves into register DL and the flags change, as follows:
EXAMPLE 5–2
0000 B2 12 MOV DL,12H 0002 80 C2 33 ADD DL,33H
Memory-to-Register Addition. Suppose that an application requires memory data to be added to the AL register. Example 5–3 shows an example that adds two consecutive bytes of data, stored at the data segment offset locations NUMB and , to the AL register.
EXAMPLE 5–3
0000 BF 0000 R MOV DI,OFFSET NUMB ;address NUMB
0003 B0 00 MOV AL,0 ;clear sum
0005 02 05 ADD AL,[DI] ;add NUMB
0007 02 45 01 ADD AL,[DI+1] ;add NUMB+1
The first instruction loads the destination index register (DI) with offset address NUMB. The DI register, used in this example, addresses data in the data segment beginning at memory location NUMB. After clearing the sum to zero, the ADD AL,[DI] instruction adds the contents of memory location NUMB to AL. Finally, the ADD AL,[ ] instruction adds the contents of memory location NUMB plus 1 byte to the AL register. After both ADD instructions execute, the result appears in the AL register as the sum of the contents of NUMB plus the contents of . Array Addition. Memory arrays are sequential lists of data. Suppose that an array of data (ARRAY) contains 10 bytes, numbered from element 0 through element 9. Example 5–4 shows how to add the contents of array elements 3, 5, and 7 together.
NUMB + 1 DI + I
NUMB + 1 O = 0 1no overflow2
P = 0 1odd parity2 S = 0 1result positive2 A = 0 1no half-carry2 C = 0 1no carry2 Z = 0 1result not zero2
This example first clears AL to 0, so it can be used to accumulate the sum. Next, register SI is loaded with a 3 to initially address array element 3. The ADD AL,ARRAY[SI] instruction adds the contents of array element 3 to the sum in AL. The instructions that follow add array ele-ments 5 and 7 to the sum in AL, using a 3 in SI plus a displacement of 2 to address element 5, and a displacement of 4 to address element 7.
EXAMPLE 5–4
0000 B0 00 MOV AL,0 ;clear sum
0002 BE 0003 MOV SI,3 ;address element 3
0005 02 84 0000 R ADD AL,ARRAY[SI] ;add element 3 0009 02 84 0002 R ADD AL,ARRAY[SI+2] ;add element 5 000D 02 84 0004 R ADD AL,ARRAY[SI+4] ;add element 7
Suppose that an array of data contains 16-bit numbers used to form a 16-bit sum in regis-ter AX. Example 5–5 shows a sequence of instructions written for the 80386 and above, showing the scaled-index form of addressing to add elements 3, 5, and 7 of an area of memory called ARRAY. In this example, EBX is loaded with the address ARRAY, and ECX holds the array ele-ment number. Note how the scaling factor is used to multiply the contents of the ECX register by 2 to address words of data. (Recall that words are 2 bytes long.)
EXAMPLE 5–5
0000 66|BB 00000000 R MOV EBX,OFFSET ARRAY ;address ARRAY
0006 66|B9 00000003 MOV ECX,3 ;address element 3
000C 67&8B 04 4B MOV AX,[EBX+2*ECX] ;get element 3
0010 66|B9 00000005 MOV ECX,5 ;address element 5
0016 67&03 04 4B ADD AX,[EBX+2*ECX] ;add element 5
001A 66|B0 00000007 MOV ECX,7 ;address element 7
0020 67&03 04 4B ADD AX,[EBX+2*ECX] ;add element 7
Increment Addition. Increment addition (INC) adds 1 to a register or a memory location. The INC instruction adds 1 to any register or memory location, except a segment register. Table 5–2 illustrates some of the possible forms of the increment instructions available to the 8086–Core2 processors. As with other instructions presented thus far, it is impossible to show all variations of the INC instruction because of the large number available.
With indirect memory increments, the size of the data must be described by using the BYTE PTR, WORD PTR, DWORD PTR, or QWORD PTR directives. The reason is that the
TABLE 5–2 Example increment instructions.
Assembly Language Operation
INC BL BL = BL + 1
INC SP SP = SP + 1
INC EAX EAX = EAX + 1
INC BYTE PTR[BX] Adds 1 to the byte contents of the data segment memory location addressed by BX
INC WORD PTR[SI] Adds 1 to the word contents of the data segment memory location addressed by SI
INC DWORD PTR[ECX] Adds 1 to the doubleword contents of the data segment memory location addressed by ECX
INC DATA1 Adds 1 to the contents of data segment memory location DATA1 INC RCX Adds 1 to RCX (64-bit mode)
assembler program cannot determine if, for example, the INC [DI] instruction is a byte-, word-, or doubleword-sized increment. The INC BYTE PTR [DI] instruction clearly indicates byte-sized memory data; the INC WORD PTR [DI] instruction unquestionably indicates a word-byte-sized memory data; and the INC DWORD PTR [DI] instruction indicates doubleword-sized data. In 64-bit mode operation of the Pentium 4 and Core2, the INC QWORD PTR [RSI] instruction indicates quadword-sized data.
Example 5–6 shows how to modify Example 5–3 to use the increment instruction for addressing NUMB and . Here, an INC DI instruction changes the contents of register DI from offset address NUMB to offset address . Both program sequences shown in Examples 5–3 and 5–6 add the contents of NUMB and . The difference between them is the way that the address is formed through the contents of the DI register using the increment instruction.
EXAMPLE 5–6
0000 BF 0000 R MOV DI,OFFSET NUMB ;address NUMB
0003 B0 00 MOV AL,0 ;clear sum
0005 02 05 ADD AL,[DI] ;add NUMB
0007 47 INC DI ;increment DI
0008 02 05 ADD AL,[DI] ;add NUMB+1
Increment instructions affect the flag bits, as do most other arithmetic and logic operations.
The difference is that increment instructions do not affect the carry flag bit. Carry doesn’t change because we often use increments in programs that depend upon the contents of the carry flag.
Note that increment is used to point to the next memory element in a byte-sized array of data only. If word-sized data are addressed, it is better to use an ADD DI,2 instruction to modify the DI pointer in place of two INC DI instructions. For doubleword arrays, use the ADD DI,4 instruction to modify the DI pointer. In some cases, the carry flag must be preserved, which may mean that two or four INC instructions might appear in a program to modify a pointer.
Addition-with-Carry. An addition-with-carry instruction (ADC) adds the bit in the carry flag (C) to the operand data. This instruction mainly appears in software that adds numbers that are wider than 16 bits in the 8086–80286 or wider than 32 bits in the 80386–Core2.
Table 5–3 lists several add-with-carry instructions, with comments that explain their operation. Like the ADD instruction, ADC affects the flags after the addition.
NUMB + 1 NUMB + 1 NUMB + 1
TABLE 5–3 Example add-with-carry instructions.
Assembly Language Operation
ADC AL,AH AL = AL + AH + carry ADC CX,BX CX = CX + BX + carry ADC EBX,EDX EBX = EBX + EDX + carry
ADC RBX,0 RBX = RBX + 0 + carry (64-bit mode)
ADC DH,[BX] The byte contents of the data segment memory location addressed by BX add to DH with the sum stored in DH
ADC BX,[BP+2] The word contents of the stack segment memory location addressed by BP plus 2 add to BX with the sum stored in BX
ADC ECX,[EBX] The doubleword contents of the data segment memory location addressed by EBX add to ECX with the sum stored in ECX
Suppose that a program is written for the 8086–80286 to add the 32-bit number in BX and AX to the 32-bit number in DX and CX. Figure 5–1 illustrates this addition so that the placement and function of the carry flag can be understood. This addition cannot be easily performed with-out adding the carry flag bit because the 8086–80286 only adds 8- or 16-bit numbers. Example 5–7 shows how the contents of registers AX and CX add to form the least significant 16 bits of the sum. This addition may or may not generate a carry. A carry appears in the carry flag if the sum is greater than FFFFH. Because it is impossible to predict a carry, the most significant 16 bits of this addition are added with the carry flag using the ADC instruction. The ADC instruction adds the 1 or the 0 in the carry flag to the most significant 16 bits of the result. This program adds BX–AX to DX–CX, with the sum appearing in BX–AX.
EXAMPLE 5–7
0000 03 C1 ADD AX,CX 0002 13 DA ADC BX,DX
Suppose the same software is rewritten for the 80386 through the Core2, but modified to add two 64-bit numbers in the 32-bit mode. The changes required for this operation are the use of the extended registers to hold the data and modifications of the instructions for the 80386 and above. These changes are shown in Example 5–8, which adds two 64-bit numbers. In the 64-bit mode of the Pentium 4 and Core2, this addition is handled with a single ADD instruction if the location of the operands is changed to RAX and RBX as in the instruction ADD RAX,RBX, which adds RBX to RAX.
EXAMPLE 5–8
0000 66|03 C1 ADD EAX,ECX 0003 66|13 DA ADC EBX,EDX
Exchange and Add for the 80486–Core2 Processors. A new type of addition called exchange and add (XADD) appears in the 80486 instruction set and continues through the Core2. The XADD instruction adds the source to the destination and stores the sum in the destination, as with any addition. The difference is that after the addition takes place, the original value of the destina-tion is copied into the source operand. This is one of the few instrucdestina-tions that change the source.
For example, if , and the XADD BL,DL instruction executes, the BL register contains the sum of 14H and DL becomes 12H. The sum of 14H is generated and the original destination of 12H replaces the source. This instruction functions with any register size and any memory operand, just as with the ADD instruction.
BL = 12H and DL = 02H
CF
(ADC) (ADD)
BX AX
DX CX
BX AX
+
FIGURE 5–1 Addition-with-carry showing how the carry flag (C) links the two 16-bit additions into one 32-bit addition.
Subtraction
Many forms of subtraction (SUB) appear in the instruction set. These forms use any addressing mode with 8-, 16-, or 32-bit data. A special form of subtraction (decrement, or DEC) subtracts 1 from any register or memory location. Section 5–3 shows how BCD and ASCII data subtract. As with addition, numbers that are wider than 16 bits or 32 bits must occasionally be subtracted. The subtract-with-borrow instruction (SBB) performs this type of subtraction. In the 80486 through the Core2 processors, the instruction set also includes a compare and exchange instruc-tion. In the 64-bit mode for the Pentium 4 and Core2, a 64-bit subtraction is also available.
Table 5–4 lists some of the many addressing modes allowed with the subtract instruction (SUB). There are well over 1000 possible subtraction instructions, far too many to list here.
About the only types of subtraction not allowed are memory-to-memory and segment register subtractions. Like other arithmetic instructions, the subtract instruction affects the flag bits.
Register Subtraction. Example 5–9 shows a sequence of instructions that perform register sub-traction. This example subtracts the 16-bit contents of registers CX and DX from the contents of register BX. After each subtraction, the microprocessor modifies the contents of the flag register.
The flags change for most arithmetic and logic operations.
EXAMPLE 5–9
0000 2B D9 SUB BX,CX 0002 2B DA SUB BX,DX
Immediate Subtraction. As with addition, the microprocessor also allows immediate operands for the subtraction of constant data. Example 5–10 presents a short sequence of instructions that subtract 44H from 22H. Here, we first load the 22H into CH using an immediate move
TABLE 5–4 Example subtraction instructions.
Assembly Language Operation
SUB CL,BL CL = CL – BL
SUB AX,SP AX = AX – SP
SUB ECX,EBP ECX = ECX – EBP
SUB RDX,R8 RDX = RDX – R8 (64-bit mode)
SUB DH,6FH DH = DH – 6FH
SUB AX,0CCCCH AX = AX – 0CCCCH SUB ESI,2000300H ESI = ESI – 2000300H
SUB [DI],CH Subtracts CH from the byte contents of the data segment memory addressed by DI and stores the difference in the same memory location SUB CH,[BP] Subtracts the byte contents of the stack segment memory location
addressed by BP from CH and stores the difference in CH
SUB AH,TEMP Subtracts the byte contents of memory location TEMP from AH and stores the difference in AH
SUB DI,TEMP[ESI] Subtracts the word contents of the data segment memory location addressed by TEMP plus ESI from DI and stores the difference in DI SUB ECX,DATA1 Subtracts the doubleword contents of memory location DATA1 from
ECX and stores the difference in ECX SUB RCX,16 RCX = RCX – 18 (64-bit mode)
TABLE 5–5 Example decrement instructions.
Assembly Language Operation
DEC BH BH = BH – 1
DEC CX CX = CX – 1
DEC EDX EDX = EDX – 1
DEC R14 R14 = R14 – 1 (64-bit mode)
DEC BYTE PTR[DI] Subtracts 1 from the byte contents of the data segment memory location addressed by DI
DEC WORD PTR[BP] Subtracts 1 from the word contents of the stack segment mem-ory location addressed by BP
DEC DWORD PTR[EBX] Subtracts 1 from the doubleword contents of the data segment memory location addressed by EBX
DEC QWORD PTR[RSI] Subtracts 1 from the quadword contents of the memory location addressed by RSI (64-bit mode)
DEC NUMB Subtracts 1 from the contents of data segment memory location NUMB
instruction. Next, the SUB instruction, using immediate data 44H, subtracts 44H from the 22H.
After the subtraction, the difference (0DEH) moves into the CH register. The flags change as fol-lows for this subtraction:
EXAMPLE 5–10
0000 B5 22 MOV CH,22H 0002 80 ED 44 SUB CH,44H
Both carry flags (C and A) hold borrows after a subtraction instead of carries, as after an addition. Notice in this example that there is no overflow. This example subtracted 44H ( ) from 22H ( ), resulting in a 0DEH ( ). Because the correct 8-bit signed result is , there is no overflow in this example. An 8-bit overflow occurs only if the signed result is greater than
or less than .
Decrement Subtraction. Decrement subtraction (DEC) subtracts 1 from a register or the con-tents of a memory location. Table 5–5 lists some decrement instructions that illustrate register and memory decrements.
The decrement indirect memory data instructions require BYTE PTR, WORD PTR, DWORD PTR, or QWORD PTR because the assembler cannot distinguish a byte from a word or doubleword when an index register addresses memory. For example, DEC [SI] is vague because the assembler cannot determine whether the location addressed by SI is a byte, word, or double-word. Using DEC BYTE PTR[SI], DEC WORD PTR[DI], or DEC DWORD PTR[SI] reveals
–128 +127
–34 –34
+34 +68
O = 0 1no overflow2 P = 1 1even parity2 S = 1 1result negative2 A = 1 1half-borrow2 C = 1 1borrow2 Z = 0 1result not zero2
TABLE 5–6 Example subtraction-with-borrow instructions.
Assembly Language Operation
SBB AH,AL AH = AH – AL – carry
SBB AX,BX AX = AX – BX – carry
SBB EAX,ECX EAX = EAX – ECX – carry
SBB CL,2 CL = CL – 2 – carry
SBB RBP,8 RBP = RBP– 2 – carry (64-bit mode)
SBB BYTE PTR[DI],3 Both 3 and carry subtract from the data segment memory location addressed by DI
SBB [DI],AL Both AL and carry subtract from the data segment memory loca-tion addressed by DI
SBB DI,[BP+2] Both carry and the word contents of the stack segment memory location addressed by BP plus 2 subtract from DI
SBB AL,[EBX+ECX] Both carry and the byte contents of the data segment memory location addressed by EBX plus ECX subtract from AL
CF
(SBB) (SUB)
BX AX
SI DI
BX AX
–
FIGURE 5–2 Subtraction-with-borrow showing how the carry flag (C) propagates the
FIGURE 5–2 Subtraction-with-borrow showing how the carry flag (C) propagates the