Chapter 2 Thermal Noise in MOSFETs
2.2 Noise Analysis
2.2.3 Further analysis
Now, we start to derive the new noise equations of the relationship between noise performance and the characteristics again. Recall that the MOSFETs noise model consists of two generators. The mean-square drain current noise from the thermal current noise and the substrate thermal noise is:
C f
We will ignore the second term of the drain thermal current noise since it will drop quickly at the high frequencies range.
The drain-induced-gate-noise is:
f
Further recall that the drain-induced-gate-noise is correlated with the drain noise, with a correlation coefficient defined formally as:
2
The long-channel value of c is theoretically –j0.395. Precise measurements of the correlation coefficient are difficulty to carry out (especially in the deep sub-micron
factor of 2 of this theoretically value, even for devices with drawn channel lengths as small as 0.13µm.
To derive the four equivalent two-port noise parameters, repeated here for convenience,
f KT R
ne
n≡ ∆ 4
2
(11)
f KT G
ui
u≡ ∆ 4
2
(12)
c c
n c
c
G jB
e
Y ≡ i = +
(22)We first reflect the two fundamental MOSFETs noise source back to the input as a different pair of equivalent input generator (one voltage and one current source).
The equivalent input noise voltage generator accounts for the output noise observed when the input port is short-circuited. To determine its value, reflect the drain current noise back to the input as a noise voltage source and recognize that the ratio of these quantities is simply gm. But there is one more important noise source which should be added in account. That is the gate resistance thermal noise which becomes more and more significant effect on the noise performance in recently deep sub-micron technology. Thus, the over all equivalent input noise voltage generator including gate resistance and the reflected noise current is equal to:
0
from which it is apparent that equivalent input noise voltage is completely correlated, and in phase, with the drain current noise. Thus, we can immediately determine the equivalent noise resistance that:
0
The equivalent input noise voltage generator by itself does not fully account foe the drain current noise, however, because a nosy drain current also flows even when the input is open-circuits and the drain-induced-gate-noise is ignored. Under this open-circuit condition, dividing the drain current noise by the transconductance yields an equivalent input which, when multiplied by the input admittance, gives us the value of an equivalent input current noise that completes the modeling of ind:
0 2
In this step of the derivation, we have assumed that the input impedance of a MOSFET is purely capacitive. This assumption is a good approximation for frequencies well below ωT, if appropriate high-frequency layout practice is observed to minimize gate resistance. Given this assumption, Eqn. 25 shows that the input noise current in1 is in quadrature, and therefore completely correlated, with the equivalent
The total equivalent input current noise is the sum of the reflected drain noise contribution of Eqn. 25 and the induced gate current noise. The induced gate noise current itself consists of two terms. One, which we’ll denote ingc, is fully correlated with the drain current noise, while the other, ingu, is completely uncorrelated with the drain current noise. Hence, we may express the correlation admittance as follows:
⎟⎟ ⎠
For simplifying the expression, we define a gate-resistance coefficient, Z, with the following relation:
2
So we can redraw some of the formulas which we just derived before as:
2
2
To express Yc in a more useful form, we need to incorporate the induced gate noise correlation factor explicitly. To do so, we must manipulate the last term of Eqn.
26 in ways that will initially appear mysterious. First, we express it in terms of cross-correlations by multiplying both numerator and denominator by the conjugate of the drain noise current and then averaging each:
gs
If we assume that c continues to be purely imaginary, even in the short-channel regime, we finally obtain a useful expression for the correlation admittance by combining Eqn. 26 and 31 as that:
⎟⎟ ⎠
where we have used the substitution:
0
Since α is unity for long-channel devices and progressively decrease as channel lengths shrink, it is one measure of the departure from the long-channel regime.
We see from Eqn. 32 that the correlation admittance is purely imaginary, so that Gc=0. more significant, however, is the fact that Yc does not equal the admittance of Cgs, although it is some multiple of it. Hence, one cannot maximize power transfer and minimize noise figure simultaneously. To investigate further the important implications of this impossibility, though, we need to derive the last remaining noise parameter, Gu.
Using the definition of the correlation coefficient, we may express the induced gate noise as follows:
)
The last term in Eqn. 34is uncorrelated portion of the induced gate noise current, so that, finally:
0
With these parameters, we can determine both the source impedance that minimizes the noise figure as well as the minimum noise figure itself:
⎟⎟ ⎠
From Eqn. 36, we see that the optimum source susceptance is essentially inductive in character, except that it has the wrong frequency behavior. Hence, achieving a broadband noise matching is fundamentally difficult.
Continuing, the real part of the optimum source admittance is:
And the minimum noise figure is given by:
)
In Eqn. 38, the approximation is exact if one threats ωT as simply the ratio of gm
to Cgs. Note that if there were no the drain-induced-gate-noise current (i.e., if δ were zero), the minimum noise figure would be 0 dB. That unrealistic prediction along should be enough to suspect that the induced gate noise must indeed exist. Also note that, in principle, increasing the correlation between drain and gate current noise would improve noise figure, although correlation coefficient unrealistic near unity would be required to effect large reductions in noise figure.
Another important observation is that improvements in ωT that accompany technology scaling also improve the noise figure at any given frequency. However, the rapid pace of change in IC technology virtually guarantees an incomplete understanding of the behavior of transistors of the most recent generations of technology. Because the detailed behavior of some of the coefficients in the short-channel regime is still unknown, we will have to make accurate noise
measurement and then carefully extract the important MOSFETs noise coefficients.
III. MOSFETs Noise Coefficients Extraction
3.1 Introduction
The RF noise is difficult to measure in Si MOSFETs due to the strong parasitic substrate loss (shown in fig. 5) that dominates the noise in as-measured NFmin.
De-embedding is required to give the much smaller intrinsic NFmin [3]-[5] - this can produce errors. To overcome this problem we used a novel microstrip transmission line layout, which is shown in figure 6. Figures 7(a) and 7(b) show the as-measured NFmin of different gate fingers devices, respectively. The as-measured NFmin using the standard CPW transmission line design is also shown for comparison. A large NFmin reduction over the whole frequency range is observed using the microstrip line design, even without de-embedding. At 10 GHz, the as-measured NFmin is only 0.9 dB for the 8 gate-finger MOSFET. This is the lowest reported NFmin for a 0.18 µm MOSFET and is comparable with the data for 0.13 µm devices (Lg= 80nm) [4]-[5].
The low NFmin of 0.9 dB at 10 GHz is sufficient for UWB (3.1-10.6 GHz) applications.
Figure 5 Complex parasitic circuits of CPW layout.
DUT DUT
Figure 6 Developed microstrip line structure.
Lthru1
Csub1 Rsub1
Rthru2 Lthru2
PORT1 PORT2
Csub2 Rsub2 RB
Rthru1 Rg
Cox1 Cox2
Rpad1 Cpad1 C'pad1
Rpad2 Cpad2 C'pad2
pad through intrinsic through pad
Lthru1
Csub1 Rsub1
Rthru2 Lthru2
PORT1 PORT2
Csub2 Rsub2 RB
Rthru1 Rg
Cox1 Cox2
Rpad1 Cpad1 C'pad1
Rpad2 Cpad2 C'pad2
pad through intrinsic through pad
0 2 4 6 8 10 12 14 16 18 20 0.0
0.5 1.0 1.5 2.0 2.5
NFmin_Microstrip (dB)
Frequency 8 fingers
16 fingers 32 fingers 64 fingers
Figure 7(a) NFmin of different fingers on microstrip.
0 2 4 6 8 10 12 14 16 18 20
0 1 2 3 4 5 6
NFmin_CPW (dB)
Frequency 8 fingers
16 fingers 32 fingers 64 fingers
Figure 7(b) NFmin of different fingers on CPW.
The equivalent noise resistance of the two-port, which is shown in figure 8, decreases slightly with increasing frequencies. This is because that the substrate thermal noise which we ignore in our noise equations contributes some the equivalent noise resistance. As a result, we will extract the noise coefficients, such as γ and δ, at high frequencies range (10GHz) in order to get the better accuracy.
0 2 4 6 8 10 12 14 16 18 20
0 50 100 150 200 250 300 350 400
Rn
Frequency
8 fingers 16 fingers 32 fingers 64 fingers
Figure 8 Equivalent noise resistance of different fingers versus freq.
Figure 9 Test-key layout.
0.2 0.5 1.0 2.0 5.0
-0.2j 0.2j
-0.5j 0.5j
-1.0j 1.0j
-2.0j 2.0j
-5.0j 5.0j
8 fingers 16 fingers 32 fingers 64 fingers
Figure 10 Γopt of different fingers on smith chart.
The figure 9 is the layout of the ultra-low noise MOSFETs, which includes the conventional CPW and our microstrip layout of MOSFETs and two more 3D inductors. And the figure 10 shows the optimum source impedance of the ultra-low noise MOSFETs. Sine we have derived the accurate noise data, we will start to extract the noise coefficients in the next step.
3.2 Extraction Results
According to our noise equations, we can extract the thermal drain current noise factor, γ, from Rn which is shown in the equation 30.
By our extraction, the thermal drain current noise factor, γ, is about to 0.9, which is shown in figure 11. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short channel MOSFETs. The abnormal among of noise from other group’s results maybe due to inaccuracy measurements, lacking of gate and substrate thermal noise, or inappropriate layout.
0 10 20 30 40 50 60 70
Figure 11 Extracted γ factor of different fingers at 10GHz.
The other two coefficients, c and δ, can be extract from equation 36~38 which are recalled again here for convenience.
⎟⎟⎠
By the extraction, the correlation factor, c, remains the value of –j0.395 as it in the long-channel regime theory [9], while δ is twice the value of γ. This value of δ is reasonable since it comes from the thermal drain current noise.
Figure 12 ~ 17 show the extraction results. Figure 12 and 13 represent the measured and modeling optimum source impedance respectively at 10GHz, while figure 14 is the measured and modeling NFmin at 10GHz. And figure 15 demonstrate the measured and modeling optimum source versus frequencies with 32 gate fingers, while figure 16 is the measured and modeling NFmin versus frequencies with 32 gate fingers. Very Good agreement between the measurements and our modeling is achieved by using our derived noise equations. Figure 17 tabulates the relative characteristics of the RF MOSFETs that we measured.
0 10 20 30 40 50 60 70 -0.016
-0.014 -0.012 -0.010 -0.008 -0.006 -0.004 -0.002 0.000
B opt
Fingers Number
modeling data measured data
Figure 12 Modeling and measured Bopt of different fingers at 10GHz.
0 10 20 30 40 50 60 70
0.000 0.001 0.002 0.003 0.004 0.005 0.006
G opt
Fingers Number modeling data
measured data
Figure 13 Modeling and measured Gopt of different fingers at 10GHz.
0 10 20 30 40 50 60 70 0.0
0.5 1.0 1.5 2.0
NF min (dB)
Fingers Number modeling data measured data
Figure14 Modeling and measured NFminof different fingers at 10GHz.
0 1 1 2 5
-0j 0j
-1j 1j
-1j 1j
-2j 2j
-5j 5j
measured modeling
0 2 4 6 8 10 12 14 16 18 modeling data measured data
Figure 16 the NFmin versus frequencies of 32 gate fingers.
2γ
Characteristics
\
F.N.2γ
Characteristics
\
F.N.Figure 17 Summary of MOSFETs characteristics.
3.3 Conclusions
We have developed a new microstrip line design to measure NFmin accurately without the need for complicated de-embedding. Based on the accurate NFmin measurement and analytical NFmin equation, close agreements to the measurements with modeling data are all obtained that is important for further circuit application.
IV. UWB LNA Design
4.1 Introduction
Ultra wideband (UWB) systems are a new wireless technology capable of transmitting data over a wide spectrum of frequency bands with very low power and high data rates. Among the possible applications, UWB technology may be used for imaging systems, vehicular and ground penetrating radars, and communication systems. Although the UWB standard (IEEE 802.15.3a [16]) has not been completely defined, most of the proposed applications are allowed to transmit in a band between 3.1 and 10.6 GHz. In this work, the design of a low noise amplifier (LNA) in a 0.18µm CMOS technology for the receiver path of a UWB system is discussed. Such an amplifier must feature wide-band input matching to a 50Ω antenna, flat gain over the entire bandwidth, good linearity, minimum possible noise figure and low power consumption.
In recent years, narrow-band CMOS LNA designs have employed inductive source degeneration to achieve good input matching. This technique also yields nearly optimal noise figure at the resonance frequency of the input network [17]. In the proposed wide-band design in Figure 16 (at the next section), the inductively degenerated common source topology is further explored. The input impedance Zin is embedded in a two-section band-pass filter to resonate its reactive part over the whole
band. The cascode configuration improves the reverse isolation and the frequency response of the amplifier. Source-follower buffer of the second stage is intended for measurement purposes, i.e. to drive an external 50Ω load.
4.2 Design Procedures
In this work, we first use inductive source degeneration to achieve good matching to 100Ω in stead of the conventional 50Ω to decrease the Q value of the serial resonance circuits. This is because that the lower Q value implies the wider bandwidth, which makes a broadband matching. Then we add an L-section circuit to transfer the 100Ω to the source impedance 50Ω. Finally by using CAD tool to optimize the circuits, we can achieve an input reflection coefficient to smaller than -10dB in-band: Ls=0.9nH, Lg=1.6nH, L1=0.9nH and C1=0.25pF. The size of M1 is chosen as 128 gate fingers to minimize the inductance values. The bias of M1 is set for balance between gain and power consumption.
The cascode device is chosen as small as possible to reduce the parasitic capacitances. A lower limit to the width of M2 (24 gate fingers) is set by its reasonable Vds. Both M1 and M2 are minimum length devices. The load is designed to achieve flat gain over the whole bandwidth. In-band, M1 acts as a current amplifier, the input current being Vin/Rs, and the current gain β(ω)=gm/(jωCgs). To compensate
for the roll-off of β(ω), a shunt-peaked load is used. The value of the inductance L2 (2.3nH) is limited by acceptable power gain over shooting. Resistance RL (60Ω) improves the gain at lower frequency. All the design and the layout are shown in figure 18 and figure 19 respectively.
M1 M2
M3
M4
Ls Lg
L1 C1
RL
L2
L3 M1
M2
M3
M4
Ls Lg
L1 C1
RL
L2
L3
Figure 18 Circuits diagram.
Figure 19 Chip layout.
4.3 Simulation results
Figure 20 shows the simulated input and output reflection coefficients. S11 is lower than -8dB between 3.1 and 12GHz. The output buffer achieves excellent matching such that S22 is lower than -10dB from 1.7GHz to 15.9 GHz. Figure 21 is the power gain versus frequencies, and the maximum power gain is 10.4dB in our simulation results. Since the output source follower drives a matched load, the voltage gain of the core amplifier is exactly 6dB higher than S21. The -3dB bandwidth is 0.4~9.9GHz for the simulation. The noise figure (NF) of this UWB LNA is shown in Figure 22. The noise figure is as low as 3.3dB at 6GHz which is the center frequency
of UWB system, while the average noise figure in-band is about 4dB. Figure 23 and 24 show the simulated reverse isolation S12 and stability factor respectively. The two-tone test results for third-order intermodulation distortion are shown in Figure 25.
The test is performed at 6GHz. IIP3 is to 3.3dBm, and the input referred 1-dB compression point (ICP) is -9dBm. These results imply excellent linearity of our LNA.
The proposed UWB LNA dissipate 27mW (15mW for first stage) with a power supply of 1.8V. Figure 27 summarizes the performance of the presented amplifiers,
m2freq=
dB(S(1,1))=-7.9563.100GHz m3 freq=
dB(S(1,1))=-8.1787.900GHz m4 freq=
dB(S(1,1))=-13.06710.60GHz
2 4 6 8 10 12 14 16 18
0 20
-20 -15 -10 -5
-25 0
freq, GHz
dB(S(1,1))
m2 m3
m4
dB(S(2,2))
Figure 20 Simulated S11 & S22.
m1 freq=
dB(S(2,1))=7.884 3.600GHz m5 freq=
dB(S(2,1))=10.427 7.500GHz
2 4 6 8 10 12 14 16 18
0 20
0 10
-10 20
freq, GHz
dB(S(2,1))
m1 m5
Figure 21 Simulated power gain.
m6 freq=
nf(2)=3.326 6.100GHz
2 4 6 8 10 12 14 16 18
0 20
5 10 15 20
0 25
freq, GHz
nf(2)
m6
NFmin
Figure 22 Simulated NF and NFmin.
2 4 6 8 10 12 14 16 18
0 20
-100 -80 -60 -40
-120 -20
freq, GHz
dB(S(1,2))
Figure 23 Simulated reverse isolation.
2 4 6 8 10 12 14 16 18
0 20
2 3 4 5
1 6
freq, GHz
Mu1MuPrime1
Figure 24 Simulated stability.
Figure 25 Two tones test.
Figure 26 Power-out versus power-in.
m1 Pin=
dBm(out[::,1])=-0.044 -9.000
-70 -60 -50 -40 -30 -20 -10 0
-80 10
-60 -40 -20 0
-80 20
Pin
dBm(out[::,1])
m1
m1indep(m1)=
plot_vs(dBm(out), freq)=-70.1116.000E9 m2indep(m2)=
plot_vs(dBm(out), freq)=-236.7515.950E9
5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4
5.5 6.5
-300 -250 -200 -150 -100
-350 -50
freq, GHz
dBm(out)
m1
m2
EqnIIP3=(m1-m2)/2-80 indep(IIP3)
<invalid>
IIP3 3.320
27; 15
Figure 27 Simulated circuits SPEC summary.
4.4 Measurements and Conclusions
The following figures 28~33 are the measurement results which are only slightly different form our simulation, which imply good accuracy of our simulation and good circuit design. The some of the bandwidth compression showing in figure 28 maybe due to the underestimate of the load resistor parasitic.
0 2 4 6 8 10 12 14 16 Figure 28 Measured power gain.
0 1 2 3 4 5 6 7 8 9 10 0
5 10 15 20
NOise Figure (dB)
Frequencies Figure 29 Measured noise figure.
0 2 4 6 8 10 12 14 16
-20 -15 -10 -5 0
S11 S-parameters (dB) S22
Frequencies Figure 30 Measured S11 and S22.
0 2 4 6 8 10 12 14 16 -50
-40 -30 -20 -10 0
S12
S-parameters (dB)
Frequencies Figure 31 Measured S12.
-30 -25 -20 -15 -10 -5 0
-80 -70 -60 -50 -40 -30 -20 -10 0 10
OP1 Output Power (dB) OP3
Input Power (dB) Figure 32 Measured linearity.
Figure 33 Measured results summary.
The bandwidth of this work with considering matching and power gain is from 3 to 8 GHz, while the average power gain is about 8dB which can be up to 14 dB without the current buffer in real cases. The noise performance is good and the minimum noise figure is only 3.5dB at 3~4GHz. The noise figure can be even better if we solve the bandwidth compression problem from the resistor parasitic. Input and output matching are achieved well in band and the linearity of this work is excellent.
Total power consumption is 27mW, while the core LNA consumes only 15mW by 1.8V power supply. By the new input matching approach we proposed, a low noise, broadband, low power consumption and good-linearity amplifier is developed for the UWB system applications.
+2
Figure 34 Die photo.
Figure 35 Comparison of broadband LNA performance.
0.18μm 2004
V. Summary
Let us summary the conclusions of this paper briefly.
Noise modeling: The low noise amplifier in a RF receiver is a significant component, since it plays an important role in the noise performance of a RF system, which affects the dynamic range and the signal to noise ratio of this system. The current noise model with BSIM3v3 core can not model the noise behavior correctly. In order to develop the accurate noise model of RF MOSFETs, we have developed a new microstrip line design to measure NFmin accurately without the need for complicated de-embedding. Based on the accurate NFmin measurement and analytical NFmin equation, close agreements to the measurements with modeling data are all obtained that is important for further circuit application.
UWB LNA: By the new input matching approach we proposed, a low noise, broadband, low power consumption and good-linearity amplifier is developed for the future UWB system applications. The advantages of this design include extending the famous source L-degenerate matching to broadband, low noise, low power consumption, reducing inductor numbers and excellent linearity. All the advantages are important for UWB system considerations.
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