Analytical results

We evaluate lower bounds for the RSC codes given in Table 3.1. Figs. 3.5-3.7 plot the lower bounds for various interleaver lengths TsL. Larger component code period generally gives higher lower bound, as indicated by these curves.

Separate encoding improves the lower bounds for some interleaver lengths but also imposes constraints on interleaver lengths. These figures shows 10–50 weight improve-ments on the lower bound for long interleaver lengths but W2(L) is small for short interleaver lengths. Fig. 3.7 indicates that, the lower bound is a decreasing function of Ts for short block length. Corollary 3.2 says that W2(L) is not a dominant factor of the lower bound if the block length constraint L ≥ (T^c+ 2d)M is satisfied.

Fig. 3.5 compares the upper bound [25] and the lower bound we derived. The large

“gap” between the upper and lower bounds is due to the fact that [25] does not consider the weight-2 error events resulted from adjacent partitions but our derivation does. The

gap would be much reduced if these events were taken into account.

0 200 400 600 800

20 40 60 80 100 120 140

T_s=1 T_s=2 T_s=4 T_s=6 T_s=8 Upperbound [4]

The Weight-2 Bound

Interleaver Length

Figure 3.5: The weight 2 lower bound for the Scrambling function _1+D+D^1+D22.

We derive a general achievable codeword weight lower bound for the weight-2 error events when a TB-IBPTC uses two identical RSC code. The bound implies separate encoding stands a better chance to obtain a weight-2 lower bound larger than that of the conventional continuous encoding scheme if the block length is not too small and is properly chosen. The relationships between these two parameters and the lower bound provide useful design guideline for TB-IBPTC.

0 400 800 1200 30

60 90 120 150

Ts=1 Ts=2 Ts=3 Ts=4 Ts=5

The Weight-2 Lower Bound

Interleaver Length

Figure 3.6: The weight 2 lower bound for the Scrambling function _1+D^1+D+D2+D³³.

0 400 800 1200 1600

40 120 200 280 360

T_s=1 T_s=2 T_s=3

The Weight-2 Lower Bound

Interleaver Length

Figure 3.7: The weight 2 lower bound for the Scrambling function ^1+D_1+D+D^2+D3+D4 ⁴.

Chapter 4

Block-oriented inter-block permutation interleaver

Block-oriented inter-block permutation (B-IBP) interleaver is a definite length turbo code interleaver design regarding to the parallel turbo decoder architecture. The ar-chitecture has five implementation issues: memory contention [49, 20, 98, 97], network routing and control signalling [78, 68, 67, 33], permutation table storage [70, 95, 96]

and the support of high-radix APP decoding. B-IBP interleaver can well address these issues. The invariant IBP and identical intra-block permutation mentioned in Theorem 3.1 resolve memory contention. The network-oriented B-IBP design reduces network routing complexity and simplifies network control signaling. Choosing an intra-block permutation whose permutation table can be generated on-fly avoids memory storage for permutation table. If the block interleaver is generalized maximal contention-free, the associated B-IBP interleaver is also generalized maximal contention-free. Further-more if the block interleaver supports the high-radix APP decoder [16], the associated B-IBP interleaver also supports the high-radix APP decoder. One can find popular interleavers such as almost regular permutation (ARP) [12, 37, 38, 56], quadratic poly-nomial permutation (QPP) [90, 85, 92, 93, 3] and inter-window shuffle interleaver [69, 70]

belonging to this class of B-IBP interleaver and enjoy these properties. However the in-terleaver restricts the inin-terleaver length which is identical to the multiple of the block length. Therefore we propose shortening position assigning algorithm. This algorithm

not only supports various input information lengths but also reduces implementation complexity without obvious performance degradation. At last an example of the B-IBP interleavers ranging from 40 to 6144 bits is proposed and this interleaver supports the above mentioned hardware properties. The associated implementation applying the in-terleaver with 4096 bits is provided and requires less power consumption comparing to fashion designs.

4.1 The parallel turbo decoder architecture and mem-ory contention

The parallel turbo decoder applies N APP decoders instead of a single APP decoder to increase decoding throughput by N . Since there are N APP decoders, the turbo decoder requires N memory banks to store received samples and the extrinsic messages while a network connects these APP decoders and memory banks. Fig. 4.1 (a) shows an example of the architecture with N = 4 and a fully-connected network [35] bridges both sides. These APP decoders apply the sliding-window APP (SWAPP) decoding algorithm [104, 21] which can manipulate partial coded sequence to generate the extrinsic information. Therefore we partition a coded sequence into N segments so that each segment is decoded by one APP decoder.

Memory contention occurs due to the serial memory access of these APP decoders and influences the turbo decoding throughput and turbo decoder complexity. Each APP decoder requires prior and successive extrinsic messages to decode each bit (symbol) and it must decode information bits sequentially using a reasonable window size. The APP decoders sequentially access certain memory banks to fetch or write the extrinsic mes-sages according to an interleaving-deinterleaving rule. The interleaving-deinterleaving rule may induce memory contention and more than one APP decoder want to access the same memory bank simultaneously; see Fig. 4.1 (b). Memory contention decreases de-coding throughput and increases decoder complexity because these APP decoders require

1 2 3 4 Memory

Banks

1 2 3 4

APP Decoders

(a)

1 2 3 4

Memory Banks

1 2 3 4

APP Decoders

(b)

1 2 3 4

Memory Banks

1 2 3 4

(c)

APP Decoders

Figure 4.1: (a) The block diagram of the parallel turbo decoder architecture with par-allelism degree 4; (b) memory contention; (c) memory contention-free.

contention avoidance circuit to stagger memory access. [49] proposed using a buffer to store temporary data to resolve memory contention but the complexity increases linearly with the number of APP decoders.

An interleaver that resolves memory contention without extra buffer and contention avoidance circuit will minimize the corresponding decoder complexity. To assure memory contention-free (see Fig. 4.1 (c)), the interleaving law has to be such that at each instance there is a one-to-one mapping between the memory banks and APP decoders.

It is also desired that the interleaving rule supports various numbers of APP decoders so that trade-off between complexity and throughput is available. We give a definition for memory contention-free property to facilitate our discussions.

Definition 18 A length-K interleaver supports memory contention-free property for N =§_K

L

¨ APP decoders, if there exist two K-to-N mapping functions M and M^d such that M(iL+k) 6= M(jL+k), M^d(iL+k) 6= M^d(jL+k), M^d(π(iL+k)) 6= M^d(π(jL+k)) and M(π⁻¹(iL + k)) 6= M(π⁻¹(jL + k)), ∀ 0 ≤ i < j < N, 0 ≤ k < L, 0 ≤ iL + k < K and 0 ≤ jL + k < K.

Assume there are N APP decoders, where the jth APP decoder processes information sequence ranging from the jLth symbol to the (j + 1)L − 1th symbol. We allocate information symbols satisfying the mapping properties described in Definition 18. Then the jth APP decoder fetches message from memory bank M(jL + k) (M^d(jL + k)) and write message to memory bank M^d(π(jL + k)) (M(π⁻¹(jL + k))) without memory contention if these N APP decoders process the kth bits in each length-L information symbol sequence concurrently. The definition is well-defined.

One may find a contention-free definition as

Definition 19 A length-K interleaver Π is contention-free for N =§_K

L

¨ APP decoders if both φ = π and φ = π⁻¹ satisfy

¹φ(k + iL) L

º 6=

¹φ(k + jL) L

º

. (4.1)

This definition is only a special case corresponding to our Definition 18 with the mapping functions M(k + iL) = i and M^d(k + iL) = i.