Fig. 7-1 Sequences of negative bias temperature instability (NBTI) …..…………..216
Fig. 7-2 (a) The NBTI degradation under various stress conditions at 25 oC. (b) Anomalous NBTI degradation showed in Fig.7-1(a) …..………217
Fig. 7-4 Impact of temperature on threshold voltage shift during NBTI degradation…..……….………219
Fig. 7-5 Impact of temperature on interface degradation during NBTI process…..……….………...220
Fig. 7-6 Impact of temperature on the generation of bulk traps in HfO2 at (a) stress | Vg | < | -3.1V | (b) stress | Vg | > | -3.1V |…..………...221
Fig. 7-7 Threshold voltage shift versus number of injection charge under various stress conditions at 25oC…..……….………..…..222
Fig. 7-8 Charge pumping results related to anomalous NBTI conditions…..…..…..223
Fig. 7-9 Similar phenomena showed on Id-Vg results in HfSiON/SiO2 gate stack. (a) Electron trapping (b) Transition (c) Hole Trapping…..………...224
Fig. 7-10 Similar phenomena showed on charge pumping current results in another experiments. (a) Electron trapping (b) Transition (c) Hole Trapping…..……….………...225
Fig. 7-11 Band diagram under various stress conditions with respect to distinct polarity of net trapped charge…..……….……….226
Fig. 7-12 Bulk traps in HfO2 under various stress conditions…..………227
Fig. 7-13 Impacts of (a) AC frequency (b) duty cycle on threshold voltage shift,
Fig. 7-14 Impacts of (a) AC frequency (b) duty cycle on interface degradation,
(ΔNit) …..……….……….229
Fig. 7-15 Lifetime prediction with consideration of anomalous NBTI…..…………..230
Chapter 1
Introduction
1.1 Motivation of Using High-κ Gate Dielectrics
As the CMOS technology continues to scale down following the Moore’s Law, the shrinkage of gate dielectric thickness is approaching a physical limitation of conventional SiO2-based ultrathin oxide [1]. The aggressive scaling of CMOS technology leads the ultrathin gate oxide to suffer the intolerable direct tunneling gate leakage current which results in the devices to face the serious concerns such as gate integrity, stand-by power consumption, and associated reliability issues [2-5]. As the rapid reduction of equivalent oxide thickness (EOT), the appropriate EOT requirements with the considerations of the tough challenges are outlined by the International Technology Roadmap for Semiconductors (ITRS) in Table 1-1 [6].
In recent years, numbers of alternative gate dielectric materials have been extensively investigated on the aggressive attempts to replace the conventional ultrathin gate oxide. High dielectric permittivity gate dielectrics (high-κ gate dielectrics) have been proposed to be the potential candidates to solve the critical issues since their thicker films can be utilized to reduce the large direct tunneling leakage current while maintaining EOT value and the device performances [7-9]. Presently, many associated researches about high-κ gate dielectrics have been widely investigated to explore their detailed properties. The experimental results have demonstrated the compatibility of high-κ gate dielectrics in CMOS technology, and some findings have successfully
applications [10-12]. The selections of high-κ gate dielectrics are usually consistent with the requirements of sufficient κ-value, wide bandgap, thermal stability, and process compatibility [13-15]. At the beginning of high-κ researches, many high-κ gate dielectrics including Ta2O5, TiO2, Si3N4, Al2O3, and HfO2 are considerations in the related researches [16-23]. However, Ta2O5, TiO2, Al2O3, are gradual far away the major current in high-κ investigations with the comprehensive considerations of poor thermal stability (Ta2O5, TiO2) and insufficient κ-value (Si3N4, Al2O3). Nowadays, Hf-based family such as HfO2, HfON (nitride), HfSiO (silicate), HfAlON (multi-elements incorporation) become the most promising solutions due to the moderate dielectric constant (20~25), large energy bandgap (5.7~6.2 eV), sufficient barrier height to Si for both electrons and holes (1.5~1.9eV), and excellent thermal stability of amorphous phase and interface properties (~1000 )℃ [19-22, 24-26].
1.2 Critical Issues of High-κ Gate Dielectrics
Nowadays, high-κ gate dielectrics become the promising solutions to replace the conventional ultrathin oxide in order to keep the steps of developing advanced CMOS technology. However, the high-κ gate dielectrics have several critical problems needed to overcome in progress. In the early researches, the thermal stability of high-κ materials is a quite urgent issue in the device integration. The high-κ gate dielectrics easily react with the Si-substrate to result in the formation of based oxide (or silicate) on the Si surface. These extra interfacial layers between high-κ and Si-substrate usually have the poor film quality and the increasing EOT requirements to restrain the CMOS technology development. Moreover, the amorphous crystallization is the preferable phase to prevent from the significant direct-tunneling gate-leakage-current. However,
low crystallization temperature. For HfO2, slight crystallization is already observed when temperature is around 400 ~ 500 ℃ [27]. Nevertheless, the high-κ gate dielectrics are inevitable to suffer the crucial temperature which might be up to 950 ℃ in a complete CMOS process (such as the post rapid thermal annealing to enhance the quality of gate dielectrics ; high temperature activation to drive the implanted dopants.) [28-29]. Fig. 1-1(a)-(d) showed the HRTEM pictures of the HfO2 with various high temperature annealing (a) as-deposited state, 400 °C, (b) 800 °C annealing, (c) 900 °C annealing, (d) 1000 °C annealing, respectively [27]. Although HfO2 is more close to amorphous phase in the as-deposited state, there is still partially crystallization observed in HfO2 itself. Moreover, higher temperature drives up the crystallization of HfO2 itself and increase the interfacial layer (eq. based oxide); those imply the poor thermal stability of high-κ gate dielectrics. In order to overcome the significant issues of thermal stability, numbers of related process have been modified with less thermal budget (ex a rapid thermal process is preferred replacing the conventional furnace process.) to avoid the interaction between high-κ and Si-substrate. In addition, the formation of multi-element high-κ compounds is also adopted to solve this critical problem because of elevated crystallization temperature. The Hf-based high-κ gate dielectrics have been demonstrated to depict better capability of crystallization temperature even above 1000
℃ [30-33].
Except the concerns of thermal stability, plenty of the pre-existing bulk traps have been verified to exist in Hf-based high-κ gate dielectrics, thus led to significant impacts on device performance and reliability. The Fermi-level pinning effect is one of the critical issues. The origin of Fermi-level pinning effect is resulted from the existence of electrical dipole with respect to the inter reaction and electron exchange between the
reports [36, 39], a formation of an oxygen vacancy would result in the generation of two electrons. If the oxygen vacancy is near the interface, the generated electrons can transfer across the interface to the poly-Si gate electrode and an interface dipole produced in the oxide. The dipole would lead to the large threshold shift and causes some difficulties in logic designs. This existence of Fermi-level pinning effect has persecuted the developments of the advanced gate stack to achieve the appropriately low threshold voltage, which can meet the future progress of CMOS technology. Fig.
1-2(a)-(c) showed the Fermi-level pinning effect in high-κ gate dielectrics revealed in C-V characteristics (a) SiON (b) HfAlOx (c) HfSiOx [39]. Today, a method of replacing the poly-Si electrode by metal gate is considered as the practical solution for this problem [40]. The related investigations have been verified to effectively reduce the Fermi-level pinning effect and accomplish the proper requirements of low threshold voltage. Furthermore, the other researches also have found that insertion of an ultra-thin cap layers in between the poly-Si and the high-κ gate dielectrics can also improve the Fermi-level pinning effect by means of eliminating the inter electron exchange and oxygen vacancies in between gate electrodes and high-κ gate dielectrics [41].
The channel mobility degradation becomes another significant problem when the high-κ gate dielectrics have been applied on the CMOS technology [42-43]. Fig. 1-3 represented the apparent mobility degradation with the high-κ gate stack. This phenomenon is governed by various scattering mechanisms at the bulk silicon and at the gate dielectric/Si interface with respect to the variety of Coulomb, phonon, and surface roughness (at high electric field) scattering as well known [44-45]. In high-κ gate dielectrics, the most critical concern is the most significant phonon scattering referred to the great quantity of high-κ bulk traps. Plenty of high-κ investigations demonstrated the
degradation [46-47]. These phonons will interact with the channel electrons and produce the apparent mobility degradation. Especially, the soft optical phonons would become actively at the elevated temperature because of the plenty of ionic bonds in high-k gate dielectrics themselves [48-49]. Besides, the interface dipole existed between high-κ gate dielectrics and based oxide (or called as interfacial layer, IL) is also demonstrated as the major reason which is responsible for the channel mobility degradation shown in Fig.
1-4 [50]. Therefore, eliminating the high-κ bulk traps is essential for solving this perplexing problem. However, this specific and urgent problem is hard to remove due to the intrinsic properties of quantities of natural bulk traps in high-κ gate dielectrics. For the consideration, strain effect is thought as one of the most potential solutions to enhance the degraded mobility under the seriously unfavorable bulk traps. The physical mechanism can be explained as the related band splitting induced by the strain force. It leads the carriers with lower effective mass and higher mobility, and further enhances the channel mobility [51]. Many related researches have exhibited the brilliant results to verify the feasibility of strain effects including the globe strain and the local strain [45, 52]. The associated achievements of mobility enhancements conducted by strain effect are also revealed in Fig. 1-5(a) and Fig. 1-5(b) [53].
Overall, the most troublesome issue is considered as the significant charge trapping/de-trapping effects in the high-k gate dielectrics [54-55]. In the conventional SiO2 gate dielectrics, the NBTI degradation is a serious concern while the PBTI degradation is as less consideration [56]. However, both of hole trapping and electron trapping in high-κ are equally significant, and their impacts on device characteristics can not be neglected anymore according to plenty of intrinsic bulk defects. On one hand, the charge trapping usually occurs when devices are under the electrical stress due to the
hand, the charge de-trapping normally happens when devices are under the recovery force according to the relaxation of the trapped charges from the traps centers in high-κ gate dielectrics [59-60]. Both the charge trapping/de-trapping effects would result in the serious threshold voltage shift to degrade the device performance and associated reliability. Fig. 1-6(a) and Fig. 1-6(b) exhibited the charge trapping/de-trapping phenomena in the both nMOSFETs and pMOSFETs through the dynamic-PBTI and dynamic-NBTI degradations, respectively [61]. In our studies, the investigations of charge trapping/de-trapping in high-κ dielectrics are our major aims to understand the related physical mechanisms and further expect to develop the high-κ gate dielectrics on CMOS technology.
1.3 Dissertation Organization
As the passage above indicated, the aims of this dissertation will contain two parts of related high-κ researches including: (a) The investigations of device enhancements on the critical high-κ issues through the fabrication technologies are coordinated in the chapter 2, and (b) The studies of charge trapping/de-trapping behaviors in the aspects of device reliabilities through electrical characterizations. They are discussed in the chapter 3, 4, 5, 6, 7, respectively. The organization of this dissertation is briefly described as below. The chapter 2 studies the enhancements of device performance for the critical issues accompanied with the application of high-k gate dielectrics through the fabrication technologies. The ozone oxidation, fluorine incorporation, and tensile strain effect were utilized to improve the interfacial properties between high-κ gate dielectrics and Si-substrate, high-k bulk properties, and n-channel electron mobility, respectively. The chapter 3 studies the charge trapping behavior in the high-κ gate
charge trapping behavior leads the PBTI degradation in nMOSFETs with high-κ gate dielectrics. A universal physics model for the charge trapping in high-κ gate dielectrics is established through the investigations on stress voltage, stress time, and analysis of fast/slow charge trapping behaviors. Moreover, the new findings of charge trapping at the critical voltage which the FN-tunneling starts are also carefully discussed. The chapter 4 studies the charge de-trapping behavior in the high-κ gate dielectrics under various recovery conditions. As similar to the chapter 3, a mathematical modeling demonstrates the charge relaxation from the bulk trap centers to primarily dominate the charge de-trapping behavior in high-κ gate dielectrics. A universal physics model is also established through the investigations on stress voltage, recovery voltage, and analysis of fast/slow charge de-trapping behaviors. The chapter 5 discusses the necessary and the applications of pulse measurements with the further considerations of fast transient charge trapping/de-trapping behaviors. The transient charge trapping/de-trapping effects are systematically investigated through the stages of stress voltage, stress time, and recovery voltage. Lower activation energy extracted form the temperature dependence demonstrated the charge tunneling is the predominance for both charge trapping/de-trapping dynamics. Besides, the AC stress is also verified to have the apparent impacts on the charge trapping/de-trapping. The chapter 6 further explores the influences of charge trapping/de-trapping on the continuing device operation. The residual charges are demonstrated to significantly affect the dynamic-PBTI degradation in both DC and pulse measurements. The chapter 7 searches for the origin of anomalous NBTI behavior. A NBTI lifetime prediction is clarified to be necessary in the considerations of both hole trapping and electron trapping in pMOSFETs. The chapter 8 summarizes the related findings and recommends the further suggestions to the future
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