Table 4-1 Modeling fitting of charge de-trapping under all stress voltages………..139
Figure Captions
Chapter 1 Introduction
Fig. 1-1 HRTEM pictures of the HfO2 with various high temperature annealing (a) as-deposited state, 400 °C, (b) 800 °C annealing, (c) 900 °C annealing, (d) 1000 °C annealing, respectively…………...………...……..……18
Fig. 1-2 The Fermi-level pinning effect in high-κ gate dielectrics revealed in C-V characteristics (a) SiON (b) HfAlOx (c) HfSiOx………..……….……19
Fig. 1-3 Significant mobility degradation in the devices with poly-Si/high-κ gate dielectrics. The mobility can be improved with mid-gap metal gate electrode by screening the remote phonons scattering…..………20
Fig. 1-4 Interface dipole is considered as the primary origin of significant mobility degradation………...………...……..……21
Fig. 1-5 The strain engineering for High-k FETs (a) nMOSFETs (b) pMOSFETs………..……..……22
Fig. 1-6 The charge trapping/de-trapping phenomena in (a) Dynamic-PBTI, nMOSFETs (b) Dynamic-NBTI, pMOSFETs. ………...………..……23
Chapter 2 The Enhancements of Device Performance for High-κ Gate
Fig. 2-1 Key issues of high-κ gate dielectrics applied on CMOS technology………47
Fig. 2-2 Process flows and experimental conditions with the ozone surface treatment………48
Fig. 2-3 Growth curves of ozone-mediated oxides plotted as a function of the concentration of ozone in water………49
Fig. 2-4 Comparison of the etching rates at HF:H2O = 1:500 of the ozone-mediated oxide to that of the chemical oxide formed by RCA cleaning without HF-last………...………50
Fig. 2-5 HRTEM image of the ozone-treated HfO2 after PDA at 600 °C………...…51
Fig. 2-6 (a) Ozone-treated HfO2 w/o PDA (b) Ozone-treated HfO2 with PDA.
Ozone-treated HfO2 with an appropriate PDA exhibit the improved interface, and the less hysteresis even after a severe electrical stress………...…52
Fig. 2-7 Leakage current density of HfO2 gate stacks with respect to the various surface treatment processes………...………53
Fig. 2-8 C-V characteristics of HfO2 stacked gate dielectrics with respect to various surface treatment processes………...………54
Fig. 2-9 Hysteresis curves obtained with respect to the various surface treatment processes………...……….…55
Fig. 2-11 Charge trapping effects plotted with respect to the various surface treatment processes………...……….……57
Fig. 2-12 Investigations of reliability obtained in TDDB measurements with respect to the various surface treatment processes……….…58
Fig. 2-13 Process flow of fluorine incorporation………..……59
Fig. 2-14 SIMS profile of fluorine incorporation into Hf-based high-κ gate dielectrics…..………..………..……….…60
Fig. 2-15 Effect of fluorine incorporation was shown on C-V characteristics. A positive C-V shift was according to the diffusion of fluorine atom into
HfO2..………..……….….…….……61
Fig. 2-16 The Id-Vg characteristics showed the influences of fluorine incorporation.
The mechanism of positive Vt shift was similar to the C-V behavior due to fluorine diffusion into HfO2. The enhanced Gm revealed the improvement at interface of gate dielectric/Si-substrate because of F-Si bonding by fluorine incorporation……….……….……62
Fig. 2-17 The Id-Vd characteristics showed the enhancement of Fluorine incorporation on device driving current…………..……….……63
Fig. 2-18 The dependence of channel length on (a) threshold voltage, Vt (b) maximum transconductance, Gm (c) subthreshold swing, S.S……….…….……64
demonstrated by charge pumping current………...………...65
Fig. 2-20 The interface degradation in various fluorine dose conditions was investigated after electrical stress……….………….……66
Fig. 2-21 Two-frequency charge pumping method revealed the characteristics of interface state and high-κ bulk traps………...….……67
Fig. 2-22 The influence of temperature effect on interface degradation was studied through the NBTI process………...……….……68
Fig. 2-23 The NBTI degradation was investigated with respect to Fluorine dose conditions. The fluorine-incorporated samples showed a robust ability for reliability characteristics even at 125oC…..………….……….……69
Fig. 2-24 The behavior of total trap generation during NBTI degradation.…..………70
Fig. 2-25 The whole NBTI degradation was dominated by high-κ bulk degradation rather than the interface degradation…..………..……….……71
Fig. 2-26 Carrier mobility was extracted by Split-CV method. The enhanced mobility may be according to the reduction of remote phonon scattering because of fluorine incorporation repaired high-k bulk traps…..….………..…72
Fig. 2-27 Mechanism of strain effect influences on the enhancements of channel mobility…..………..……….……73
Fig. 2-29 (a) C-V characteristics were identical with various CESLs strain conditions.
(b) Extracted EOT form C-V characteristics were between 2.2~2.4 nm.….75
Fig. 2-30 The enhancements of CESLs strain effects exhibited in (a) Id-Vg
characteristics (b) Gm-Vg characteristics…..……….……76
Fig. 2-31 The CESLs strain effect were demonstrated in the enhanced driving current…..……….……….……77
Fig. 2-32 The channel length dependences on Gm.MAX. The enhancements of strain effect were apparently observed in short channel length…..………….……78
Fig. 2-33 Interface properties at SiON/Si-substrate were investigated through charge pumping method. A reduces of donor-like traps and interface states were found because a hydrogen passivation was conducted during SiN deposition by PECVD…..………..………….……79
Fig. 2-34 The PBTI degradation was investigated with respect to CESLs strain conditions. The experimental results were fine fitting with charge trapping model……….…..……….…….……80
Fig. 2-35 The dependences of stress voltage were also investigated in PBTI degradation…..……….……….……81
Fig. 2-36 Frenkel-Poole emission fitting was modeled for samples (a) w/o SiN capping.
(b) 300nm SiN capping. The trap energy level with respect to conduction band of HfO2 was extracted as 0.92eV for w/o SiN capping and 0.93eV for
Fig. 2-37 Fowler-Nordheim tunneling fitting was modeled for samples w/o SiN capping and with 300nm SiN capping. The nearly identical slopes of FN-tunneling fitting indicated that CESLs strain effect did not change the trap energy levels and charge trapping behaviors in HfO2…..………..83
Fig. 2-38 Flicker noise results were investigated in samples w/o SiN and with 300nm SiN. The elevated γ value extracted from flicker noise signal indicated the increase of trap density after PBTI degradation…..………..84
Fig. 2-39 The effective trap density was transformed from flicker noise signal. The experimental results implied that samples with SiN capping had a severe charge trapping in high-κ bulk, and it led to more significant PBTI degradation…..……….……….……85
Chapter 3 Charge Trapping Behavior in High-κ Gate Dielectrics
Fig. 3-1 Impacts of charge trapping on (a) Threshold voltage instability and (b) Transconductance, Gm…..……….……99
Fig. 3-2 The PBTI degradation under various stress voltages as a function of stress time…..……….………...100
Fig. 3-3 Modeling of charge trapping in nMOSFETs with Poly-Si/HfO2/SiON gate stack. (a) Maximum of trapping charges, ΔVMAX (b) Trapping time constant, τ0 (c) Related trap distribution, γ…..……….………..…102
stress voltage in high-κ gate dielectrics. The associated trap distribution is revealed by fitting parameter, γ…..………..………...…103
Fig. 3-5 A newly experimental results related to the traps generation under various stress voltages in high-κ gate dielectrics. The associated trap distribution is revealed by fitting parameter, γ…..………..…..………….…104
Fig. 3-6 A definition of fast trapping (t = 0 ~ 1.78 sec) and slow trapping (t = 1.78 ~ 100 sec) in our studies for the PBTI measurement with the conventional DC method…..……….………..……105
Fig. 3-7 Analysis of fast trapping, slow trapping, and total trapping under various stress voltages (a) Based SiO2 = 0.8 nm (b) Based SiO2 = 1.4 nm………..106
Fig. 3-8 Fast/total trapping ratio during whole PBTI degradation under various stress voltages (a) Based SiO2 = 0.8 nm (b) Based SiO2 = 1.4 nm. [A fast/total trapping ratio is defined as (fast trapping)/(total trapping) × 100 % in our studies] …..……….……….…107
Fig. 3-9 Comparisons of all charge trapping behaviors. (a) Fast trapping and slow trapping (b) Fast/total trapping ratio…..……….……...108
Fig. 3-10 The predominant conduction mechanism in the regime of gate voltage….109
Fig. 3-11 Frenkel-Poole emission (F-P) Fitting in the regime of stress voltage (a) Stress Vg = 0.6 ~ 1.0V (b) Stress Vg = 1.0 ~ 1.6V (c) Stress Vg = 1.6 ~ 2.0V…..……….…...110
Fig. 3-12 Fowler Nordheim tunneling (FN) Fitting in the regime of stress voltage (a) Stress Vg = 1.6 ~ 2.0V (b) Stress Vg = 2.0 ~ 2.6V…..………...…111
Fig. 3-13 Band diagram of charge trapping under various stress Vg conditions. (a) Stress Vg = 1.2V (b) Stress Vg = 1.5V (c) Stress Vg = 1.8V…..…………..112
Fig. 3-14 Modeling of charge trapping at various stress time as a function of stress voltage. (a) Before FN-tunneling, stress Vg = 1.2 ~ 1.6V (b) After FN-tunneling, stress Vg = 1.6 ~ 2.0V…..……….………113
Fig. 3-15 Distinct charge trapping behaviors in various time demarcation (short-time stress, up to 2 ms ) (a) Stress Vg = 1.2V (b) Stress Vg = 1.6…..…………..115
Fig. 3-16 Distinct charge trapping behaviors in various demarcation of stress time (long-time stress, up to 104 sec) (a) Threshold voltage shift in PBTI degradation (b) Fast trapping and slow trapping behaviors versus stress time…..……….………...116
Chapter 4 Charge De-trapping Behavior in High-κ Gate Dielectrics
Fig. 4-1 Linear relation between normalized saturation drain current degradation and threshold voltage shift (ΔVt) under various stress voltages…..……...…131
Fig. 4-2 Successful modeling fitting of charge de-trapping in HfO2/SiON gate stack under various stress voltages…..………...…..132
Fig. 4-4 A definition of fast de-trapping (t = 0 ~ 1.78 sec) and slow de-trapping (t = 1.78 ~ 100 sec) in our studies for the PBTI measurement with the conventional DC method…..……….…..134
Fig. 4-5 Analysis of fast de-trapping, slow de-trapping, and total de-trapping under various stress voltages (a) Based SiO2 = 0.8 nm (b) Based SiO2 = 1.4 nm………135
Fig. 4-6 Charge de-trapping behaviors in both based SiO2 = 0.8 nm and 1.4 nm under various stress voltages (a) Recovered Vt shift (related to recovered charges) (b) Non-recovered Vt shift (related to non-recovered charges) …..………136
Fig. 4-7 Charge de-trapping behaviors in both based SiO2 = 0.8 nm and 1.4 nm under various stress voltages (a) Recovery (%) (b) Fast/total de-trapping ratio. A fast/total de-trapping ratio is defined as (fast de-trapping)/(total de-trapping)
× 100 % in our studies] …..…………...………...……….…..137
Fig. 4-8 Analysis of fast de-trapping, slow de-trapping, and total de-trapping under various stress voltages (a) Based SiO2 = 0.8 nm (b) Based SiO2 = 1.4 nm…..………..138
Fig. 4-9 Analysis of fast de-trapping, slow de-trapping, and total de-trapping under various recovery voltages (a) Based SiO2 = 0.8 nm (b) Based SiO2 = 1.4 nm…..………...……….…..140
Fig. 4-10 Charge de-trapping behaviors in both based SiO2 = 0.8 nm and 1.4 nm under
charges) …..………..…….…..141
Fig. 4-11 Recovery (%) in both based SiO2 = 0.8 nm and 1.4 nm under various recovery voltages. [Recovery (%) is defined as (total de-trapping)/(total trapping) × 100 % in our studies] …..………...…...….…..142
Fig. 4-12 (a) Fast/total de-trapping ratio under various recovery voltages. (b) Fast/total trapping ratio under various stress voltages illustrated in Fig. 3-9(a).
[Fast/total de-trapping ratio is defined as (fast de-trapping)/(total trapping) × 100 % in our studies] …..………..……..143
Fig. 4-13 Band diagram of charge de-trapping under various recovery Vr conditions. (a) Recovery Vr = 0V (b) Recovery Vr = -0.5V (c) Recovery Vr = -1.6V…..……….……….144
Fig. 4-14 A schematic illustration of available de-trapping shallow traps under recovery condition of Vr = 0V…..……….…..145
Fig. 4-15 The comparisons of charge de-trapping between based SiO2 = 0.8 nm and 1.4 nm under various recovery voltages. [Charge de-trapping ratio is defined as (Charge de-trapping in IL = 1.4 nm)/(Charge de-trapping in IL = 0.8 nm) in our studies] …..……….………..146