Asynchronous Two-Level FIFO Buffer Architecture

There are major problems in having various synchronous on-chip communications, including ,odularity and design reuse, electromagnetic interference (EMI), worst case performance, clock power consumption and Clock skew [4.31]. Asynchronous NoC platforms are proposed for globally-asynchronous locally-synchronous (GALS) systems to achieve energy efficiency, quality-of-service and clock de-skewing

[4.32]-[4.34]. In GALS systems, data synchronization and communication across different clock domains are extremely challenging. An alternative solution is provided by GALS interface and an asynchronous network [4.35]-[4.38].

Fig. 4.14 Asynchronous two-level FIFO buffer architecture.

The two-level FIFO buffer is also employed for an asynchronous router, and the behavior of the asynchronous two-level FIFO buffer is similar to that of the synchronous two-level FIFO buffer. Fig. 4.14 shows the architecture of the asynchronous two-level FIFO buffer. However, the main difference between the synchronous and asynchronous two-level FIFO buffers is that the synchronous two-level FIFO has a multiple access mechanism. In terms of the different frequencies of each local clock domain, the arrival times of data from different input channels cannot be predicted. Thus, the asynchronous two-level FIFO buffer must be time-insensitive. Therefore, implementing the level-2 FIFO with multiple access

mechanism is unnecessary. Additionally, the asynchronous two-level FIFO buffer requires a read arbiter and write arbiter to control read and write access, respectively.

Communications in the two-level FIFO architecture are asynchronous between the distributed level-1FIFOs and centralized level-2 FIFO via a four-phase handshaking protocol. Since the depth of the distributed level-1 FIFOs are shallow, these FIFOs are implemented as asynchronous FIFOs for input and output channels. These FIFOs are implemented by the Bus-In Bus-Out structure to provide low latency and high throughput FIFO cells. The read/write order depends on the token in circular FIFO cells. Further, the distributed level-1 FIFOs connect GALS wrappers and the asynchronous two-level FIFO buffer.

When input data is stored in a distributed level-1 FIFO, the header decoder decodes the header and passes the request to the corresponding output channel. The arbiter of each output channel arbitrates the requests from different input channels and creates the link between the granted distributed level-1 FIFO and the data-link scheduler. Therefore, the data-link scheduler transmits the granted data to the centralized level-2 FIFO or the output distributed level-1 FIFO depending on the buffering condition in the output channel. If no data exist in the centralized level-2 FIFO for this output channel and the distributed level-1 FIFO is not full, data are transmitted to the distributed level-1 FIFO. Restated, if the distributed level-1 FIFO is full or the centralized level-2FIFO for this output channel is not empty, the data are delivered to the centralized level-2 FIFO. For single access of the centralized level-2 FIFO, the data-link scheduler also requires a read arbiter and write arbiter to arbitrate congestion on the read and write ports.

The arbitration circuitry must deal with concurrent and even simultaneous requests, and should not grant access to more than one sender at any time. Furthermore, to

avoid confusion, the grant signal must be free of hazards and not be in other meta-stable states. The arbitration for the four-request asynchronous architecture can be performed using a MUTEX-based scheme, which is called MUTEX-NET [4.33].

When four requests arrive from different senders, the MUTEX-NET guarantees that the first request and last request are granted in their original order, but the other two requests may not retain their order.

Fig. 4.15 Data-link scheduler and centralized level-2 FIFO for asynchronous two-level FIFO buffer.

Fig. 4.15 shows the details of the data-link scheduler and centralized level-2 FIFO for the asynchronous two-level FIFO buffer. The write and read arbiters determine access permission of the centralized level-2 FIFO for different output channels when more than two output channels issue requests. The R/W-enable controller produces R/W-enabled signals for the centralized level-2 FIFO based on read_req and write_req, which are requests from the read port and write port, respectively. Because the write generator must identify the written word for the next transaction according to the

occupied condition of the centralized level-2 FIFO, the read pulse and write pulse must be separated. That is, the centralized level-2 FIFO cannot be read and written simultaneously. Therefore, the R/W-enabled arbiter permits the reading operation or writing operation by a MUTEX-based arbiter. Furthermore, in an asynchronous two-level FIFO buffer, implementation of the write generator is similar to that of a synchronous two-level FIFO buffer without multiple slides. Moreover, the pulse generator generates the read pulse and write pulse for the read and write operations.

Fig. 4.16 STG specification for the read operation and write operation of the centralized level-2 FIFO.

Fig. 4.16 shows the signal transition graph (STG) specifications for read and write operations. The STG specifications show the four-phase handshakingprotocol for the centralized level-2 FIFO buffer. For a read operation, while r_req is asserted, the R/W-enables arbiter will assert r_enable when w_req is not asserted. The pulse generator then generates a pulse (r_pulse) to read data and reading control signals for the next reading transaction. Depending on the falling edge of a pulse, the 4_handshalking circuitry will activate r_ack to acknowledge the signal for the distributed level-1 FIFO to de-assert the request. Additionally, the acknowledge signal is pulled down by the falling request. The handshaking of the write operation is the same as that of the read operation.