XOR-based Conditional Keeper for Match-Line

floating

Fig. 6.7 AND-type match-line with XOR-based conditional keeper.

Table 6.1 Control organism of XOR-based conditional keeper.

Clock Floating Node Control Signal on gate of keeper

Low Low Low, to speed up the process of pre-charge Low High High, to avoid the impact on performance at the

very beginning of evaluation High Low High, keeper should be off

High High Low, keeper should be activated to enhance the capability of noise immunity

The AND-type match-line includes high fan-in circuits. However, conventional keepers perform more poorly in terms of propagation delay and power consumption.

The main idea of the proposed XOR-based conditional keeper is to ensure that the keeper does not turn on in the dynamic circuit at the beginning of the evaluation phase.

Fig. 6.7 and Table 6.1 present the new control signals and their corresponding keeper states. When the match-line pre-charge signal and the floating node are both low, the TCAM circuit is at the beginning of the pre-charge period and the conditional keeper should be turned on to accelerate the pre-charge procedure. When the match-line

pre-charge signal is low and the floating node is high, the pre-charge process is complete and the gate is ready to be evaluated. Therefore, the conditional keeper should be turned off to prevent any impact on the delay and any unnecessary power consumption. When the match-line pre-charge signal and floating node are both high, the match-line is either at the beginning of the evaluation process or stores state HIGH in the floating node at the end of the evaluation process. If it is at the beginning of the evaluation process, the floating node will eventually be at the appropriate voltage as long as the delay of the XOR gate exceeds the propagation delay of the dynamic circuits. Since the delay time of the dynamic circuits is shorter than that of the XOR gate, the conditional keeper is slightly turned on at the beginning of the evaluation process and is fully turned on or off as determined by the final value that is stored in the floating node. When the match-line pre-charge signal is high and the floating node is low, the evaluation mode has been completed and the final value stored in the floating node is low. Consequently, the conditional keeper should be fully turned off.

An XOR gate is required to generate the desired control signals.

(a) (b)

Fig. 6.8 (a) Search time (b) Power consumption versus UNG margin for different keepers.

Four different types of 8-bit AND-type match-line schemes are adopted for the performance comparison. The first one is match-line scheme with conventional keeper, depicted as Fig. 6.4. The second one uses weak keeper to match-line scheme. The third one is

match-line scheme with the twin transistors technique. The fourth one is the proposed AND-type match-lines scheme with XOR-based conditional keeper. During the noise tolerance comparison, what we concern about is not the actual size of the keeper device or actual size of twin transistors but the ability to resist noises. This ability is testified by the widely used Unity Noise Gain (UNG) margin [6.29]. Fig. 6.8(a) and Fig. 6.8(b), present the search time and power consumption versus unity noise gain margin for four types of AND-type match-line, respectively. For example, when UNG is at 810mV, 19.2% search time reduction and 3.5% power saving compared to conventional keeper up-sizing are achieved by using XOR-based conditional keeper. Based on the same condition, compared to weak keeper, 27.1% search time reduction and 8.9% power saving are realized with XOR-based keeper.

Even though the twin transistors technique is suitable for deep fan-in dynamic circuits, the performance is worse than XOR-based keeper. According to the simulation results, 16.3%

search time growth and 8.9% power consumption increase are achieved compared to XOR-based keeper when UNG is at 810mV. However, the area overhead with XOR-based keeper is 1.8% and 1.0% compared to conventional keeper and weak keeper, respectively.

The noise-tolerant energy-efficient match-line employs the co-design of the architecture and the circuit. Based on the butterfly connection, the inverters behind the XOR-based conditional keepers and the AND gate can together be represented an NOR gate, as presented in Fig. 6.9. Therefore, to reduce the search time overhead caused by the butterfly connection, the XOR-based conditional keeper approach can be used to reduce the delay associated with the critical path of the match-line. Clearly, the increase in the propagation delay of a TCAM segment by the XOR-based conditional keeper is small. Furthermore, the gate delay of a NOR gate is shorter than that of an AND gate. Accordingly, the proposed butterfly match-line scheme with a XOR-based conditional keeper exhibits high performance, because of the high degree

of parallelism. It also saves power by using an XOR-based conditional keeper and turning off the mismatched segments. This match-line also simultaneously reduces the search time and power consumption. Moreover, it is resilient against noise effectively.

Segment 1

(Matching Information from the last stage)