Chapter 3 Hierarchical Power Delivery System and Area-Efficient Power TSV
3.5 Summary
For the TSV 3D-IC applications, a hierarchical power delivery system is proposed to decouple the global and local power networks. The decoupled power delivery structure can greatly reduce the size of decoupling capacitor especially on the global power network. Moreover, the operating supply voltages can be chosen for different parts of the system to have the best trade-off between cost, power, and performance. Such a hierarchical power delivery system is believed to be very useful for heterogeneous integration in 3D-IC chips.
In order to reduce the area occupied by power TSV matrix and reserve the routable chip area, an area-efficient power TSV planning is also proposed. Based on the TSV planning, an appropriate TSV diameter and TSV count can be chosen to deliver a reliable power supply and minimize the area occupied by power TSV matrix
at meanwhile.
Additionally, a noise suppression technique for TSV 3D integration is proposed to reduce the supply noise by the latch-based active DECAPs. Based on UMC 65nm CMOS technology, the proposed scheme can realize maximum 7.4dB supply noise reduction and 12X boost fact at the resonant frequency. Therefore, the proposed noise suppression circuit can provide a stable power for the power integrity in TSV 3D integration.
Chapter 4
Intra-Layer Power Delivery Network and Voltage Regulation Analysis
An on-chip wide bandwidth linear voltage with adaptive biasing technique is presented in this chapter. This adaptively biased regulator enhances transient response by increasing the bias current in heavy load, while keeps low quiescent current to maintain high current efficiency in light load. To further exploit the voltage fluctuations in entire planar system, power delivery network analyses considering the placement of voltage regulator modules and the size of power line width and pitch are also introduced in this chapter.
4.1 Review of Low Dropout Voltage Regulator
Reliable power supply voltage is essential for the integration of system on a chip (SoC) and 3D applications. Since low dropout (LDO) voltage regulators occupied small chip area and produced accuracy voltage conversion, they are widely used in on-chip voltage regulation. Fig. 4.1 shows a conventional linear regulator. It is composed of an error amplifier, an analog voltage buffer, and large power transistors as output device. The voltage VOUT is determined by resistor divider and reference voltage VREF. An error amplifier in feedback loop compares the feedback voltage VFB
with VREF and appropriately adjusts the gate voltage of output device. However, large parasitic capacitance at the gate of a power transistor degrades the slew rate of an
error amplifier. The transient response is therefore limited by the bandwidth and the internal slew rate of the LDO regulators. Since the bandwidth is proportional to the bias current of error amplifier, a simple solution to improve transient performance is increasing bias current. However, a trade-off exists between the bandwidth and current efficiency. Hence, adaptively biased regulators are proposed to provide fast transient response and high current efficiency at the same time [4.1], [4.2].
Additionally, several techniques are also presented for improving transient response to maintain a reliable supply voltage [4.3]-[4.8].
Fig. 4.1. Conventional analog style linear regulator [4.5].
Replica controlled circuit is also an useful technique to enhance transient speed [4.9]-[4.11]. Since there is no large loading connected to the replica circuit, less stability issues will be involved. One can use wider loop bandwidth to achieve fast tracking speed. The local feedback technique is also applied to the load regulation.
With much small non-dominant poles than conventional single pole approaches, the load regulation loop exhibits fast transient response when the loading is disturbance.
However, using replica circuit controlled makes an inaccurate regulation due to the feedback node is not a real output.
In rent years, the research of digital controlled voltage regulators are emerging [4.12], [4.13]. They replace the analog blocks with their counterparts. Therefore,
digital regulators have larger immunity against PVT variations than traditional analog regulators. The digital circuit is also easy to migrate from one technology to another.
However, discontinuous output voltage and large amount of capacitance needed are the drawbacks of digital regulators.
On the other hand, low-noise regulator design is a critical issue for sensitive analog/RF circuits. In order to effectively decouple the supply noise from VDD to VOUT for PSR improvement, a regulator using feedforward amplifier to cancel the noise propagated from voltage supply is proposed in [4.14].
4.2 Wide Bandwidth Variable Output Voltage Regulator
System heterogeneity offered by 3D integration has exacerbated the requirement for multiple, wide range, and well controlled power supplies. In view of these, a wide bandwidth variable output voltage regulator is designed.
The voltage regulator using an adaptive biasing circuit to enhance transient response by increasing the bias current in heavy load, while keeps low quiescent current to maintain high current efficiency in light load. In order to provide variable output voltage, a resistor-string voltage divider also used. In the following, we describe the details of the adaptive biasing netwok, resistor-string voltage divider, and stability analysis of the proposed regulator.
4.2.1 Variable Output Voltage Regulator with Adaptively
Biasing Technique
Current Mirror Vref
VOUT
Fig. 4.2. The concept of adaptively biased regulator.
The concept of adaptive biasing technique is illustrated in Fig. 4.2. Different from most of regulators, which are biased with fixed bias current, the adaptive biasing circuit feeds an extra bias current to an error amplifier through a simple current mirror.
By adjusting the bias current to be proportional to the current load, the bandwidth of the regulator is improved. A large additional bias current results in fast transient response in heavy load, whereas a small additional bias current keeps efficient conversion in light load.
Bias opamp Adaptive biasing
Vfb Vref Vfb
Fig. 4.3. Schematic of adaptively biased regulator.
Fig. 4.3 shows the detailed schematic of adaptively biased regulator. It is composed of a bias current generator, a two-stage error amplifier (EA), an adaptive biasing network, an output voltage device, and a voltage divider. The voltage V is
determined by voltage divider and reference voltage VREF. An EA in feedback loop compares the feedback voltage Vfb with VREF and appropriately adjusts the gate voltage of output device. When the feedback voltage Vfb is lower than the reference voltage VREF, the EA decreases the gate voltage of output device. The small gate voltage of power transistor leads to a large number of current recovering VOUT to the nominal voltage.
The output resistance should be infinity of an ideal bias circuit to makes bias current stable at nominal value under process, voltage, and temperature variations.
Therefore, cascode current mirror was chosen for generating a fixed bias current to EA due to large output resistance.
High-precision regulation requires high loop gain amplifier. A high gain EA can be realized by multi-stage or folded cascode amplifier scheme. In low-voltage operation, cascode type EA does not guarentee all the transistors operating in saturation region. To achieve high gain, two-stage EA is used in this design. The EA, which is modified from [4.2], consists of M0 to M8. The Miller capacitor Cf is connected between the output node of the regulator and the output node of the differential stage. As the gain from differential stage to VOUT is large, pole splitting is effective.
The adaptive biasing network is implemented with two current mirror pairs (MP, MS), and (Mab1, Mab2). The sensing transistor Ms senses the gate voltage of the power transistors and changes its drain current according to the current load. The sensing current therefore conducted to Mab2 and mirrored a small additional bias current to Mab1. The magnitude of additional bias current is depending on the width ratio of power transistor and sensing transistor. However, the drain-to-source voltage of sensing transistor is higher than power transistor (V > V ). The sensing current
has enlarged over the nominal aspect ratio. Hence, the sensing transistor should be smaller in the actual design when considering the cannel length modulation.
The reference voltage VREF, which is 0.6V, is assumed from a bandgap reference circuit. In order to produce variable output voltage without using multiple bandgap reference, a resistor-string voltage divider is necessary to diviede each desired regulated voltage to 0.6V. Fig. 4.4 depicts the resistive voltage divider. It takes VOUT as input and provides three divides voltages with different dividing ratios. Only one at a time will be passed to Vfb by the switch. For example, when demanding a 0.9V regulated voltage, the decorder block will activate the first switch. A 6/9 ratio will divide 0.9V to 0.6V that is able to be compared with VREF.
VOUT
Decoder
Control Signal 6/7 VOUT
6/8 VOUT
6/9 VOUT
Vfb
Fig. 4.4. Resistor-string voltage divider.
4.2.2 Stability Analysis
A typical structure of a low-dropout regulator shows in Fig. 4.5. which consists of an error amplifier comparing the output voltage to the reference voltage Vref, a PMOS pass transistor Mp, and the output buffer stage driving Mp. There are three different poles in the voltage regulator structure located at the output node of the error
amplifier (N1), the output node of the buffer (N2), and the output node of the voltage regulator (Vout). In particular, these poles are given by
(4.1) (4.2)
(4.3)
Error Amp
Vin
Buffer
C
ibr
obN1 N2
V
REFR1
R2 C
LR
LOUT
Fig. 4.5. Typical structure of a low-dropout regulator with an intermediate buffer stage [4.4].
The ro1 is the output resistance of the error amplifier, C1 is the equivalent capacitance at N1 which is dominated by the input capacitance of the buffer Cib, rob, is the output resistance of the buffer, Cp is the input capacitance of Mp, and roeq is the equivalent resistance seen at the output of the voltage regulator. Ideally, both Cib and rob should be very small in order to achieve single-pole loop response by locating both p1 and p2 at frequencies much higher than the unity-gain frequency of the regulation loop.
In order to construct the required output buffer stage, a simple PMOS source-follower is first considered for implementing the output buffer and its structure is shown in Fig. 4.6. The PMOS source-follower provides near complete shutdown of
the pass device when under the light-load conditions. Because of the output resistance rob of the source-follower is given by 1/gm21, it is necessary to increase gm21 in order to decrease the value of rob and allow p2 to be located at frequencies much higher than the unity-gain frequency of the regulation loop. Transconductance gm21 can only be increased either through using a larger W/L ratio of transistor M21, or through increasing the DC biasing current I21 through M21, or both. However, increasing I21
would increase the total quiescent current of the regulator, and the current efficiency of the voltage regulator is degraded. Using a larger W/L ratio of M21 would increase the input capacitance Cib of the buffer, which is in turn pushes p1 to a lower frequency and the stability would be poorly affected. A simple PMOS source-follower need to design carefully.
Vin
C
ibr
obN1 N2
P1
I
21P2 M
PFig. 4.6. Source-follower implementation of the intermediate buffer stage [4.4].
The stability of LDO based on dominant-pole compensation with pole-zero cancellation as shown in Fig. 4.7. The second pole p2 is cancelled by the zero z1
created by the ESR of the output capacitor. With a large output capacitance, the LDO stability is achieved by locating p3 beyond the unity-gain frequency of the loop gain for providing sufficient phase margin. However, when loop gain is too high, p3 locates before the unity-gain frequency, and an even larger output capacitance is required to
retain LDO stability.
Moreover, the power PMOS transistor in the classical LDO must operate in saturation region for considering the stability problem at different input voltages. The change of the voltage gain due to different drain–source voltage is not substantial when the transistor operates in saturation region. However, if the transistor operates in linear region at dropout, the transistor will operate in saturation region instead as the input voltage increases. As mentioned before, when the loop gain increases, the classical LDO based on dominant-pole compensation may be unstable. Hence, the power PMOS transistor needs to operate in saturation region throughout the entire range of input voltage, so a large transistor size is required for providing a small saturation voltage at the maximum output current.
Freq.
P
3Z
1P
2P
120log|L(jw)|
0dB
pole from output capacitor
pole from error amplifier output
higher loop gain
zero from ESR
pole from buffer output
Fig. 4.7. Frequency response of classical LDO.
4.2.3 Simulation Results
The simulation of the wide bandwidth variable output voltage regulator uses a UMC 65nm standard CMOS technology. Only normal threshold voltage devices are used. The input voltage is 1.0V with a 0.1nF decoupling capacitor. The output voltage is regulated to 0.7V, 0.8V, 0.9V according to the control signal of voltage divider. The design parameters are shown in Table 4.1. Maximum output current load is 200mA.
The Cf, CC, and RC act as frequency compensator. The aspect ratio of sensing transistor and output device is set 3.2μm: 4000μm. Although the factor is only 1/1250 in design stage, it increases to 1/300 after considering channel length modulation.
Table 4.1. Design parameters of regulator
Technology UMC 65nm
VIN 0.95V – 1.5V
VOUT 0.7V – 0.9V
VREF 0.6V
ILOAD 1mA – 200mA
CL 100pF
Cf, CC, RC 3.5pF, 0.4pF, 2.0kΩ
R1, R2 10kΩ, 20kΩ
Ms:Mp 3.2μm : 4000μm
Output mode changing is shown in Fig. 4.8. The minimum error is 1mV at 0.7V output state whereas the maximum error is 2mV at 0.9V output state. The error comes from the limited EA loop gain. The output state changes from 0.8V to 0.9V within 70ns. For simplicity, only the 0.9V output simulation results are presented in the
following. The stable state output voltage under different process and temperature conditions are shown in Fig. 4.9. The maximum voltage error is less than 3mV in the temperature range from -40℃ to 125 ℃.
Output voltage (mV)
900
800
700
1μs 2μs 3μs 4μs 5μs
Fig. 4.8. Simulation waveform of output state changing.
0.896 0.897 0.898 0.899 0.9 0.901 0.902 0.903
-40 -20 0 20 40 60 80 100 120
Temperature(℃)
Vout(V)
FF corner TT corner SS corner
ILOAD = 100 mA
Fig. 4.9. 0.9V output under different process and temperature conditions
High bandwidth is guaranteed to have excellent performance in line/load transient. Without adaptive biasing technique, high bandwidth can only be achieved by using a large quiescent current. In this work, an adaptively biased regulator is designed to extend bandwidth in heavy load operation whereas keep low quiescent current in light load. The bandwidth improvement with adaptive current biasing is
shown in Fig. 4.10. This adaptive biasing technique increases the unit gain frequency from 6MHz to 15.3MHz over 200mA current load range. The maximum improvement is 5.52X at 100mA current load.
Fig. 4.10. Unit gain frequency improvement of adaptive current biasing.
The current efficiency and quiescent current using adaptive biasing technique are shown in Fig. 4.11. The basic quiescent current is fixed at 60μA. With the increasing of output load from 1mA to 200mA, the adaptive biasing network feeds an additional bias current to EA. The quiescent current is therefore changed from 63μA to 741μA.
This adaptively biased regulator leads to 94.05% current efficiency at 1mA current load whereas 99.63% at 200mA current load.
0
Fig. 4.11. Current efficiency and quiescent current with adaptive biasing technique.
The simulated load step response of the regulated voltage is shown in Fig. 4.12.
A 10mA to 100mA current step with 100ps rising and falling time is used. The overshoot/undershoot voltage is 70mV/138mV. It recovers the voltage to regulated output within 140ns/80ns. The error voltage is 2mV and load regulation is 22.22μV/mA.
0.80 0.90 0.97
0.76
100
50
10
Output voltage (V) Load current (mA)
3μs 3.5μs 4.0μs 4.5μs
Fig. 4.12. Simulation waveform of load transient response.
The line step response of the regulated voltage is shown in Fig. 4.13. A 10%
voltage variation from 0.95V to 1.1V with 100ps rising and falling time is used. The overshoot/undershoot voltage is 112mV/108mV. It recovers the voltage to regulated output within 100ns/100ns. The error voltage is 0.43mV and line regulation is 2.86mV/V.
Output voltage (V)
0.8 0.9 1.0 1.1
3μs 4μs 5μs 6μs
Fig. 4.13. Simulation waveform of line transient response.
To ensure the stability of LDO, the frequency response analyses of light/heavy load operation are also required. Fig. 4.14 and Fig. 4.15 show the frequency responses when the regulator operates in light load (1mA) and heavy load (200mA), respectively.
The DC gain of the regulator is 56.9dB and 25.8dB, and the phase margin (PM) is 89°
and 79.26° in the light load and heavy load operation, respectively. Both the light load and heavy load operation, the regulator is stabilized with sufficient phase margin (PM>60°).
Fig. 4.14. Frequency response at light load operation.
Fig. 4.15. Frequency response at heavy load operation.
As shown in Fig. 4.16, due to the extended bandwidth, the regulator has high power supply rejection (PSR). The PSR is 56dB at 100KHz, and 40dB even at 1MHz.
It means that the output ripple is only 1% of supply ripple variation.
Fig. 4.16. Power supply rejection of the adaptively biased regulator.
The comparison of the adaptively biased regulator with previous works is shown in Table 4.2. Because of the smallest decoupling capacitor and not excessive quiescent current in our work, the adaptively biased regulator has the best figure of merit (FOM) in these researches.
Table 4.2. Comparison with previous works.
M. Al-Shyoukh, JSSC'07[4.4]
P. Hazucha, JSSC'07[4.5]
M. El-Nozahi,
JSSC‘10[4.14] This Work
Technology 0.35 μm 90 nm 130 nm 65 nm
Input Voltage 2.0V 2.4V 1.15V 1.0V
Output Voltage 1.8V 1.2V 1.0V 0.9V
Output droop ΔVOUT
54mV 120mV 10mV 129mV
Max. Current 200mA 1A 25mA 200mA
IQ (quiescent
current) 20μA 25.7mA 50μA 63μA @1mA
741μA @200mA Current Efficiency 99.80% 97.50% 99.80% 94.05% @1mA
99.63% @200mA
Decoupling Cap. 1000nF 2.4nF 4000nF 0.1nF
FOM [4.5]
(figure of merit) 27ps 7.4ps 3.2ns 239fs
4.3 Power/Ground Grid Construction
As technology advances towards Gigascale Integration (GSI), chips require higher current densities and lower supply voltages in their power distribution networks. The tolerable power supply noise of circuits, as a result, decreases and makes design of power distribution networks more challenging.
IR-drop and Simultaneous Switching Noise (SSN) are the two main components of power supply noise. IR-drop results from the supply current passing through the parasitic resistance of the power distribution network. SSN is caused by inductance of the power delivery system, and occurs when a group of circuits switch simultaneously.
Among three distinct droops of SSN, the first droop has the shortest duration and largest magnitude, thus it influences chip performance most severely [4.15].
In order to mitigate the on-chip voltage fluctuations, the optimum sizing of power grids for reducing IR-drop is proposed in [4.16]. As for SSN reduction, an interdigitated power/ground (P/G) networks where a few wide lines are replaced by a large number of narrow lines is often used to reduce the inductive effect [4.17]-[4.19].
The interdigitated structure is shown to achieve the greatest reduction in LdI/dt drop.
The brief introduction of aforementioned works and power grid modeling method are described in the following subsections.
4.3.1 Optimum Sizing of Power Grids for IR Drop
As IR drop is only concerned in [4.16], only the resistive nature of the power grid lines will be considered, and a constant DC current load will represent the average load current. The grid structure exhibits large symmetry around the origin.
The power grid now has a group of square-shaped concentric nodes. Grouping parallel resistors and current sources in Fig. 4.17(a) and Fig. 4.17(b), the corresponding reduced grid models in Fig. 4.17(c) and Fig. 4.17(d) are obtained.
This paper targeted the initial design of power grids [4.16]. It presented simple reduced models based on equipotential-nodes approximation, and simple yet accurate analytical optimum line width to uniform one formula to calculate the IR drop with error less than 0.1%. The models and the IR drop formula accurately captured the effects of the design parameters on IR drop. Thus, they have high fidelity in comparing different grid designs regarding the IR drop. This paper also derived the optimum sizing scheme of power grid lines for minimum IR drop at the grid center [4.16]. Using this technique, a uniform grid was optimum for uniform load current
This paper targeted the initial design of power grids [4.16]. It presented simple reduced models based on equipotential-nodes approximation, and simple yet accurate analytical optimum line width to uniform one formula to calculate the IR drop with error less than 0.1%. The models and the IR drop formula accurately captured the effects of the design parameters on IR drop. Thus, they have high fidelity in comparing different grid designs regarding the IR drop. This paper also derived the optimum sizing scheme of power grid lines for minimum IR drop at the grid center [4.16]. Using this technique, a uniform grid was optimum for uniform load current