Variable Output Voltage Regulator with Adaptively Biasing Technique 77

Current Mirror Vref

VOUT

Fig. 4.2. The concept of adaptively biased regulator.

The concept of adaptive biasing technique is illustrated in Fig. 4.2. Different from most of regulators, which are biased with fixed bias current, the adaptive biasing circuit feeds an extra bias current to an error amplifier through a simple current mirror.

By adjusting the bias current to be proportional to the current load, the bandwidth of the regulator is improved. A large additional bias current results in fast transient response in heavy load, whereas a small additional bias current keeps efficient conversion in light load.

Bias opamp Adaptive biasing

Vfb Vref Vfb

Fig. 4.3. Schematic of adaptively biased regulator.

Fig. 4.3 shows the detailed schematic of adaptively biased regulator. It is composed of a bias current generator, a two-stage error amplifier (EA), an adaptive biasing network, an output voltage device, and a voltage divider. The voltage V is

determined by voltage divider and reference voltage V_REF. An EA in feedback loop compares the feedback voltage Vfb with VREF and appropriately adjusts the gate voltage of output device. When the feedback voltage V_fb is lower than the reference voltage VREF, the EA decreases the gate voltage of output device. The small gate voltage of power transistor leads to a large number of current recovering V_OUT to the nominal voltage.

The output resistance should be infinity of an ideal bias circuit to makes bias current stable at nominal value under process, voltage, and temperature variations.

Therefore, cascode current mirror was chosen for generating a fixed bias current to EA due to large output resistance.

High-precision regulation requires high loop gain amplifier. A high gain EA can be realized by multi-stage or folded cascode amplifier scheme. In low-voltage operation, cascode type EA does not guarentee all the transistors operating in saturation region. To achieve high gain, two-stage EA is used in this design. The EA, which is modified from [4.2], consists of M₀ to M₈. The Miller capacitor C_f is connected between the output node of the regulator and the output node of the differential stage. As the gain from differential stage to V_OUT is large, pole splitting is effective.

The adaptive biasing network is implemented with two current mirror pairs (MP, M_S), and (M_ab1, M_ab2). The sensing transistor Ms senses the gate voltage of the power transistors and changes its drain current according to the current load. The sensing current therefore conducted to M_ab2 and mirrored a small additional bias current to Mab1. The magnitude of additional bias current is depending on the width ratio of power transistor and sensing transistor. However, the drain-to-source voltage of sensing transistor is higher than power transistor (V > V ). The sensing current

has enlarged over the nominal aspect ratio. Hence, the sensing transistor should be smaller in the actual design when considering the cannel length modulation.

The reference voltage VREF, which is 0.6V, is assumed from a bandgap reference circuit. In order to produce variable output voltage without using multiple bandgap reference, a resistor-string voltage divider is necessary to diviede each desired regulated voltage to 0.6V. Fig. 4.4 depicts the resistive voltage divider. It takes V_OUT as input and provides three divides voltages with different dividing ratios. Only one at a time will be passed to V_fb by the switch. For example, when demanding a 0.9V regulated voltage, the decorder block will activate the first switch. A 6/9 ratio will divide 0.9V to 0.6V that is able to be compared with V_REF.

VOUT

Decoder

Control Signal 6/7 VOUT

6/8 VOUT

6/9 VOUT

Vfb

Fig. 4.4. Resistor-string voltage divider.

4.2.2 Stability Analysis

A typical structure of a low-dropout regulator shows in Fig. 4.5. which consists of an error amplifier comparing the output voltage to the reference voltage V_ref, a PMOS pass transistor Mp, and the output buffer stage driving Mp. There are three different poles in the voltage regulator structure located at the output node of the error

amplifier (N1), the output node of the buffer (N2), and the output node of the voltage regulator (Vout). In particular, these poles are given by

(4.1) (4.2)

(4.3)

Error Amp

Vin

Buffer

C

_ib

r

ob

N1 N2

V

REF

R1

R2 C

L

R

_L

OUT

Fig. 4.5. Typical structure of a low-dropout regulator with an intermediate buffer stage [4.4].

The ro1 is the output resistance of the error amplifier, C1 is the equivalent capacitance at N1 which is dominated by the input capacitance of the buffer C_ib, r_ob, is the output resistance of the buffer, Cp is the input capacitance of Mp, and roeq is the equivalent resistance seen at the output of the voltage regulator. Ideally, both C_ib and rob should be very small in order to achieve single-pole loop response by locating both p1 and p2 at frequencies much higher than the unity-gain frequency of the regulation loop.

In order to construct the required output buffer stage, a simple PMOS source-follower is first considered for implementing the output buffer and its structure is shown in Fig. 4.6. The PMOS source-follower provides near complete shutdown of

the pass device when under the light-load conditions. Because of the output resistance rob of the source-follower is given by 1/gm21, it is necessary to increase gm21 in order to decrease the value of rob and allow p2 to be located at frequencies much higher than the unity-gain frequency of the regulation loop. Transconductance gm21 can only be increased either through using a larger W/L ratio of transistor M₂₁, or through increasing the DC biasing current I21 through M21, or both. However, increasing I21

would increase the total quiescent current of the regulator, and the current efficiency of the voltage regulator is degraded. Using a larger W/L ratio of M21 would increase the input capacitance C_ib of the buffer, which is in turn pushes p1 to a lower frequency and the stability would be poorly affected. A simple PMOS source-follower need to design carefully.

Vin

C

_ib

r

_ob

N1 N2

P1

I

₂₁

P2 ^M

^P

Fig. 4.6. Source-follower implementation of the intermediate buffer stage [4.4].

The stability of LDO based on dominant-pole compensation with pole-zero cancellation as shown in Fig. 4.7. The second pole p2 is cancelled by the zero z1

created by the ESR of the output capacitor. With a large output capacitance, the LDO stability is achieved by locating p3 beyond the unity-gain frequency of the loop gain for providing sufficient phase margin. However, when loop gain is too high, p3 locates before the unity-gain frequency, and an even larger output capacitance is required to

retain LDO stability.

Moreover, the power PMOS transistor in the classical LDO must operate in saturation region for considering the stability problem at different input voltages. The change of the voltage gain due to different drain–source voltage is not substantial when the transistor operates in saturation region. However, if the transistor operates in linear region at dropout, the transistor will operate in saturation region instead as the input voltage increases. As mentioned before, when the loop gain increases, the classical LDO based on dominant-pole compensation may be unstable. Hence, the power PMOS transistor needs to operate in saturation region throughout the entire range of input voltage, so a large transistor size is required for providing a small saturation voltage at the maximum output current.

Freq.

P

₃

Z

₁

P

₂

P

₁

20log|L(jw)|

0dB

pole from output capacitor

pole from error amplifier output

higher loop gain

zero from ESR

pole from buffer output

Fig. 4.7. Frequency response of classical LDO.

4.2.3 Simulation Results

The simulation of the wide bandwidth variable output voltage regulator uses a UMC 65nm standard CMOS technology. Only normal threshold voltage devices are used. The input voltage is 1.0V with a 0.1nF decoupling capacitor. The output voltage is regulated to 0.7V, 0.8V, 0.9V according to the control signal of voltage divider. The design parameters are shown in Table 4.1. Maximum output current load is 200mA.

The C_f, C_C, and R_C act as frequency compensator. The aspect ratio of sensing transistor and output device is set 3.2μm: 4000μm. Although the factor is only 1/1250 in design stage, it increases to 1/300 after considering channel length modulation.

Table 4.1. Design parameters of regulator

Technology UMC 65nm

V_IN 0.95V – 1.5V

V_OUT 0.7V – 0.9V

VREF 0.6V

ILOAD 1mA – 200mA

CL 100pF

C_f, CC, RC 3.5pF, 0.4pF, 2.0kΩ

R1, R2 10kΩ, 20kΩ

Ms:Mp 3.2μm : 4000μm

Output mode changing is shown in Fig. 4.8. The minimum error is 1mV at 0.7V output state whereas the maximum error is 2mV at 0.9V output state. The error comes from the limited EA loop gain. The output state changes from 0.8V to 0.9V within 70ns. For simplicity, only the 0.9V output simulation results are presented in the

following. The stable state output voltage under different process and temperature conditions are shown in Fig. 4.9. The maximum voltage error is less than 3mV in the temperature range from -40℃ to 125 ℃.

Output voltage (mV)

900

800

700

1μs 2μs 3μs 4μs 5μs

Fig. 4.8. Simulation waveform of output state changing.

0.896 0.897 0.898 0.899 0.9 0.901 0.902 0.903

-40 -20 0 20 40 60 80 100 120

Temperature(℃)

Vout(V)

FF corner TT corner SS corner

ILOAD = 100 mA

Fig. 4.9. 0.9V output under different process and temperature conditions

High bandwidth is guaranteed to have excellent performance in line/load transient. Without adaptive biasing technique, high bandwidth can only be achieved by using a large quiescent current. In this work, an adaptively biased regulator is designed to extend bandwidth in heavy load operation whereas keep low quiescent current in light load. The bandwidth improvement with adaptive current biasing is

shown in Fig. 4.10. This adaptive biasing technique increases the unit gain frequency from 6MHz to 15.3MHz over 200mA current load range. The maximum improvement is 5.52X at 100mA current load.

Fig. 4.10. Unit gain frequency improvement of adaptive current biasing.

The current efficiency and quiescent current using adaptive biasing technique are shown in Fig. 4.11. The basic quiescent current is fixed at 60μA. With the increasing of output load from 1mA to 200mA, the adaptive biasing network feeds an additional bias current to EA. The quiescent current is therefore changed from 63μA to 741μA.

This adaptively biased regulator leads to 94.05% current efficiency at 1mA current load whereas 99.63% at 200mA current load.

0

Fig. 4.11. Current efficiency and quiescent current with adaptive biasing technique.

The simulated load step response of the regulated voltage is shown in Fig. 4.12.

A 10mA to 100mA current step with 100ps rising and falling time is used. The overshoot/undershoot voltage is 70mV/138mV. It recovers the voltage to regulated output within 140ns/80ns. The error voltage is 2mV and load regulation is 22.22μV/mA.

0.80 0.90 0.97

0.76

100

50

10

Output voltage (V) Load current (mA)

3μs 3.5μs 4.0μs 4.5μs

Fig. 4.12. Simulation waveform of load transient response.

The line step response of the regulated voltage is shown in Fig. 4.13. A 10%

voltage variation from 0.95V to 1.1V with 100ps rising and falling time is used. The overshoot/undershoot voltage is 112mV/108mV. It recovers the voltage to regulated output within 100ns/100ns. The error voltage is 0.43mV and line regulation is 2.86mV/V.

Output voltage (V)

0.8 0.9 1.0 1.1

3μs 4μs 5μs 6μs

Fig. 4.13. Simulation waveform of line transient response.

To ensure the stability of LDO, the frequency response analyses of light/heavy load operation are also required. Fig. 4.14 and Fig. 4.15 show the frequency responses when the regulator operates in light load (1mA) and heavy load (200mA), respectively.

The DC gain of the regulator is 56.9dB and 25.8dB, and the phase margin (PM) is 89°

and 79.26° in the light load and heavy load operation, respectively. Both the light load and heavy load operation, the regulator is stabilized with sufficient phase margin (PM>60°).

Fig. 4.14. Frequency response at light load operation.

Fig. 4.15. Frequency response at heavy load operation.

As shown in Fig. 4.16, due to the extended bandwidth, the regulator has high power supply rejection (PSR). The PSR is 56dB at 100KHz, and 40dB even at 1MHz.

It means that the output ripple is only 1% of supply ripple variation.

Fig. 4.16. Power supply rejection of the adaptively biased regulator.

The comparison of the adaptively biased regulator with previous works is shown in Table 4.2. Because of the smallest decoupling capacitor and not excessive quiescent current in our work, the adaptively biased regulator has the best figure of merit (FOM) in these researches.

Table 4.2. Comparison with previous works.

M. Al-Shyoukh, JSSC'07[4.4]

P. Hazucha, JSSC'07[4.5]

M. El-Nozahi,

JSSC‘10[4.14] This Work

Technology 0.35 μm 90 nm 130 nm 65 nm

Input Voltage 2.0V 2.4V 1.15V 1.0V

Output Voltage 1.8V 1.2V 1.0V 0.9V

Output droop ΔVOUT

54mV 120mV 10mV 129mV

Max. Current 200mA 1A 25mA 200mA

IQ (quiescent

current) 20μA 25.7mA 50μA 63μA @1mA

741μA @200mA Current Efficiency 99.80% 97.50% 99.80% 94.05% @1mA

99.63% @200mA

Decoupling Cap. 1000nF 2.4nF 4000nF 0.1nF

FOM [4.5]

(figure of merit) 27ps 7.4ps 3.2ns 239fs

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