Calibration Circuits

Fig. 4-11 (a) shows the block diagram of calibration circuits. It contains two replica stages, a calibration comparator with offset calibration, and a digital loop filter.

As described in 3.4.3, because of incomplete-settling technique, there is sampling attenuation between stages. Sampling attenuation can be compensated:

( )⋅ =2

eff s y

G t G (4.8) From (4.8), G_eff( )t is _s 2

Gy . Because sampling attenuation happens between stages, if only the first replica stage with residue plot shown in Fig. 4-11 (b) is applied, a known analog input V_{in known_} set 0 with D_{1_replica1} set 0 and D_{1_replica2} set -1 is given,

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and an analog value set 2 Vref

which corresponds to V_{in known_} is compared with the residue output Vout replica_{_ 1}( )ts of the first replica stage at t_s, assuming that the

comparator is calibrated and has no offset, from (4.1):

_ 1( ) ( )( _ 1_ 1 2 _ 1 )

out replica s eff s in known replica replica

ref

Gy . In other words, sampling attenuation cannot be compensated. If the second replica stage with residue plot shown in Fig. 4-11 (c) is added with D_{1_replica2}

set 0 and D_{2 _replica2} set 1, and replica stage at t_s, assuming that the comparator is calibrated and has no offset, from

(4.1) and (4.9):

out replica s eff s in replica replica replica

ref ref

eff s y out replica s replica replica

eff s y eff indeed partially compensates sampling attenuation. As described in 4.2.2,

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dt of neighboring binary digital control bits

5, , , , , 4 3 2 1 0 To deserve to be mentioned,

2 Vref

used for calibration is generated in chip by a resistor-ladder which corresponds to 6-bit matching.

_ 0

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The Second Replica Stage Calibration Point

(c)

Fig. 4-11 (a) block diagram of calibration circuits (b) residue plot of the first replica stage (c) residue plot of the second replica stage

Besides, offset of opamp of the replica stages will cause error when G_eff( )t_s is

determined. Assuming that offset of opamp of the fisrt and second replica stages is

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1

Vos and V_os2, respectively, the residue output Vout replica_{_ 1}( )t of the first replica stage s

at t_s without considering sampling attenuation and offset of the calibration

comparator:

out replica s eff s in replica replica replica os

ref

out replica s eff s in replica replica replica os

ref ref

eff s out replica replica replica os

eff s eff error. Input-offset-storage (IOS) technique [18] is used to suppress the effect of offset of opamp of the replica stages. Fig. 4-12 (a) and (b) shows that input-offset-storage (IOS) technique is used in sampling phase and amplification phase, respectively. The output offset voltage of the outputs of opamp due to offset V_os is reduced to

0

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Fig. 4-12 IOS technique is used (a) in sampling phase (b) in amplification phase

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If offset of the calibration comparator after offset calibration is V_{os cal_} , from

(4.13), equivalently, Vout replica_{_ 2}( )ts is compared with ( 125 ) _{_} 2

ref

os cal

V = mV +V .

Assuming that sampling attenuation, V_os1, and V_os2 are not taken into consideration,

_ os cal

V with maximum ( 1.5 )

±V5^LSB = ±

mV let G_eff( )t_s deviate from 2 by ±0.008 which is small enough refer to Fig. 3-8.

The circuit implementation of the calibration comparator with offset calibration is shown in Fig. 4-13. There are four binary-weighted current controlled by digital control bits , , , y₃ y₂ y₁ y₀ and z₃, , , z₂ z₁ z₀ at each side of the calibration

comparator to compensate offset of the calibration comparator before offset calibration.

φ1pb

φ1pb φ1pb

Vi₊ V_i−

Do₊

Do₋

y3 y₂ y₁ y₀

z3

z2

z1

z0

Fig. 4-13 circuit implementation of calibration comparator with offset calibration

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Input-referred offset of the calibration comparator before offset calibration is

±17 mV ( 3σ ) in post-simulation. Fig. 4-14 shows embedded calibration offset v.s.

3 0

y ... y (or z ... z_{3 0} ) in decimal expression in post-simulation. Maximum

embedded calibration offset is ±17.9 mV with maximum 1.5 mV step.

0 2 4 6 8 10 12 14 16 18 20

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

embedded calibration offset

3, , , 2 1 0 ( , , , )3 2 1 0

y y y y or z z z z

Fig. 4-14 embedded calibration offset v.s. y ... y_{3 0} (or z ... z_{3 0})

Fig. 4-15 (a) shows the block diagram of the digital loop filter. It contains two cascaded sub-filter and back-end digital circuits. The function of the digital loop filter is to eliminate the disturbance of noise.

The first sub-filter shown in Fig. 4-15 (b) is composed of a front-end D flip-flop (DFF), two DFF chains, and two reset DFF. Each DFF chain has 5 DFF. The front-end DFF captures the comparison result of the calibration comparator. If the comparison

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result is 1, the up DFF chain shifts 1 right and reset the down DFF chain, and vice versa. Once 1 is shifted to the most right of either the up or down DFF chain, both them are reset. For example, the outputs , , , , M_{4 _up} M_{3_up} M_{2 _up} M_{1_up} U_{p_1} of the up DFF chain are 11000 and the outputs , , , , M_{4 _dn} M_{3 _dn} M_{2 _dn} M_{1_dn} D_{n_1} of the

down DFF chain are 00000 at this moment. If next comparison result is 1,

4 __up ... _p_1

M U is 11100, and M_{4 _dn} ... D_{n_1} is 00000. And if next comparison result is 0, M_{4 _up} ... U_{p_1} is 00000, and M_{4 _dn} ... D_{n_1} is 10000. Only that five consecutive 1 of the comparison result appears, U_{p_1} becomes 1, and vice versa.

The second sub-filter shown in Fig. 4-15 (c) is composed of a reset DFF and two DFF chains. Each DFF chain has 5 DFF. Before the beginning of sampling-point calibration, DFF of the DFF chains is reset by init. Then sampling-point calibration starts. The clock of the DFF chains is triggered by trig which becomes 1 when either U_{p_1} or D_{n_1} becomes 1. When U_{p_1} becomes 1, the up DFF chain shifts 1

right, and the down DFF chain shifts 0 left, and vice versa. Once 1 is shifted to the most right of either the up or down DFF chain, both them are reset. For example, the outputs N_{4 _up}, , , , N_{3 _up} N_{2 _up} N_{1_up} U_{p_ 2} of the up DFF chain are 11100 and the outputs N_{4 _dn}, , , , N_{3 _dn} N_{2 _dn} N_{1_dn} D_{n_ 2} of the down DFF chain are 10000 at this moment. If U_{p_1} becomes 1, N_{4 _up} ... U_{p_ 2} is 11110, and N_{4 _dn} ... D_{n_ 2} is 00000.

And if D_{n_1} becomes 1, N_{4 _up} ... U_{p_ 2} is 11000, and N_{4 _dn} ... D_{n_ 2} is 11000.

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Only that the accumulation of the number of times of 1 of U_{p_1} larger than that of

_1

Dn is five, U_{p_ 2} becomes 1, and vice versa.

The back-end digital circuits comprise the registers, a adder, and a subtracter. As described in 4.2.3, the registers is used to store current binary digital control bits

5, , , , , 4 3 2 1 0

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Fig. 4-15 block diagram of (a) digital loop filter (b) the first sub-filter (c) the second sub-filter