一個使用不完全趨穩技巧伴隨著背景調整取樣時間校正的高速導管式類比數位轉換器

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致謝

本論文的完成，首先要感謝我的指導教授陳信樹博士，除了學術上的指引，

更教導了作研究的態度及處事的方法，使我獲益良多。再者要感謝林宗賢教授和郭建宏教授，撥冗來擔任我的口試委員，並提供了寶貴的意見，讓本論文能夠更加完整。

特別感謝千鑑學長的指導與貢獻，也感謝鈞維和亞珊的幫忙，讓本論文能夠順利完成。感謝菁華、泓霖、依峻、宏彥和嘉南，和你們請教和討論的過程中，

使我電路設計的基礎更加穩固。另外感謝博仰、承學、崇銘、耀升和宗翰，和你們教學相長的過程中，也使我電路設計的觀念更加清晰。

最後感謝父母的支持，讓我三年來能夠毫無後顧之憂地完成本論文。

賴傑帆 2012/08/15 博理館 415 室

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I

摘要

本論文採用了不完全趨穩的技巧，提出了背景調整取樣時間校正來實現一個六位元、每秒十億次取樣的導管式類比數位轉換器。不完全趨穩的技巧伴隨著背景調整取樣時間校正能夠降低類比數位轉換器中運算放大器對於增益和頻寬的需求從而降低運算放大器的功率消耗。

本晶片使用台積電 65nm CMOS 一般製程製作。根據量測結果，在 1 GS/s 的轉換率下的 DNL 和 INL 分別為+0.72/-0.68 LSB 和+0.76/-0.68 LSB。在輸入頻率為 499.0 MHz 且在 1 GS/s 的轉換率下時，SNDR 和 SFDR 分別為 33.39 dB 和 41.03 dB。然而在輸入頻率為 9.7 MHz 且在 900 MS/s 的轉換率下時，SNDR 和 SFDR 分別為 35.17 dB 和 49.50 dB。在 1 V 的電壓和 1 GS/s 的轉換率下的功率消耗為 62 mW。

全部的晶片面積大小為 0.89 mm²，然而主動電路所占的面積只有 0.30 mm²。

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II

Abstract

This thesis adopts incomplete-settling technique and proposes background sampling-point calibration to realize 6-bit, 1GS/s pipelined ADC. Incomplete-settling technique with proposed background sampling-point calibration allows low-gain and low-bandwidth opamp to be used and lowers the power consumption of opamp.

This prototype ADC is fabricated in TSMC 65nm CMOS general-process.

According to measurement results, this prototype ADC exhibits DNL of +0.72/-0.68 LSB and INL of +0.76/-0.68 LSB at sampling rate of 1 GS/s. SNDR and SFDR are 33.39 dB and 41.03 dB at 1 GS/s with 499.0 MHz input frequency. But at 900 MS/s with 9.7 MHz input frequency, SNDR and SFDR are 35.17 dB and 49.50 dB. The power consumption is 62 mW at 1 V supply voltage and 1 GS/s sampling rate. Active area is 0.30 mm², and whole chip with pads occupies 0.89 mm².

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III

List of Figures

Chapter 2

Fig. 2-1 transfer curve with (a) offset error (b) gain error ... 4

Fig. 2-2 transfer curve with DNL and INL ... 5

Fig. 2-3 flash ADC architecture ... 9

Fig. 2-4 successive-approximation ADC architecture ... 10

Fig. 2-5 pipelined ADC architecture ... 12

Fig. 2-6 continuous-time delta-sigma ADC architecture ... 13

Chapter 3 Fig. 3-1 conventional 1.5-bit pipelined ADC i stage ... 13 ^th Fig. 3-2 relation of ωp, ω_{− dB}₃ ^{, and} ωu loop_ in Bode plot ... 19

Fig. 3-3 (a) interstage gain error 0.8 at each stage (b) reference voltage of each stage multiplies 0.8 ... 21

Fig. 3-4 G is bigger than 8 is to create a cross point where _fix G_eff( )t_s is exactly 8 24 Fig. 3-5 ADC architecture with background sampling-point calibration ... 25

Fig. 3-6 sampling-point is adjusted to let G_eff( )t_s be 2 ... 27

Fig. 3-7 sampling-point calibration algorithm ... 28

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VIII

Fig. 3-8 SNDR v.s. interstage gain G_eff( )t_s in behavior simulation ... 29

Fig. 3-9 MDAC in (a) sampling phase (b) the beginning of amplification phase ... 32 Fig. 3-10 (a) sampling network (b) equivalent model ... 35 Chapter 4

Fig. 4-1 residue plot of (a) conventional 1.5-bit stage (b) 2-bit stage with folded-residue technique which uses comparators without offset and with maximum

8 Vref

±

offset ... 40 Fig. 4-2 block diagram of MDAC ... 42 Fig. 4-3 normalized G_norm is expressed as a function of A₀ with different G .... 44 _fix Fig. 4-4 circuit implementation of (a) opamp (b) bias circuit (c) CMFB circuit ... 45 Fig. 4-5 ac analysis of MDAC and opamp when output swing is 0 ... 46 Fig. 4-6 +V_x for all input range ... 47 Fig. 4-7 (a) A_o and ωu changes with output swing (b) residue plots of ideal and

actual transfer curve (c) normalized +V_{z norm}_{_} defined as the voltage difference between ideal and actual transfer curve ... 49 Fig. 4-8 (a) block diagram of sub-ADC (b) circuit implementation of comparator .... 52 Fig. 4-9 (a) block diagram of clock generator (b) block diagram of DTC ... 54

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IX

Fig. 4-10 delay of DTC with Sel v.s. binary digital control bits x₅, , , , , x₄ x₃ x₂ x₁ x₀ in decimal expression ... 56 Fig. 4-11 (a) block diagram of calibration circuits (b) residue plot of the first replica

stage (c) residue plot of the second replica stage ... 59 Fig. 4-12 IOS technique is used (a) in sampling phase (b) in amplification phase ... 61 Fig. 4-13 circuit implementation of calibration comparator with offset calibration ... 62 Fig. 4-14 embedded calibration offset v.s. y ... y₃ ₀ (or z ... z₃ ₀) ... 63

Fig. 4-15 block diagram of (a) digital loop filter (b) the first sub-filter (c) the second sub-filter ... 66 Fig. 4-16 timing arrangement of MDAC ... 68 Fig. 4-17 modifying action in duration 5 to eliminate memory effect due to

opamp-sharing technique ... 69 Fig. 4-18 DNL and INL of ADC @ Fs =1 GS/s, Fin =492.1 MHz ... 71 Fig. 4-19 FFT test of ADC @ Fs =1 GS/s, Fin =492.1 MHz ... 72 Chapter 5

Fig. 5-1 floor plan of (a) ADC (b) one of all the stages ... 75 Fig. 5-2 layout of ADC ... 75

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X

Fig. 5-3 schematic of analog input on PCB ... 77

Fig. 5-4 schematic of reference voltages on PCB ... 78

Fig. 5-5 schematic of power supplies on PCB ... 79

Fig. 5-6 test setup ... 80

Fig. 5-7 die photo of ADC ... 81

Fig. 5-8 DNL and INL of ADC (a) @ Fs =900 MS/s, Fin =9.7 MHz (b) @ F_s = 1 GS/s, Fin =499.0 MHz ... 83

Fig. 5-9 FFT test of ADC (a) Fs =900 MS/s, Fin =9.7 MHz (b) @ F_s = GS/s, 1 =10.7 Fin MHz (c) @ F_s = GS/s, 1 Fin =499.0 MHz ... 86

Fig. 5-10 F v.s. dynamic performance @ _s Fin =10.7 MHz ... 86

Fig. 5-11 F v.s. dynamic performance @ _in F_s = GS/s ... 87 1 Fig. 5-12 ENOB v.s. binary digital control bits x₅, , , , , x₄ x₃ x₂ x₁ x₀ in decimal expression with Sel of DTC set 0 @ F_s = GS/s , 1 Fin =10.7 MHz ... 87

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XI

List of Tables

Chapter 4

Table 4-1 timing arrangement ... 70 Table 4-2 performance of ADC ... 72 Chapter 5

Table 5-1 functions of the 45 pins of ADC ... 77 Table 5-2 performance of ADC ... 88 Table 5-3 comparison of 5-bit to 8-bit resolution pipelined ADC ... 89

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1

Chapter 1 Introduction

1.1 Motivation

High-speed applications such as magnetic and optical read channels, serial-link receivers, and ultra-wideband (UWB) radios need fast ADC with low resolution.

Pipelined ADC architecture has the advantages of high sampling rate and low input capacitance and is adopted in this thesis. Opamp in pipelined ADC is a key building block. However, it is also a power-hungry block. Two main approaches about opamp are researched to lower the power consumption of pipelined ADC. The first approach tries to reduce the power consumption of opamp by using circuit techniques such as incomplete-settling technique [1][2], correlated-level-shifting (CLS) technique [3], opamp-sharing technique [4], capacitor-sharing technique [5], and time-sharing technique [6]. The second approach attempts to replace opamp by introducing modified architectures such as comparator-based architecture [7], charge-pump-based architecture [8], and ring-oscillator-based architecture [9]. This thesis follows the first approach. It adopts incomplete-settling technique and proposes background sampling-point calibration to decrease the power consumption of opamp.

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1.2 Thesis Organization

This thesis contains six chapters. In chapter one, it describes motivation and thesis organization. In chapter two, it gives the overview of the basic knowledge of ADC. Chapter three discusses different calibrations for incomplete-settling technique and proposed ADC architecture with some non-idealities. Chapter four introduces proposed building blocks with analysis, circuit implementation, and simulation results.

Measurement results are shown in chapter five. Finally, conclusions about this thesis are made in chapter six.

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Chapter 2 Fundamentals of ADC

2.1 Introduction

Some important performance metrics about the static and dynamic performance of ADC will be defined. And a number of ADC architectures will be described.

2.2 Performance Metrics

2.2.1 Static Performance

2.2.1.1 Offset and Gain Error

Offset error is the shift of actual transfer curve from ideal transfer curve shown in Fig. 2-1(a). And gain error is the difference of the slopes of actual transfer curve and ideal transfer curve when offset error is zero shown in Fig. 2-1(b).

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(a) (b) Fig. 2-1 transfer curve with (a) offset error (b) gain error

2.2.1.2 Differential and Integral Nonlinearities (DNL, INL)

Differential nonlinearity (DNL) is defined as the difference of each actual transition level width and ideal transition level width without offset and gain error.

DNL at code n is given as:

1 1 , 0 (2^N 1)

n n

LSB

V V

DNL n

V

+ −

= − ≤ ≤ − (2.1)

where V is actual transition point of digital output code n, and N is the resolution of _n ADC. V_LSB is amplitude voltage of 1 LSB, so DNL is expressed by LSB.

Integral nonlinearity (INL) is defined as the deviation of actual transfer curve from an ideal straight line and is also expressed by LSB. INL at code n is said to be

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5

the width difference of actual transition point n and ideal transition point n. Summing up DNL from code 0 to code n is another way to evaluate INL:

1

( ) ( )

n

i

INL n DNL i

=

∑

(2.2) DNL and INL are shown in Fig. 2-2.

Fig. 2-2 transfer curve with DNL and INL

DNL and INL are sometimes said to be the maximum value.

2.2.2 Dynamic Performance

Dynamic performance is based on FFT analysis. A sine wave as the analog input of ADC is applied, and the digital output of ADC is processed by FFT analysis. The

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total power of digital output can be sorted into three parts. The first part is signal power. The second part is harmonic power. The number of harmonics which are included in harmonic power depends on individual definition. The third is noise power. Noise power is calculated by subtracting signal power and harmonic power from total power.

2.2.2.1 Signal to Noise Ratio (SNR)

Signal to noise ratio (SNR) is the ratio of signal power to noise power. SNR is written as:

10 log

dB

signal power SNR noise power

⎛ ⎞

= ⎜ ⎟

⎝ ⎠ (2.3)

2.2.2.2 Total Harmonic Distortion (THD)

Total harmonic distortion (THD) is the ratio of harmonic power to signal power.

The first five harmonics are included in harmonic power in this thesis. THD is expressed as:

10 log

dB

harmonics power

THD signal power

⎛ ⎞

= ⎜ ⎟

⎝ ⎠ (2.4)

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2.2.2.3 Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range (SFDR) is the ratio of signal power to the largest harmonic power. SFDR is mentioned as:

10 log

largest harmonic power

dB

signal power

SFDR ⎛ ⎞

= ⎜ ⎟

⎝ ⎠ (2.5)

2.2.2.4 Signal to Noise and Distortion Ratio (SNDR) and Effective Number of

Bits (ENOB)

Signal to noise and distortion ratio (SNDR) is the ratio of signal power to noise power and harmonic power. SNDR is described as:

10 log

dB

signal power

SNDR noise power harmonics power

⎛ ⎞

= ⎜⎝ + ⎟⎠ (2.6)

Effective number of bits (ENOB) is a measure based on SNDR and is calculated as:

1.76 6.02

dB bit

ENOB SNDR −

= (2.7)

2.2.2.5 Figure of Merit (FoM)

Figure of Merit (FoM) is the important performance metric of ADC in terms of power, speed and accuracy. FoM is defined as:

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2^ENOB 2 _in Power

FoM = f

× (2.8)

2.3 ADC Architectures

2.3.1 Flash ADC Architecture

Flash ADC architecture is shown in Fig. 2-3. It contains several 2^N − 1 comparators where N is the resolution of ADC and a decoder. The analog input of flash ADC is compared with reference voltages generated by resistor-ladder simultaneously with the comparators. The differences of the analog input and the reference voltages are amplified to digital levels, and thermometer code is generated.

Then the thermometer code is converted to binary code by the decoder. Moreover, preamplifiers are often added in front of the comparators to decrease input-referred offset. Flash ADC achieves the fastest sampling rate because of parallel processing.

However, when the resolution of flash ADC increases, power and area consumption increase exponentially. Therefore, flash ADC is usually implemented in low resolution and high-speed design.

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DN-1

DN-2

DN-3

D0

2^N-1 Comparators Vin

Vref+

Vref-

R

Thermometer code

Fig. 2-3 flash ADC architecture

2.3.2 Successive-approximation ADC Architecture

Successive-approximation ADC architecture is shown in Fig. 2-4. It is composed of a front-end sample-and-hold amplifier (SHA), a comparator, a successive-approximation (SA) control logic, and a DAC. It applies binary search algorithm to resolve the digital output of successive-approximation ADC. With binary search algorithm, successive-approximation ADC halves the maximum difference of

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the analog output of the SHA which is V_SHA and the analog output of the DAC which is V_DAC in each step. In the first step, the registers of the SA control logic are set

100000 for 6-bit resolution for example, and then V_DAC is set 2 Vref

. The comparator compares V_SHA with V_DAC to make a decision and control the SA control logic. If

VSHA is larger than V_DAC, the register of MSB is still 1. In the second step, the registers of the SA control logic is set 110000 and the above steps are repeated.

Successive-approximation ADC is N times where N is the resolution of ADC slower than flash ADC. However, offset of the comparator is independent of the linearity of successive-approximation ADC because only one comparator is used.

Successive-approximation ADC is usually implemented in low-to-medium resolution and low-power design.

Fig. 2-4 successive-approximation ADC architecture

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2.3.3 Pipelined ADC Architecture

Pipelined ADC architecture is shown in Fig. 2-5. It consists of a series of stages.

Each stage is made up of a SHA, a sub-ADC, a sub-DAC, and an amplifier. It mainly operates in two phases which are amplification phase and sampling phase. When the i stage is in amplification phase, the (th i−1)^th and (i+1)^th stages are in sampling

phase, and vice versa. When the i stage is in amplification phase, assuming that the ^th resolution of the i stage is M-bit, it generates an M-bit digital output and a residual ^th voltage, and then the amplifier amplifies the residual voltage by 2^M⁻¹ times to a residue output sampled as the input of the (i+1)^th stage. When the i stage is in ^th sampling phase, it samples the residue output of the (i−1)^th stage. This arrangement lets all stages of pipelined ADC work concurrently, so sampling rate is independent of the number of stages of pipelined ADC. Due to amplification between stages, critical accuracy is in the first stage, and accuracy of later stages is relaxed. Pipelined ADC is usually implemented in medium-to-high resolution and high-speed design.

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Fig. 2-5 pipelined ADC architecture

2.3.4 Continuous-time Delta-sigma ADC Architecture

Continuous-time delta-sigma ADC architecture is shown in Fig. 2-6. It is comprised of a continuous-time delta-sigma modulator and a digital decimation filter.

The continuous-time delta-sigma modulator is a feedback loop which includes a low-resolution ADC, a low-resolution DAC, and a continuous-time integrator. It adopts over-sampling and noise-shaping technique [10] to improve SNR. With over-sampling technique, the analog input of ADC is sampled with sampling rate much higher than Nyquist-rate. This spreads quantization noise power to bandwidth of sampling rate and leaves less quantization noise power in signal-band. With noise-shaping technique, the feedback loop pushes quantization noise power to high-frequency and also leaves less quantization noise power in signal-band. The

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digital decimation filter removes quantization noise power out of signal-band to obtain the digital output of ADC. Continuous-time delta-sigma ADC is usually implemented in high resolution and low-power design.

Fig. 2-6 continuous-time delta-sigma ADC architecture

2.4 Summary

First, static and dynamic performance are introduced. Static performance includes offset, gain error and DNL, and INL. Dynamic performance includes SNR, THD, SFDR, SNDR, ENOB , and FoM. Second, three ADC architectures which contains flash ADC, successive-approximation ADC, pipelined ADC, and

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continuous-time delta-sigma ADC are mentioned and applied according to different applications.

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Chapter 3 Proposed Background Sampling-point

Calibration for Pipelined ADC Using

Incomplete-settling Technique

3.1 Introduction

As described in 2.3.3, Fig. 3-1 shows the conventional 1.5-bit pipelined ADC i ^th stage which contains sub-ADC and MDAC. Sub-ADC is composed of two comparators and a decoder. MDAC which realizes the function of SHA, sub-DAC, and an amplifier is composed of opamp, sampling capacitor C , feedback capacitor _s

C , and a multiplexer. f V_in and V_ref are the analog input and the reference voltage of ADC, respectively. In sampling phase, switch S₁ is on. Switches S₂ and S₃ connect the residue output V_{out i}_{_} ₋₁ of the (i−1)^th stage to C and _s C . Then _f

_ −1 out i

V is sampled as the input V_{in i}_{_} of the i stage. Sub-ADC compares ^th V_{out i}_{_}₋₁

with 4 Vref

± in the end of sampling phase to decide which voltage (+V_ref or 0 or

Vref

− ) is connected to the output of the multiplexer. In amplification phase, S₁ is off.

S2 and S₃ respectively connect C and _f C to the outputs of opamp and the _s output of the multiplexer. Assuming that the system has only one pole ωp

contributed by opamp, the residue output V_{out i}_{_} ( )t of the i stage is described as: ^th

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_ _

0

_ 1

( ) (1 )( 1 )(1 )[ ( ) ]

1 1

1,

4 0,

4 4

1, >

4

t

s s

out i in i i ref

f s f

ref out i

ref ref

i out i

ref

out i

C C

V t e V D V

C C C

A if V V

V V

D if V

if V V

τ

β

−

= + − − ⋅

+ +

⎧+ > +

⎪⎪

=⎪⎨ + > > −

⎪⎪

− −

⎪⎩

(3.1)

A is dc gain of opamp, and 0 β(= )

+ +

f

s f p

C

C C C , where C is the parasitic _p capacitance of the inputs of opamp, is feedback factor. τ is time constant and ¹

τ is closed-loop ω−₃dB( (1= +A₀β ω) p). ¹

τ is equal to loop-gain unit gain bandwidth

_ ( 0 )

ωu loop = Aβωp if loop-gain dc gain A₀β is much larger than 1. Fig. 3-2 shows

the relation of ωp, ω_{− dB}₃ ^{, and}ωu loop_ in Bode plot. D_i is a digital code. Usually

A0β is much larger than 1, and (3.1) can be approximately rewritten as:

_ _

0

( ) (1 )(1 1 )(1 )[ ( ) ]

t

s s

out i in i i ref

f s f

C C

V t e V D V

C A C C

β τ

−

+ − − − ⋅

+ (3.2)

Assuming that C and _s C are matched and not taken into consideration, there are _f two error terms which are static error (

0

1 1 Aβ

− ) caused by finite dc gain of opamp and

dynamic error (1 ^τ

− − t

e ) caused by insufficient time. If V_{out i}_{_} has to conform to 1

2LSB of N-bit accuracy, two limits about static error and dynamic error have to be obeyed:

static error limit:

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1 0

1 1

s 2N

ε A

β ⁺

= < (3.3)

dynamic error limit:

1

1 2 ε = ⁻τ^s < ₊

t

d e N (3.4) where t is settling time which corresponds to _s 1

2LSB of N-bit accuracy.

For example, for 6-bit resolution, 1GS/s sampling rate design with conventional 1.5-bit stages, assuming that t is 200 ps, the requirements of the first stage (N=5 _s because 1 bit is already resolved by the first stage) for A of opamp is about 42.1 dB ₀

( 1

β because of 1.5-bit stage) and for unit gain bandwidth 2 ωu(=A₀ωp) of opamp is about 6.6 GHz (τ =48.1 ps). It will consume a lot of power for opamp to achieve the above requirements.

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Multiplexer

2-bit

Decoder

A

Stage 1 Stage 2 Stage N

Digital Correction

Dout

Stage i

2-bit Sub-ADC

MDAC

_ out i

V

S1

Cf

Cs

Cp

S2

S3

Vref

+ 0 −Vref _ 1

out i

V ₋

4 Vref

+ 4 Vref

−

Vin

Fig. 3-1 conventional 1.5-bit pipelined ADC i stage ^th

ω Amplitude

A0

ωp

0 u

A p

ω ω

= A0β

_

0 u loop

A p

ω βω

=

3

(1 0 )

dB

A p

ω

β ω

−

= +

0

1 0

A A β +

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Fig. 3-2 relation of ωp, ω_{− dB}₃ ^{, and} ωu loop_ in Bode plot

3.2 Incomplete-settling Technique

3.2.1 Concept of Incomplete-settling Technique

Two parameters G_fix and G_eff( )t are introduced here. G_fix represents interstage gain defined by hardware implementation ( _fix 1 ^s

f

G C

= +C when conventional closed-loop 1.5-bit stage is used for example). G_eff( )t represents actual interstage gain at time t . Moreover, G and _fix G_eff( )t are related in closed-loop

topology:

0

( ) ( 1 )(1 )

1 1

τ

β

−

≡ −

+

t

eff fix

G t G e

A

(3.5)

Conventionally, ( )G_eff t_s is equal to G with small static and dynamic error limited _fix by (3.3) and (3.4). Opamp dc gain A₀ and unit gain bandwidth ωu(= A₀ωp)

requirements are based on (3.3) and (3.4):

1 0

2^N

A β

> + (3.6)

0

1 ( 1) ln 2

u p

s

A N ω ω t

βτ β

= > + (3.7)

If the requirements for opamp A₀ and ω can be reduced, the power consumption _u

of opamp can hence be reduced. This is the concept of incomplete-settling technique [1][2]. Incomplete-settling technique ignores these requirements and uses opamp

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which has smaller A and ₀ ω than (3.6) and (3.7) to lower the power consumption _u of opamp. However, from (3.3), if A decreases, ₀ εs will increase. Similarly, from

(3.4), if ωu decreases, εd will increase (because ε = ⁻^τ^s ⁻^ω^u^_^{loop s} = ⁻^βω^{u s}

t

t t

d e e e ), too.

That is, εs and εd will become larger and larger with the decrease of A and ₀ ωu. Also, from (3.5), G_eff( )t_s will become smaller and smaller than G_fix. If the big difference between G_fix and G_eff( )t_s can be compensated during ADC conversion

by digital reference calibration [1], digital signal processing calibration [2], and proposed sampling-point calibration, incomplete-settling technique can be adopted, and the power consumption of opamp can be declined.

3.2.2 Prior Work 1: Digital Reference Calibration

In prior work 1 [1], 1.5-bit stage at each stage uses closed-loop topology where

Gfix is 2 and G_eff( )t_s is 1.6 (no need to be precise because settling behavior changes with PVT and digital reference calibration can accommodate this variation) at fixed

t . Tuning the reference voltage of each stage is one method to compensate the s

difference between G_fix and G_eff( )t_s . There is interstage gain error defined as ( ) 1.6

( 0.8)

2

eff s

fix

G t

G = = at each stage shown in Fig. 3-3 (a), and the reference voltage of

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each stage also multiplies 0.8, no error will be induced during ADC conversion shown in Fig. 3-3 (b).

(0.8)V_ref Vref

_ 1

Vout V_out_{_ 2}

Vin

(a)

(0.8)V_ref 2

(0.8)V_ref

_ 1

Vout

(0.8)V_ref

_ 2

Vout

_ 2 _ 1

in out

V V Vin

Vref

(b)

Fig. 3-3 (a) interstage gain error 0.8 at each stage (b) reference voltage of each stage multiplies 0.8

In practice, the reference voltage of each stage can be adjusted independently to avoid mismatches between stages and achieve better performance. Digital reference

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22

calibration based on maximizing SNDR is adopted to find the right reference voltage which corresponds to each stage. However, there are some disadvantages. First, because of interstage gain error, the reference voltage of each stage shrinks stage by stage. Assuming that noise except quantization noise remains unchanged, the effect of the noise is bigger than convention, so ADC performance cannot be as good as convention. Second, the calibration is so complex as to be not embedded on-chip.

Third, the calibration is foreground and cannot adapt to environment variation continuously.

3.2.3 Prior Work 2: Digital Signal Processing Calibration

In prior work 2 [2], 3.5-bit stage at the first stage uses open-loop topology.

Because of open-loop topology, assuming that the system has only one pole

0

( 1 )

ωp =

R CL where R is output resistance and ₀ C is load capacitor, and the pole _L is contributed by opamp, the residue output V_{out i}_{_} of the i stage in amplification ^th

phase is described as:

_ ( ) 0(1 )[ _ ]

2

open

t

ref

out i in i i

V t A e^τ V D V

−

= − − ⋅ (3.8)

where ¹ τopen

is ωp. G (_fix G_fix = in open-loop topology) and A₀ G_eff( )t are related

in open-loop topology:

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23

( ) (1 ^τ )

−

≡ − ^open

t

eff fix

G t G e (3.9)

Gfix is bigger than 8 and ideally G_eff( )t_s is 8 (no need to be precise because settling behavior changes with PVT and digital signal processing calibration can accommodate this variation) at fixed t . The reason why _s G is bigger than 8 is to _fix create a cross point where G_eff( )t_s is exactly 8 shown in Fig. 3-4. Because settling behavior varies with PVT, G_eff( )t_s may not be 8 at fixed t . Digital signal _s

processing calibration which directly processes the digital output of ADC is adopted to compensate linear error (linear because from (3.8) and (3.9), G_eff( )t_s is independent of V_{in i}_{_} ) caused by the variation of G_eff( )t_s . The calibration has

disadvantages of complication and off-chip.

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24 ts

( ) 8

eff s

G t =

Fig. 3-4 G_fix is bigger than 8 is to create a cross point where G_eff( )t_s is exactly 8

3.3 Proposed Pipelined ADC Architecture and

Background Sampling-point Calibration

3.3.1 Pipelined ADC Architecture

Fig. 3-5 shows 6-bit, 1GS/s pipelined ADC architecture. It is composed of four identical 2-bit stages and a 2-bit flash at the end for ADC conversion. The digital codes resolved by each stage are aligned and added to obtain the digital output of ADC. Calibration circuits which contain two replica stages, a calibration comparator

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25

with offset calibration, and a digital loop filter are added for background sampling-point calibration. Why two rather than one replica stage is used is according to analysis later. The replica stages are the same as those stages for ADC conversion.

Moreover, a global clock generator which produces clock phases is shared among all the stages.

Vin _ in known

V

2 Vref

Dout

Fig. 3-5 ADC architecture with background sampling-point calibration

3.3.2 Background Sampling-point Calibration

All the stages use incomplete-settling technique with closed-loop topology. From (3.5), there are some parameters such as G , _fix β , A , 0 τ ^{, and}t chosen to tune s

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26

eff( )s

G t . First, since G_fix is roughly equal to 1

β ^(because ¹

s fix

f

G C

= +C and 1

β

+ +

= ^s ^f ^p

f

C C C

C when conventional closed-loop 1.5-bit stage is always used for example in this section), tuning G and _fix β is considered together. G and _fix β

are related to capacitor ratio [11]. The variable capacitor ratio increases circuit complexity and parasitic capacitance in the signal path of MDAC due to additional switches for tuning, and this decreases sampling rate. Second, tuning A₀ is considered. A₀ is tuned by changing the bias point of opamp [12]. Also, the variable

bias point rises circuit complexity and parasitic capacitance in the signal path of MDAC. Third, tuning τ is considered. Because τ is

3 0

1 1

( )

(1 )

ω₋dB ⁼ +Aβ ωp , τ can be tuned by tuning A₀ and β considered above. Fourth, tuning t is _s considered. t is tuned by adding delay elements with variable delay into clock _s generator. That is, sampling-point can be adjusted. No extra circuit is required in the signal path of MDAC, and this achieves fast sampling rate. Besides, the tuning range of ( )G_eff t_s is wider by altering sampling-point than the capacitor ratio or the bias point of opamp with less circuit. Finally, G is 16 and _fix G_eff( )t_s is 2 according to

analysis later. Although settling behavior varies with PVT, sampling-point can be adjusted to let G_eff( )t_s be 2 shown in Fig. 3-6.

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27 ( ) 2

eff s

G t =

τ1

τ2

τ3

1

ts t_s₃

2

ts

3 2 1

τ ^>τ ^>τ

3 2 1

s s s

t >t >t

Fig. 3-6 sampling-point is adjusted to let G_eff( )t_s be 2

Sampling-point calibration is proposed to operate automatically with the help of calibration circuits (To describe calibration algorithm shown in Fig. 3-7, two replica stages are reduced to one which is conventional closed-loop 1.5-bit stage for simplicity for example in this section). Before the beginning of sampling-point calibration, a calibration comparator is calibrated to eliminate offset, and then sampling-point calibration starts. First, a known analog input V_{in known}_{_} set

4 Vref

is sampled by the replica stage. After being amplified by the replica stage, the residue output Vout replica_{_} ( )t of the replica stage at s t is compared with an analog value set _s

2 Vref

with the calibration comparator.

2 Vref

corresponds to 4 Vref

, assuming that

eff( )s

G t is 2. If Vout replica_{_} ( )t is larger than s

2 Vref

, or in other words, G_eff( )t_s is larger than 2, sampling-point is adjusted to let t and _s G_eff( )t_s decrease, and vice

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28

versa. Finally, G_eff( )t_s of all the stages is 2 at decided sampling-point. Because the

replica stage is independent of those stages for ADC conversion, sampling-point calibration is background and never stops.

( ) 2

eff s

G t <

_ 4

ref in known

V =V

( ) 2

eff s

G t >

_ ( )

2

ref out replica s

V t >V

s s

t = ++t t t_s = −+t_s t

_ ( )

out replica s

V t

(G_eff( )t_s =G_eff( )t_s ++G) (G_eff( )t_s =G_eff( )t_s −+G)

eff( )s

G t

Fig. 3-7 sampling-point calibration algorithm

3.4 Non-Idealities of Background Sampling-point

Calibration

Non-idealities of sampling-point calibration are discussed in terms of either voltage or gain. In terms of voltage, if the residue output V_{out i}_{_} ( )t of the i stage ^th

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29

want to satisfy 1

2LSB of N-bit accuracy, the voltage error of V_{out i}_{_} ( )t caused by separate non-idealities is required to be less than ₁

2 ⁺

ref N

V . In terms of gain, Fig. 3-8

shows SNDR v.s. interstage gain G_eff( )t in behavior simulation. _s G_eff( )t from 1.90 _s

to 2.07 ensures maximum reduction by 3 dB from ideal SNDR of 37.88( 6.02 6 1.76)= ⋅ + dB of 6-bit ADC. That is, the stage gain error of each stage caused by separate non-idealities should be less than 0.07 to obtain SNDR of

34.88( 6.02 6 1.76 3= ⋅ + − =37.88 3)− dB above in behavior simulation.

30 31 32 33 34 35 36 37 38 39

1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 2.2

SNDR

SNDR (dB)

eff( )s

G t

Fig. 3-8 SNDR v.s. interstage gain G_eff( )t in behavior simulation _s

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30

3.4.1 Opamp Slewing and DC Gain, Unit Gain Bandwidth

Variation with Output Swing

Incomplete-settling technique is based on linear amplification. However, there are two sources which cause non-linear amplification. First, opamp slewing is one source. Opamp slewing happens when the voltage difference of the inputs of opamp exceed 1.4 V [13] where _ov V_ov is the overdrive voltage of the input differential pair of opamp. Opamp slewing is most likely to occur in the beginning of amplification phase (φ₂). Fig. 3-9 (a) and (b) show that conventional 1.5-bit MDAC is in sampling phase (φ₁) and in the beginning of φ₂, respectively. The resultant initial voltage difference + of the inputs of opamp in the beginning of V_x φ₂ is calculated by charge conservation [1] (In the end of φ₁, charge is 2C V_u _{in i}_{_} . In the beginning of φ₂^, charge is C D V_u( _i⋅ _ref −+V_x) (+ C_eq+C_p)(−+V .): _x)

2C V_u _{in i}_ =C D V_u( _i⋅ _ref −+V_x) (+ C_eq+C_p)(−+V _x) (3.10) where V_{in i}_{_} is the input of the i stage, ^th C is the capacitor value of u C and _s C , _f

C is load capacitor, L C is _eq ^u ^L

u L

C C

C +C which is series connection of C and _u C , _L and C is the parasitic capacitance of the inputs of opamp. _p

(3.10) is rearranged as:

2 _

− + ⋅

= + +

+ _x ^u ^{in i} ^u ⁱ ^ref

u eq p

C V C D V

V C C C (3.11)

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31

And + is required to be less than 1.4 V_x V no matter what _ov V_{in i}_{_} is to ensure that non-linear amplification will not take place. For example, assuming that V is 100 _ov mV, + should be less than 140 mV for all input range. V_x

Second, opamp dc gain A and unit gain bandwidth ₀ ωu(= A₀ωp) variation with output swing are another source. From (3.1), (1+ ^s)

f

C

C is replaced with G , _fix

and ( )

+

s

s f

C

C C is replaced with 1

2 for generalization. (3.1) is rewritten as:

_ _

0

( ) ( 1 )(1 )( )

1 2

1

t

ref

out i fix in i i

V t G e V D V

A

τ

β

= − − − ⋅

+

(3.12)

A and 0

0

( 1 )

(1 )

τ ⁼ +A β ωp ideally are constants with output swing to guarantee

linear amplification. However, in practice, A and ₀ τ will change with output swing and are represented as A and ₀' τ for discrimination: '

0'= 0−+ 0[ out i_ ( )]

A A A V t (3.13)

' [ _ ( )]

τ τ τ= ++ Vout i t (3.14)

where A and ₀ τ denote that A and 0' τ have 0 output swing. ' Vout swing i_ _ ( )t stands for the output of the i stage with ^th A and ₀' τ and is expressed as: '

'

_ _ _

0

( ) ( 1 )(1 )( )

1 2

1 '

t

ref

out swing i fix in i i

V t G e V D V

A

τ

β

= − − − ⋅

+

(3.15)

Output voltage error + due to V_y A and ₀ τ variation with output swing , for given

t , is written as: s

_ _ ( ) _ ( )

= − =

+

s

y out swing i out i t t

V V t V t (3.16)

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32

If V_{out i}_{_} want to fulfill 1

2LSB of N-bit accuracy, + is required to be less than V_y 2 ⁺1

ref N

V no matter what V_{in i}_{_} is. For example, for 6-bit resolution design with

conventional 1.5-bit stages, + of the first stage (N=5 because 1 bit is already V_y

resolved by the first stage) should be less than _{5 1} 2 Vref

+ for all input range.

_ 1 out i

V

₋

V

_out_{_}_i

C

L

C

p

C

u

C

u _

V

in i _

V

in i

(a)

i ref

D V ⋅

C

u

C

u

_ out i

V C

L

C

p

V

x

+

(b)

Fig. 3-9 MDAC in (a) sampling phase (b) the beginning of amplification phase

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33

3.4.2 Discrete Sampling-point and Clock Jitter

Because of discrete sampling-point which is controlled by digital control bits, the resolution of sampling-point need to be fine enough to achieve the required resolution of ADC with the existence of clock jitter. (3.5) is differentiated with time and expressed as:

0

( ) 1 1

( )( )

1 1

( 1 ) ( )

1 1

t eff

fix

fix eff

dG t

G e

dt

A

G G t

A τ τ

β

β τ

−

=

+

+ −

=

(3.17)

If there is sampling-point variation t+ introduced by discrete control and clock jitter, for given ideal sampling-point

c where G_eff(t_ideal) is exactly 2, stage gain error +G_x is expressed as:

0

( 1 ) ( )

1 1 ( )

( 1 ) 2

1 1

β τ

=

+ −

= =

+ −

=

+ + +

+

ideal

fix eff ideal

eff

x t t

fix

G G t

dG t A

G t t

dt

G

A t

(3.18)

From (3.18), the finer the resolution of sampling-point is and the bigger t_ideal is, the smaller +G is. For example, refer to Fig. 3-8, +_x G of each stage should be less _x than 0.07 to get SNDR of 34.88( 6.02 6 1.76 3= ⋅ + − =37.88 3)− dB above of 6-bit

ADC.

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34

3.4.3 Sampling Attenuation

Conventionally, the output of the i stage settles to required accuracy when the ^th (i+1)^th stage samples. That is, when the (i+1)^th stage samples, the output of the i ^th stage is almost a dc value. Therefore, RC delay in the sampling network of the

(i+1)^th stage does not cause error and the input of the (i+1)^th stage which samples

the output of the i stage is equal to that of the ^th i stage. However, because of ^th incomplete-settling technique, the output of the i stage is still amplifying when the ^th

(i+1)^th stage samples, and RC delay in the sampling network of the (i+1)^th stage will cause sampling attenuation G between the output of the _y i stage and the ^th

input of the (i+1)^th stage. The sampling network of each stage and equivalent model in φ₁ is shown in Fig. 3-10 (a) and (b).

_

( )

out i

V t

total

C

φ

1

φ

1

(a)

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賴傑帆 i Chieh-

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伴隨著背 類比數位 C Using ground S

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帆 Fan

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士 Ph.D.

月

研究所

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時間

t

致謝

摘要

Abstract

Contents

List of Figures

List of Tables

Chapter 1 Introduction

1.1 Motivation

1.2 Thesis Organization

Chapter 2 Fundamentals of ADC

2.1 Introduction

2.2 Performance Metrics

∑

2.3 ADC Architectures

2.4 Summary

Chapter 3 Proposed Background Sampling-point

Calibration for Pipelined ADC Using

Incomplete-settling Technique

3.1 Introduction

3.2 Incomplete-settling Technique

3.3 Proposed Pipelined ADC Architecture and

Background Sampling-point Calibration

3.4 Non-Idealities of Background Sampling-point

Calibration

V

V

C

C

C

C

V

V

D V ⋅

C

C

V C

C

V

+

( )

V t

使用不完校正的 gh-speed g Techni

學電機資碩

完全趨穩的高速導 d Pipelin

資訊學院碩士論文

穩技巧伴導管式類 ned AD

院電子工文

伴隨著背類比數位 C Using ground S

信樹博士 n-Shu, P

背景調整位轉換器 g Incom Samplin

整取樣時器