Chapter 4 Proposed Building Blocks and Circuit Implementation
4.2 Building Blocks and Circuit Implementation
4.2.1 MDAC
4.2.1.1 Folded-Residue
As described in 3.4.1, non-linear amplification is caused by opamp slewing and dc gain A , unit gain bandwidth o ωu(= A0ωp) variation with output swing. From (3.11), + is proportional to Vx Vin i_ which samples Vout i_−1. If the maximum output swing of each stage can be reduced, + can be reduced, too. That is, opamp Vx
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slewing is more impossible to occur. Moreover, A and 0
0
( 1 )
(1 )
τ = +Aβ ωp variation
are less severe because of the reduced maximum output swing. Therefore, folded-residue technique [14] is adopted to reduce the maximum output swing. Fig.
4-1 (a) shows residue plot of conventional 1.5-bit stage. The maximum output swing is ±Vref . By adding an additional comparator to each conventional 1.5-bit stage,
folded-residue technique can be realized to reduce the maximum output swing to
2 Vref
± , assuming that every comparator in each stage has no offset. Even if the
comparators in each stage are designed to achieve maximum 8 Vref
± offset, or 3-bit
accuracy, the maximum output swing is limited within 3 4 Vref
± . Residue plot of 2-bit
stage with folded-residue technique which uses comparators without offset and with maximum
8 Vref
± offset is shown in Fig. 4-1 (b). Folded residue technique reduces
the maximum output swing to ensure more linear amplification at the cost of an additional comparator to each stage.
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Fig. 4-1 residue plot of (a) conventional 1.5-bit stage (b) 2-bit stage with folded-residue technique which uses comparators without offset and with maximum
8 Vref
± offset
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4.2.1.2 Amplification Multiple
MDAC with incomplete-settling technique adopts 2-bit and flip-around architecture to achieve larger feedback factor β and faster speed. Assuming that sampling capacitors C and feedback capacitor s C are matched, the residue output f
_ ( )
diagram of MDAC of each stage (single-ended version for simplicity but fully-differential actual). It contains opamp, C , and s C . f C and s C have the f same capacitor value C . In sampling phase (u φ1), the residue output Vout i_−1( )t of the (i−1)th stage is sampled as the input Vin i_ of the i stage, and in amplification th phase (φ2), charge transfers to realize plus or minus to reference voltages and amplification.
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Fig. 4-2 block diagram of MDAC
Assuming that opamp with single stage has dc gain A and a pole 0
0
( 1 )
ωp = R CL
where R is output resistance and 0 C is load capacitor which contains the L capacitor seen by the outputs of opamp of this stage (1⋅C ) and the capacitors for u
sampling of next stage in amplification phase of this stage (Gfix⋅C ), u R and 0 C L
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where gm is transconductance of the input differential pair of opamp. From (4.2) and
(4.3), closed-loop 3 1 assumption, the larger Gnorm is, the faster the speed of amplification is. Refer to Fig.
4-3, Gnorm is a maximum when G is 12 or 16, and fix G is chosen 16. fix
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The circuit implementation of opamp, bias circuit, and CMFB circuits are shown in Fig. 4-4 (a), (b), and (c), respectively. Opamp employs two-stage topology rather than single-stage one because of its less dc gain Ao and unit gain bandwidth
( )
ωu = Aoωp variation with output swing. Bias circuit undergoes the same condition
as opamp. Vcmi is the common-mode voltage of the inputs of opamp. CMFB circuit use switched-capacitor topology owing to the existence of non-overlapping phases used in pipelined ADC architecture. There are two CMFB circuits for the outputs of the first and the second stage of opamp, respectively. Vcm is the common-mode voltage of the outputs of the second stage of opamp.
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Fig. 4-4 circuit implementation of (a) opamp (b) bias circuit (c) CMFB circuit
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Fig. 4-5 shows the ac analysis of MDAC and opamp when output swing is 0 in post-simulation. Opamp dc gain is 29.1 dB, and loop-gain dc gain is 2.3 dB.
Loop-gain phase margin is 125.9 degree. Each opamp consumes 4.5 mW, and input-referred offset of opamp is ±15 mV( 3σ ) in post-simulation.
Fig. 4-5 ac analysis of MDAC and opamp when output swing is 0
As described in 3.4.1, opamp slewing will cause non-linear amplification and should be avoided. Fig. 4-6 shows +Vx for all input range when V is 250 mV in ref post-simulation. The overdrive voltage Vov of the input differential pair of opamp is set 100 mV in post-simulation. Refer to Fig. 4-6, +Vx is much smaller than 1.4
( 140 )=
Vov mV . Therefore, opamp slewing will not take place.
47 -60
-40 -20 0 20 40 60
-250 -200 -150 -100 -50 0 50 100 150 200 250
_ in i
V
xV+ xV+
Fig. 4-6 +Vx for all input range
As described in 3.4.1, opamp dc gain Ao and unit gain bandwidth ωu(= Aoωp) vary with output swing. Fig. 4-7 (a) show how Ao and ωu change with output swing in post-simulation. Ao and ωu respectively change from 29.1 dB to 26.5 dB and from 5.64 GHz to 5.49 GHz when the absolute value of output swing changes from 0 mV to 250 mV. Fig. 4-7 (b) shows residue plots of ideal and actual transfer curve in post-simulation. Output voltage error +Vz defined as the voltage difference between ideal and actual transfer curve. Fig. 4-7 (c) shows normalized +Vz norm_ where +Vz is normalized to 5-bit accuracy (because 1 bit is already resolved by the first stage) in post-simulation. Refer to Fig. 4-7 (c), +Vz norm_ is within 0.21 LSB of
5-bit accuracy.
48 25
25.5 26 26.5 27 27.5 28 28.5 29 29.5
-250 -200 -150 -100 -50 0 50 100 150 200 250
dc gain
0A
5.4 5.45 5.5 5.55 5.6 5.65 5.7
-250 -200 -150 -100 -50 0 50 100 150 200 250
unit gain bandwidth
uω
(a)
49 actual transfer curve (c) normalized +Vz norm_ defined as the voltage difference
between ideal and actual transfer curve
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As described in 3.4.3, ts is 190 ps and Ctotal is 160 fF in post-simulation.
From (3.28), G is required be larger than 0.95 in post-simulation, so y τs should be smaller than 9.5 ps, and R1+R2 should be smaller than 59 Ω . R1 is above 21 Ω for all input range, and R2 is 30 Ω in post-simulation