Circuit Implementation

This section describes the transistor-level design of the critical building blocks for the proposed RMASH 2-1-11.5b ADC. The ADC was implemented in TSMC 2.5V, 0.25-µm, 1P5M, CMOS technology with metal-insulator-metal (MIM) capacitors.

3.3.1 SC Circuit Design

The SC diagram of the implemented circuit is shown in Figure 3.25. The fully differen-tial SC technique is preferred because of increased signal DR, higher immunity to clock and charge feed-through, and better rejection to the common-mode noise. The non-inverting in-tegrators are operated with two non-overlapping clock phases: in the phase ϕ1 the sampling capacitors CSiare charged, while in the phase ϕ2 this charge is transferred to the integrating capacitor CF i. The coefficients are realized as the capacitor ratios based on charge conser-vation [29]. To reduce the effect of the signal-dependent charge injection, the delayed clock phases ϕ1D and ϕ2D have been used [29]. Figure 3.26 shows the on-chip clock generator with two non-overlapping phases. The feedback loop is used to ensure the non-overlapping

Cs2M

Figure 3.25: The SC diagram of RMASH 2-1-11.5b.

Figure 3.26: Non overlapping two-phase clock generator.

function between ϕ1and ϕ2. All of the circuits are operated from a 2.5V supply voltage. The values of first-stage reference voltages used in the 1.5-bit quantizer and DAC are 2.15V and 0.35V while the values of second- and third-stage reference voltages are 1.7V and 0.8V. All the reference voltages are driven by on-chip reference buffers and are decoupled by off-chip capacitors.

3.3.2 OTA Circuit

According to Table 3.2, the proposed modulator requires the dc gain of 75-dB and the GBW of 300 MHz for the OTA with a supply voltage of 2.5 V. To meet the requirements, we chose a folded-cascode OTA with additional gain-boosting amplifier. By carefully design and sizing of the gain-boosting amplifiers, the induced nondominant pole can be located at 1GHz. As mentioned in Section II, the output swing of the first-stage integrators can be reduced by using the tri-level quantizer and the input feedforward path. Hence, for a supply voltage of 2.5 V, the required single-ended output swing of OTA is approximately 1 V.

Figure 3.27 shows the schematic of the folded-cascode OTA being used for the first-stage integrators. The single-ended output swing of OTA is 1.4 V, which can sufficiently accommodate the required output swing at the integrator outputs, and a dc gain of 75 dB is accomplished over the entire output range. The OTA, including gain-boosting and biasing circuits, dissipates 15 mW from a 2.5-V supply and achieves a GBW of 300MHz with a capacitive loading of 5 pF, while the phase margin is 75 degree. The total thermal noise contribution over 2.5-MHz signal bandwidth is about 12.6 µV. The SC common-mode feedback is used for designed OTA because it does not dissipate the static power. The capacitors used in the common mode feedback (CMFB) circuitry are properly chosen to

Va

Figure 3.27: Circuit schematic of the OTA.

maximize the gain bandwidth, and thus avoid the settling error. We also used the similar OTA for other stages, and it dissipates 0.7 times of the power consumption the first-stage OTA consumes.

3.3.3 First Stage Design

As mentioned in Chapter 2, the noise and distortion performance of a cascaded Σ∆

modulator is determined primarily by the noise and distortion performance of first stage.

The implementation of the first stage is therefore the most important task of the design.

Figure 3.28 illustrates the SC circuit diagram of the first stage of the RMASH 2-1-11.5b. Since the dynamic range of the modulator is targeted at 90-dB at the sampling rate of 70.4MHz, the sampling capacitor is chosen to be 1.5 pF and, accordingly, the integrating and resonator feedback capacitors are 3 pF and 0.375 pF, respectively. The closed-loop bandwidth of front-end integrator is about 255MHz, which is larger than three times the sampling frequency. Because the feedback gain of the tri-level DAC is equal to one, we can use the capacitor switching technique to eliminate coefficient mismatch. The share-capacitor switching technique is to have the input sampling and feedback DAC share a common sampling capacitor CS1 [46]. However, the dependent load on the reference voltage may cause harmonic distortion. In our work, we used a dummy SC network to reduce the

C_s2

Figure 3.28: Circuit implementation of the first-stage modulator.

distortion [47]. The output two-bit code of tri-level quantizer is used to switch A1, B1, and C1 at the integrating phase.

The summing circuit in front of the quantizer is implemented by using a passive SC network to avoid the use of additional OTA and save the power dissipation. The summed signal can be expressed as

VS(z) = CF F1Vin(z) + CF F2Int1(z) + CF F3Int2(z)

CF F1+ CF F2+ C_{F F3} , (3.32)

where CF F1, CF F2, and CF F3 are the capacitors for feedforward gains. According to behav-ioral simulation, the feedforward gains are not critical and can tolerate the variation up to 2%. This allows the use of small capacitance to implement the feedforward gains. We set the values of CF F1, CF F2, and CF F3 to 0.125 pF, 0.25 pF, and 0.5 pF, respectively. Note that the summed signal is scaled down by 1/7 when comparing with the parameters of Table 3.1 and Figure 3.4. In order not to affect the desired performance of the modulator, the reference voltages of the quantizers must be scaled down by a factor of 1/7 from the nominal value. This also scales down the quantizer step size, and hence increases the requirement of the comparator resolution. In our case, the required step size of the tri-level quantizer is about 150 mV. This requirement is feasible because, in practice, the CMOS comparator with preamplifier can provide a resolution better than 50mV.

Q

Q Q

Q

VR+

VR-C_Q0

CQ1

CQ0

C_Q1

CQ0

CQ1

CQ0

C_Q1

A

C

B

Vs+

Vs-Figure 3.29: Circuit implementation of tri-level quantizer.

3.3.4 Tri-Level Quantizer Circuit

The circuit diagram of tri-level quantizer is shown in Figure 3.29. As mentioned above, the SC network must scale down the reference voltages, VR+ and VR-, by a factor of 1/7.

So, we set the values of the capacitors CQ0 and CQ1 to 0.125 pF and 0.75 pF, respectively. In our design, we used a high-speed, high-accuracy CMOS comparator with preamplifier which is presented by [48]. The clock ϕ2A is used to control the generation of A1, B1, and C1. Because of the time-delay of AND gates, the non-overlapping interval of ϕ2A is limited to 1∼ 2ns when a sampling rate of 70.4 MHz.

Vdd=2.5V

V_b3

V_b2

V_b1

C_c

V_IN V_OUT

C_ext Off-chip V_OUT

I_SS

V_b4

Figure 3.30: The schematic of reference voltage buffer amplifier.

3.3.5 Reference Buffer

Since the first integrator samples the input signal, it draws a signal-dependent cur-rent from the voltage reference and introduces harmonic distortion due to the finite output impedance of reference buffers. A high-bandwidth reference voltage buffer with fast settling behavior during the integrating phase ϕ2 is required to deal with this problem. However, such kind of reference buffer is power-consuming especially for high signal-bandwidth design.

In this work, we use a class-A amplifier with an external capacitor to make output impedance low enough to meet desired linearity requirement [49]. The schematic of the class-A amplifier is shown in Figure 3.30. The output impedance of this amplifier increases with frequency due to its finite gain-bandwidth product. Thank to the large external capacitor, the output impedance remains low at high frequencies. In other words, the transient charge is delivered from the external capacitor and the reference voltage is controlled by the class-A amplifier.

By using this topology, the power consumption of reference buffers can be reduced at the cost of using large external decoupling capacitors. The buffers for the reference voltages of the second and third stages are similar to Figure 3.29, but dissipate approximately half of that of the first stage. This arrangement is practical because the settling errors of reference voltages in the second and third stages will be suppressed by the high-pass noise shaping of H1(z) and H2(z), respectively.

3.3.6 Cancellation Filter and Decimation Filter Circuit

The implementation of digital cancellation filter and decimation filter is based on the cell-based synthesis flow. According to the coefficients listed in Table 3.1, the transfer functions of the digital cancellation filters, H1(z) and H2(z), are show as follows:

H1(z) = 1 − 2z⁻¹+ 1.03125z⁻², (3.33)

H₂(z) = 1 − 3z⁻¹+ 3.03125z⁻²− 1.03125z⁻³. (3.34) Figure 3.31 illustrates the implementation structure of H1(z) and H2(z). By precision and error analysis, the output bit-width of digital cancellation filter is chosen to be eleven bits.

The following equations are the transfer functions of CIC filter and 31-tap FIR respectively:

CIC(z) = z⁻⁹³

1−z⁻⁴ 1−z⁻¹

´5

= z⁻⁴[(1 + z⁻¹)(1 + z⁻²)z⁻¹]⁴

·[(1 + z⁻¹+ z⁻²+ z⁻³)z⁻¹],

(3.35)

FIR(z) = a₀z⁻¹+ a₁z⁻²+ a₂z⁻³+ ... + a₃₀z⁻³¹, where a0 = a30 = −0.000061035; a1 = a29 = −0.0003662;

a2 = a28 = −0.000366211; a3 = a27 = 0.001464844;

a4 = a26 = 0.0036315918; a5 = a25 = −0.000823975;

a6 = a24 = −0.012054443; a7 = a23 = −0.010437012;

a8 = a22 = 0.019775390; a9 = a21 = 0.043701172;

a10 = a20 = −0.002899160; a11 = a19 = −0.09893799;

a12 = a18 = −0.088989258; a13 = a17 = 0.154602051;

a14 = a16 = 0.516235351; a15 = 0.692199707;

(3.36)

By precision and error analysis, the output bit-width of the CIC filter, FIR, and IIR are 19 bits, 16 bits and 16 bits, respectively. The fourth-order IIR is a Chebyshev Type-II filter.

The stability of the fourth-order Chebyshev filter is guaranteed by considering the signal swing and filter coefficients. The overall SNDR of the decimation filter is designed to be higher than 80 dB to satisfy the requirement of ADSL2+ performance.

Z^-1 Z^-1 Z^-1

Figure 3.31: (a) H₁(z) and (b) H₂(z) of Circuit implementation of the cancellation filters